TW200739600A - Multi-port memory device with serial input/output interface and control method thereof - Google Patents

Multi-port memory device with serial input/output interface and control method thereof

Info

Publication number
TW200739600A
TW200739600A TW096100499A TW96100499A TW200739600A TW 200739600 A TW200739600 A TW 200739600A TW 096100499 A TW096100499 A TW 096100499A TW 96100499 A TW96100499 A TW 96100499A TW 200739600 A TW200739600 A TW 200739600A
Authority
TW
Taiwan
Prior art keywords
data bus
memory device
global data
control method
output interface
Prior art date
Application number
TW096100499A
Other languages
Chinese (zh)
Other versions
TWI319881B (en
Inventor
Chang-Ho Do
Original Assignee
Hynix Semiconductor Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Hynix Semiconductor Inc filed Critical Hynix Semiconductor Inc
Publication of TW200739600A publication Critical patent/TW200739600A/en
Application granted granted Critical
Publication of TWI319881B publication Critical patent/TWI319881B/en

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1075—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers for multiport memories each having random access ports and serial ports, e.g. video RAM
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4093—Input/output [I/O] data interface arrangements, e.g. data buffers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/1201—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details comprising I/O circuitry
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/48—Arrangements in static stores specially adapted for testing by means external to the store, e.g. using direct memory access [DMA] or using auxiliary access paths
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1048—Data bus control circuits, e.g. precharging, presetting, equalising
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/08—Functional testing, e.g. testing during refresh, power-on self testing [POST] or distributed testing
    • G11C29/12—Built-in arrangements for testing, e.g. built-in self testing [BIST] or interconnection details
    • G11C29/18—Address generation devices; Devices for accessing memories, e.g. details of addressing circuits
    • G11C29/26—Accessing multiple arrays
    • G11C2029/2602—Concurrent test

Abstract

A semiconductor memory device includes plural ports for transmitting an input data serial-interfaced with an external device into a global data bus, plural banks for parallel-interfacing with the plural ports through the global data bus, plural input signal transmission blocks, responsive to a mode register enable signal, for transmitting an input signal parallel-interfaced with the external device into the global data bus, and a mode register set for determining one of a data access mode and a test mode based on the input signal inputted through the global data bus.
TW096100499A 2006-04-13 2007-01-05 Multi-port memory device with serial input/output interface and control method thereof TWI319881B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020060033766A KR100695436B1 (en) 2006-04-13 2006-04-13 Multi port memory device with serial input/output interface and method for controlling operation mode thereof

Publications (2)

Publication Number Publication Date
TW200739600A true TW200739600A (en) 2007-10-16
TWI319881B TWI319881B (en) 2010-01-21

Family

ID=38514764

Family Applications (1)

Application Number Title Priority Date Filing Date
TW096100499A TWI319881B (en) 2006-04-13 2007-01-05 Multi-port memory device with serial input/output interface and control method thereof

Country Status (6)

Country Link
US (1) US7583557B2 (en)
JP (1) JP5019904B2 (en)
KR (1) KR100695436B1 (en)
CN (1) CN101060008B (en)
DE (1) DE102007001075B4 (en)
TW (1) TWI319881B (en)

Families Citing this family (19)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR100695437B1 (en) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 Multi port memory device
KR100723889B1 (en) * 2006-06-30 2007-05-31 주식회사 하이닉스반도체 Multi port memory device with serial input/output interface
KR100909805B1 (en) * 2006-09-21 2009-07-29 주식회사 하이닉스반도체 Multiport memory device
KR100873616B1 (en) * 2007-04-11 2008-12-12 주식회사 하이닉스반도체 Column decoder and semiconductor memory apparatus using the same
US7724598B1 (en) * 2007-04-19 2010-05-25 Altera Corporation Megafunction block and interface
KR100930403B1 (en) 2007-12-07 2009-12-08 주식회사 하이닉스반도체 Mode register set signal generation circuit
JP5588100B2 (en) 2008-06-23 2014-09-10 ピーエスフォー ルクスコ エスエイアールエル Semiconductor device and data processing system
US20100177783A1 (en) * 2009-01-13 2010-07-15 Samsung Electronics Co., Ltd. Interface systems between media access control (MAC) and physical layer (PHY) including parallel exchange of PHY register data and address information, and methods of operating the parallel exchange
KR101039859B1 (en) * 2009-07-03 2011-06-09 주식회사 하이닉스반도체 Semiconductor memory device
KR20120074897A (en) * 2010-12-28 2012-07-06 에스케이하이닉스 주식회사 Semiconductor memory device including mode regigtser set
KR101919415B1 (en) * 2012-08-08 2018-11-16 에스케이하이닉스 주식회사 Semiconductor device
JP2018032141A (en) * 2016-08-23 2018-03-01 東芝メモリ株式会社 Semiconductor device
KR102476201B1 (en) * 2018-07-24 2022-12-12 에스케이하이닉스 주식회사 Memory device and test circuit thereof
KR102576767B1 (en) * 2018-12-03 2023-09-12 에스케이하이닉스 주식회사 Semiconductor device
KR102130338B1 (en) * 2019-09-17 2020-08-05 주식회사 엑시콘 PCIe Test Apparatus
US11081201B2 (en) 2019-11-26 2021-08-03 Winbond Electronics Corp. Parallel test device
JP2021110994A (en) 2020-01-07 2021-08-02 ウィンボンド エレクトロニクス コーポレーション Constant current circuit
CN113035267B (en) * 2021-03-25 2022-05-13 长江存储科技有限责任公司 Semiconductor testing device, data processing method, equipment and storage medium
CN115374033B (en) * 2022-10-25 2023-02-03 湖南戎腾网络科技有限公司 Cross-board multi-path serial port access device and method

Family Cites Families (34)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4242749A (en) * 1977-12-30 1980-12-30 Fuji Electric Co., Ltd. Operating system for a data transmission system
US4742474A (en) * 1985-04-05 1988-05-03 Tektronix, Inc. Variable access frame buffer memory
US5228139A (en) * 1988-04-19 1993-07-13 Hitachi Ltd. Semiconductor integrated circuit device with test mode for testing CPU using external signal
US5442642A (en) * 1992-12-11 1995-08-15 Micron Semiconductor, Inc. Test signal generator on substrate to test
US6175901B1 (en) * 1994-04-15 2001-01-16 Micron Technology, Inc. Method for initializing and reprogramming a control operation feature of a memory device
JPH09147598A (en) 1995-11-28 1997-06-06 Mitsubishi Electric Corp Semiconductor storage and address change detection circuit
US5796745A (en) 1996-07-19 1998-08-18 International Business Machines Corporation Memory array built-in self test circuit for testing multi-port memory arrays
KR100228339B1 (en) 1996-11-21 1999-11-01 김영환 Multi-port access memory for sharing read port and write port
JPH10289600A (en) * 1997-04-14 1998-10-27 Hitachi Ltd Semiconductor memory device
JPH1166841A (en) 1997-08-22 1999-03-09 Mitsubishi Electric Corp Semiconductor storage device
KR20000026480A (en) * 1998-10-20 2000-05-15 윤종용 Test circuit for integrated circuit
US6421624B1 (en) * 1999-02-05 2002-07-16 Advantest Corp. Multi-port device analysis apparatus and method and calibration method thereof
KR100464940B1 (en) 1999-04-19 2005-01-05 주식회사 하이닉스반도체 Semiconductor memory device of parallel test mode
JP3625688B2 (en) * 1999-04-30 2005-03-02 富士通株式会社 Memory device
KR100319897B1 (en) * 2000-01-31 2002-01-10 윤종용 Semiconductor memory device capable of test time reduction within pipeline
JP4497645B2 (en) * 2000-04-10 2010-07-07 株式会社ルネサステクノロジ Semiconductor memory device
JP2002055879A (en) 2000-08-11 2002-02-20 Univ Hiroshima Multi-port cache memory
JP4569915B2 (en) * 2000-08-11 2010-10-27 エルピーダメモリ株式会社 Semiconductor memory device
JP4071930B2 (en) * 2000-11-22 2008-04-02 富士通株式会社 Synchronous DRAM
US6594196B2 (en) 2000-11-29 2003-07-15 International Business Machines Corporation Multi-port memory device and system for addressing the multi-port memory device
JP2002230977A (en) 2001-01-26 2002-08-16 Seiko Epson Corp Arbiter device for multi-port memory, and semiconductor device
KR100404230B1 (en) * 2001-09-18 2003-11-03 주식회사 하이닉스반도체 Circuit for Controling Test Mode in Semiconductor Memory Device
KR100546331B1 (en) * 2003-06-03 2006-01-26 삼성전자주식회사 Multi-Port memory device with stacked banks
KR100582821B1 (en) * 2003-08-29 2006-05-23 주식회사 하이닉스반도체 Multi-port memory device
DE102004050037B4 (en) * 2003-10-09 2015-01-08 Samsung Electronics Co., Ltd. Memory device, memory system and mode of operation network method
KR100609038B1 (en) * 2004-05-06 2006-08-09 주식회사 하이닉스반도체 Multi-port memory device having serial i/o interface
KR100605573B1 (en) 2004-05-06 2006-07-31 주식회사 하이닉스반도체 Multi-port memory device
JP2005332446A (en) * 2004-05-18 2005-12-02 Fujitsu Ltd Semiconductor memory
US7519877B2 (en) * 2004-08-10 2009-04-14 Micron Technology, Inc. Memory with test mode output
US7184327B2 (en) * 2005-04-14 2007-02-27 Micron Technology, Inc. System and method for enhanced mode register definitions
JP5072274B2 (en) * 2005-09-29 2012-11-14 エスケーハイニックス株式会社 Memory device write circuit
DE102006045248A1 (en) * 2005-09-29 2007-04-19 Hynix Semiconductor Inc., Ichon Multiport memory device with serial input / output interface
KR100695435B1 (en) * 2006-04-13 2007-03-16 주식회사 하이닉스반도체 Semiconductor memory device
KR100723889B1 (en) * 2006-06-30 2007-05-31 주식회사 하이닉스반도체 Multi port memory device with serial input/output interface

Also Published As

Publication number Publication date
JP2007287306A (en) 2007-11-01
CN101060008A (en) 2007-10-24
US20070242553A1 (en) 2007-10-18
US7583557B2 (en) 2009-09-01
DE102007001075A1 (en) 2007-10-18
JP5019904B2 (en) 2012-09-05
TWI319881B (en) 2010-01-21
CN101060008B (en) 2011-10-12
DE102007001075B4 (en) 2017-08-31
KR100695436B1 (en) 2007-03-16

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