HK1052579A1 - Method of forming a stacked-die integrated circuitchip package on a wafer level. - Google Patents

Method of forming a stacked-die integrated circuitchip package on a wafer level.

Info

Publication number
HK1052579A1
HK1052579A1 HK03104790A HK03104790A HK1052579A1 HK 1052579 A1 HK1052579 A1 HK 1052579A1 HK 03104790 A HK03104790 A HK 03104790A HK 03104790 A HK03104790 A HK 03104790A HK 1052579 A1 HK1052579 A1 HK 1052579A1
Authority
HK
Hong Kong
Prior art keywords
die
wafer
stacked
package
bga
Prior art date
Application number
HK03104790A
Other languages
English (en)
Inventor
Ken M Lam
Original Assignee
Atmel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Atmel Corp filed Critical Atmel Corp
Publication of HK1052579A1 publication Critical patent/HK1052579A1/xx

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    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L25/00Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof
    • H01L25/50Multistep manufacturing processes of assemblies consisting of devices, each device being of a type provided for in group H01L27/00 or H01L29/00
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    • H01L24/94Batch processes at wafer-level, i.e. with connecting carried out on a wafer comprising a plurality of undiced individual devices
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    • H01L24/93Batch processes
    • H01L24/95Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips
    • H01L24/97Batch processes at chip-level, i.e. with connecting carried out on a plurality of singulated devices, i.e. on diced chips the devices being connected to a common substrate, e.g. interposer, said common substrate being separable into individual assemblies after connecting
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    • H01L25/04Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers
    • H01L25/065Assemblies consisting of a plurality of individual semiconductor or other solid state devices ; Multistep manufacturing processes thereof all the devices being of a type provided for in the same subgroup of groups H01L27/00 - H01L33/00, or in a single subclass of H10K, H10N, e.g. assemblies of rectifier diodes the devices not having separate containers the devices being of a type provided for in group H01L27/00
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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Testing Or Measuring Of Semiconductors Or The Like (AREA)
  • Wire Bonding (AREA)
  • Dicing (AREA)
  • Structures Or Materials For Encapsulating Or Coating Semiconductor Devices Or Solid State Devices (AREA)
  • Die Bonding (AREA)
  • Semiconductor Integrated Circuits (AREA)
HK03104790A 2000-03-09 2003-07-07 Method of forming a stacked-die integrated circuitchip package on a wafer level. HK1052579A1 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US09/521,299 US6344401B1 (en) 2000-03-09 2000-03-09 Method of forming a stacked-die integrated circuit chip package on a water level
PCT/US2001/000828 WO2001067511A2 (fr) 2000-03-09 2001-01-10 Procede de formation d'un boitier pour puce a circuit integre constitue de puces empilees sur une tranche

Publications (1)

Publication Number Publication Date
HK1052579A1 true HK1052579A1 (en) 2003-09-19

Family

ID=24076195

Family Applications (1)

Application Number Title Priority Date Filing Date
HK03104790A HK1052579A1 (en) 2000-03-09 2003-07-07 Method of forming a stacked-die integrated circuitchip package on a wafer level.

Country Status (12)

Country Link
US (1) US6344401B1 (fr)
EP (1) EP1269538B1 (fr)
JP (1) JP2003526922A (fr)
KR (1) KR20020086612A (fr)
CN (1) CN1194408C (fr)
CA (1) CA2400805A1 (fr)
DE (1) DE60101159T2 (fr)
HK (1) HK1052579A1 (fr)
MY (1) MY134235A (fr)
NO (1) NO20023891D0 (fr)
TW (1) TW484214B (fr)
WO (1) WO2001067511A2 (fr)

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JP2001313350A (ja) * 2000-04-28 2001-11-09 Sony Corp チップ状電子部品及びその製造方法、並びにその製造に用いる疑似ウエーハ及びその製造方法
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TW503496B (en) * 2001-12-31 2002-09-21 Megic Corp Chip packaging structure and manufacturing process of the same
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TW536764B (en) * 2002-04-30 2003-06-11 Walsin Advanced Electronics Method for multi-chip package and structure thereof
KR100460063B1 (ko) 2002-05-03 2004-12-04 주식회사 하이닉스반도체 센터 패드 칩 적층 볼 그리드 어레이 패키지 및 그 제조방법
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EP1269538A2 (fr) 2003-01-02
CN1194408C (zh) 2005-03-23
KR20020086612A (ko) 2002-11-18
CN1416594A (zh) 2003-05-07
WO2001067511A2 (fr) 2001-09-13
TW484214B (en) 2002-04-21
CA2400805A1 (fr) 2001-09-13
US6344401B1 (en) 2002-02-05
JP2003526922A (ja) 2003-09-09
NO20023891L (no) 2002-08-16
NO20023891D0 (no) 2002-08-16
EP1269538B1 (fr) 2003-11-05
MY134235A (en) 2007-11-30
DE60101159D1 (de) 2003-12-11

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