GB2370413B - An integrated circuit package having a cavity therein for improved operation thereof - Google Patents

An integrated circuit package having a cavity therein for improved operation thereof

Info

Publication number
GB2370413B
GB2370413B GB0117310A GB0117310A GB2370413B GB 2370413 B GB2370413 B GB 2370413B GB 0117310 A GB0117310 A GB 0117310A GB 0117310 A GB0117310 A GB 0117310A GB 2370413 B GB2370413 B GB 2370413B
Authority
GB
United Kingdom
Prior art keywords
cavity
integrated circuit
circuit package
improved operation
improved
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
GB0117310A
Other languages
English (en)
Other versions
GB2370413A (en
GB0117310D0 (en
Inventor
Charles Cohn
Junior Donald Earl Hawk
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agere Systems LLC
Original Assignee
Agere Systems Guardian Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agere Systems Guardian Corp filed Critical Agere Systems Guardian Corp
Publication of GB0117310D0 publication Critical patent/GB0117310D0/en
Publication of GB2370413A publication Critical patent/GB2370413A/en
Application granted granted Critical
Publication of GB2370413B publication Critical patent/GB2370413B/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/67—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their insulating layers or insulating parts
    • H10W70/68—Shapes or dispositions thereof
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W70/00—Package substrates; Interposers; Redistribution layers [RDL]
    • H10W70/60—Insulating or insulated package substrates; Interposers; Redistribution layers
    • H10W70/62—Insulating or insulated package substrates; Interposers; Redistribution layers characterised by their interconnections
    • H10W70/63—Vias, e.g. via plugs
    • H10W70/635—Through-vias
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/071—Connecting or disconnecting
    • H10W72/075—Connecting or disconnecting of bond wires
    • H10W72/07551—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting
    • H10W72/07554—Connecting or disconnecting of bond wires characterised by changes in properties of the bond wires during the connecting changes in dispositions
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/541—Dispositions of bond wires
    • H10W72/547—Dispositions of multiple bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/50—Bond wires
    • H10W72/551—Materials of bond wires
    • H10W72/552—Materials of bond wires comprising metals or metalloids, e.g. silver
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W72/00—Interconnections or connectors in packages
    • H10W72/851—Dispositions of multiple connectors or interconnections
    • H10W72/874—On different surfaces
    • H10W72/884—Die-attach connectors and bond wires
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W74/00—Encapsulations, e.g. protective coatings
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/731—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors
    • H10W90/734—Package configurations characterised by the relative positions of pads or connectors relative to package parts of die-attach connectors between a chip and a stacked insulating package substrate, interposer or RDL
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10W—GENERIC PACKAGES, INTERCONNECTIONS, CONNECTORS OR OTHER CONSTRUCTIONAL DETAILS OF DEVICES COVERED BY CLASS H10
    • H10W90/00—Package configurations
    • H10W90/701—Package configurations characterised by the relative positions of pads or connectors relative to package parts
    • H10W90/751—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires
    • H10W90/754—Package configurations characterised by the relative positions of pads or connectors relative to package parts of bond wires between a chip and a stacked insulating package substrate, interposer or RDL
GB0117310A 2000-07-21 2001-07-16 An integrated circuit package having a cavity therein for improved operation thereof Expired - Fee Related GB2370413B (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/620,939 US6465882B1 (en) 2000-07-21 2000-07-21 Integrated circuit package having partially exposed conductive layer

Publications (3)

Publication Number Publication Date
GB0117310D0 GB0117310D0 (en) 2001-09-05
GB2370413A GB2370413A (en) 2002-06-26
GB2370413B true GB2370413B (en) 2004-10-20

Family

ID=24488025

Family Applications (1)

Application Number Title Priority Date Filing Date
GB0117310A Expired - Fee Related GB2370413B (en) 2000-07-21 2001-07-16 An integrated circuit package having a cavity therein for improved operation thereof

Country Status (5)

Country Link
US (1) US6465882B1 (https=)
JP (2) JP4352365B2 (https=)
KR (1) KR100678878B1 (https=)
GB (1) GB2370413B (https=)
TW (1) TW512503B (https=)

Families Citing this family (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6790760B1 (en) * 2000-07-21 2004-09-14 Agere Systems Inc. Method of manufacturing an integrated circuit package
DE10109542B4 (de) * 2001-02-28 2004-02-05 Siemens Ag Anordung zur Verbindung eines auf einer Leiterplatte angebrachten Bauelementes mit einer flexiblen Schichtanordnung
JP2005500638A (ja) * 2001-08-10 2005-01-06 シーゲイト テクノロジー エルエルシー 集積相互接続とその製造方法
DE10233607B4 (de) 2002-07-24 2005-09-29 Siemens Ag Anordnung mit einem Halbleiterchip und einem mit einer Durchkontaktierung versehenen Träger sowie einem ein Anschlusspad des Halbleiterchips mit der Durchkontaktierung verbindenden Draht und Verfahren zum Herstellen einer solchen Anordnung
TWI241000B (en) * 2003-01-21 2005-10-01 Siliconware Precision Industries Co Ltd Semiconductor package and fabricating method thereof
US7423340B2 (en) * 2003-01-21 2008-09-09 Siliconware Precision Industries Co., Ltd. Semiconductor package free of substrate and fabrication method thereof
US20040183167A1 (en) * 2003-03-21 2004-09-23 Texas Instruments Incorporated Recessed-bond semiconductor package substrate
US6956286B2 (en) * 2003-08-05 2005-10-18 International Business Machines Corporation Integrated circuit package with overlapping bond fingers
US7166905B1 (en) 2004-10-05 2007-01-23 Integrated Device Technology, Inc. Stacked paddle micro leadframe package
TWI286917B (en) * 2005-01-14 2007-09-11 Au Optronics Corp Thermal bonding structure and manufacture process of flexible printed circuit (FPC)
TW200703606A (en) * 2005-07-15 2007-01-16 Siliconware Precision Industries Co Ltd Semiconductor package and fabrication method thereof
US8447700B2 (en) 2005-10-11 2013-05-21 Amazon Technologies, Inc. Transaction authorization service
WO2010090075A1 (ja) * 2009-02-05 2010-08-12 アルプス電気株式会社 磁気検出装置
CN103000539B (zh) * 2012-11-16 2016-05-18 日月光半导体制造股份有限公司 半导体封装构造及其制造方法

Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196725A (en) * 1990-06-11 1993-03-23 Hitachi Cable Limited High pin count and multi-layer wiring lead frame
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
US5488542A (en) * 1993-08-18 1996-01-30 Kabushiki Kaisha Toshiba MCM manufactured by using thin film multilevel interconnection technique
US5640048A (en) * 1994-07-11 1997-06-17 Sun Microsystems, Inc. Ball grid array package for a integrated circuit
EP1011139A1 (en) * 1997-03-13 2000-06-21 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US6137168A (en) * 1998-01-13 2000-10-24 Lsi Logic Corporation Semiconductor package with traces routed underneath a die

Family Cites Families (13)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4320438A (en) 1980-05-15 1982-03-16 Cts Corporation Multi-layer ceramic package
JPH01258447A (ja) * 1988-04-08 1989-10-16 Nec Corp 混成集積回路の積層厚膜基板
JPH07112039B2 (ja) * 1991-03-14 1995-11-29 日立電線株式会社 多ピン多層配線リードフレーム
US5490324A (en) 1993-09-15 1996-02-13 Lsi Logic Corporation Method of making integrated circuit package having multiple bonding tiers
JP2931741B2 (ja) 1993-09-24 1999-08-09 株式会社東芝 半導体装置
JPH07288385A (ja) 1994-04-19 1995-10-31 Hitachi Chem Co Ltd 多層配線板及びその製造法
US5622588A (en) 1995-02-02 1997-04-22 Hestia Technologies, Inc. Methods of making multi-tier laminate substrates for electronic device packaging
JPH08288316A (ja) * 1995-04-14 1996-11-01 Citizen Watch Co Ltd 半導体装置
US5689091A (en) 1996-09-19 1997-11-18 Vlsi Technology, Inc. Multi-layer substrate structure
US6054758A (en) 1996-12-18 2000-04-25 Texas Instruments Incorporated Differential pair geometry for integrated circuit chip packages
JPH11204688A (ja) * 1997-11-11 1999-07-30 Sony Corp 半導体パッケージおよびその製造方法
JPH11266068A (ja) * 1998-01-14 1999-09-28 Canon Inc 配線基板及び配線基板の製造方法
JPH11354566A (ja) * 1998-06-08 1999-12-24 Hitachi Ltd 半導体装置およびその製造方法

Patent Citations (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US5196725A (en) * 1990-06-11 1993-03-23 Hitachi Cable Limited High pin count and multi-layer wiring lead frame
US5220195A (en) * 1991-12-19 1993-06-15 Motorola, Inc. Semiconductor device having a multilayer leadframe with full power and ground planes
US5488542A (en) * 1993-08-18 1996-01-30 Kabushiki Kaisha Toshiba MCM manufactured by using thin film multilevel interconnection technique
US5640048A (en) * 1994-07-11 1997-06-17 Sun Microsystems, Inc. Ball grid array package for a integrated circuit
EP1011139A1 (en) * 1997-03-13 2000-06-21 Ibiden Co., Ltd. Printed wiring board and method for manufacturing the same
US6137168A (en) * 1998-01-13 2000-10-24 Lsi Logic Corporation Semiconductor package with traces routed underneath a die

Also Published As

Publication number Publication date
JP4352365B2 (ja) 2009-10-28
KR20020008781A (ko) 2002-01-31
TW512503B (en) 2002-12-01
US6465882B1 (en) 2002-10-15
GB2370413A (en) 2002-06-26
JP2002093949A (ja) 2002-03-29
JP2008172267A (ja) 2008-07-24
KR100678878B1 (ko) 2007-02-07
GB0117310D0 (en) 2001-09-05
JP5135493B2 (ja) 2013-02-06

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Legal Events

Date Code Title Description
PCNP Patent ceased through non-payment of renewal fee

Effective date: 20160716