GB1486099A - Planar diffusion method for making integrated circuits - Google Patents

Planar diffusion method for making integrated circuits

Info

Publication number
GB1486099A
GB1486099A GB45110/75A GB4511075A GB1486099A GB 1486099 A GB1486099 A GB 1486099A GB 45110/75 A GB45110/75 A GB 45110/75A GB 4511075 A GB4511075 A GB 4511075A GB 1486099 A GB1486099 A GB 1486099A
Authority
GB
United Kingdom
Prior art keywords
base zones
layer
zones
circuit
conductivity type
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB45110/75A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Micronas GmbH
ITT Inc
Original Assignee
Deutsche ITT Industries GmbH
ITT Industries Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Deutsche ITT Industries GmbH, ITT Industries Inc filed Critical Deutsche ITT Industries GmbH
Publication of GB1486099A publication Critical patent/GB1486099A/en
Expired legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
    • H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
    • H01L21/2251—Diffusion into or out of group IV semiconductors
    • H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/0112—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs
    • H10D84/0116—Integrating together multiple components covered by H10D8/00, H10D10/00 or H10D18/00, e.g. integrating multiple BJTs the components including integrated injection logic [I2L]
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/01—Manufacture or treatment
    • H10D84/02—Manufacture or treatment characterised by using material-based technologies
    • H10D84/03—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology
    • H10D84/038—Manufacture or treatment characterised by using material-based technologies using Group IV technology, e.g. silicon technology or silicon-carbide [SiC] technology using silicon technology, e.g. SiGe
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D84/00—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers
    • H10D84/60—Integrated devices formed in or on semiconductor substrates that comprise only semiconducting layers, e.g. on Si wafers or on GaAs-on-Si wafers characterised by the integration of at least one component covered by groups H10D10/00 or H10D18/00, e.g. integration of BJTs
    • H10D84/65—Integrated injection logic
    • H10D84/658—Integrated injection logic integrated in combination with analog structures
    • Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
    • Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
    • Y10S148/00—Metal treatment
    • Y10S148/087—I2L integrated injection logic

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
GB45110/75A 1974-11-08 1975-10-31 Planar diffusion method for making integrated circuits Expired GB1486099A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
DE2453134A DE2453134C3 (de) 1974-11-08 1974-11-08 Planardiffusionsverfahren

Publications (1)

Publication Number Publication Date
GB1486099A true GB1486099A (en) 1977-09-14

Family

ID=5930397

Family Applications (1)

Application Number Title Priority Date Filing Date
GB45110/75A Expired GB1486099A (en) 1974-11-08 1975-10-31 Planar diffusion method for making integrated circuits

Country Status (7)

Country Link
US (1) US4043849A (en, 2012)
JP (1) JPS5910589B2 (en, 2012)
CH (1) CH596668A5 (en, 2012)
DE (1) DE2453134C3 (en, 2012)
FR (1) FR2290758A1 (en, 2012)
GB (1) GB1486099A (en, 2012)
IT (1) IT1048824B (en, 2012)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855768A1 (de) * 1978-12-22 1980-06-26 Itt Ind Gmbh Deutsche Monolithisch integrierte schaltung

Families Citing this family (17)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2532608C2 (de) * 1975-07-22 1982-09-02 Deutsche Itt Industries Gmbh, 7800 Freiburg Planardiffusionsverfahren zum Herstellen einer monolithisch integrierten Schaltung
JPS5338276A (en) * 1976-09-20 1978-04-08 Toshiba Corp Semiconductor device
DE2710878A1 (de) * 1977-03-12 1978-09-14 Itt Ind Gmbh Deutsche Verfahren zum herstellen einer an der oberflaeche eines halbleiterkoerpers aus silicium liegenden zone einer monolithisch integrierten i hoch 2 l-schaltung
DE2711657C2 (de) * 1977-03-17 1983-08-25 Deutsche Itt Industries Gmbh, 7800 Freiburg Planardiffusionsverfahren mit mindestens zwei aufeinanderfolgenden Diffusionsprozessen
DE2715158A1 (de) * 1977-04-05 1978-10-19 Licentia Gmbh Verfahren zur herstellung mindestens einer mit mindestens einer i hoch 2 l-schaltung integrierten analogschaltung
US4400689A (en) * 1977-04-07 1983-08-23 Analog Devices, Incorporated A-to-D Converter of the successive-approximation type
US4144098A (en) * 1977-04-28 1979-03-13 Hughes Aircraft Company P+ Buried layer for I2 L isolation by ion implantation
US4149906A (en) * 1977-04-29 1979-04-17 International Business Machines Corporation Process for fabrication of merged transistor logic (MTL) cells
US4157268A (en) * 1977-06-16 1979-06-05 International Business Machines Corporation Localized oxidation enhancement for an integrated injection logic circuit
JPS54113276A (en) * 1978-02-24 1979-09-04 Hitachi Ltd Rpoduction of semiconductor device
DE2835330C3 (de) * 1978-08-11 1982-03-11 Siemens AG, 1000 Berlin und 8000 München Integrierter bipolarer Halbleiterschaltkreis sowie Verfahren zu seiner Herstellung
JPS5555559A (en) * 1978-10-19 1980-04-23 Toshiba Corp Method of fabricating semiconductor device
US4272307A (en) * 1979-03-12 1981-06-09 Sprague Electric Company Integrated circuit with I2 L and power transistors and method for making
DE3020609C2 (de) * 1979-05-31 1985-11-07 Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa Verfahren zum Herstellen einer integrierten Schaltung mit wenigstens einem I↑2↑L-Element
JPS5739567A (en) * 1980-07-18 1982-03-04 Nec Corp Manufacture of semiconductor device
JPS63166793U (en, 2012) * 1987-04-17 1988-10-31
SE514707C2 (sv) * 1998-11-04 2001-04-02 Ericsson Telefon Ab L M Metod för halvledartillverkning

Family Cites Families (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL135875C (en, 2012) * 1958-06-09 1900-01-01
US3551221A (en) * 1967-11-29 1970-12-29 Nippon Electric Co Method of manufacturing a semiconductor integrated circuit
FR1569872A (en, 2012) * 1968-04-10 1969-06-06
US3655457A (en) * 1968-08-06 1972-04-11 Ibm Method of making or modifying a pn-junction by ion implantation
US3566218A (en) * 1968-10-02 1971-02-23 Nat Semiconductor Corp The Multiple base width integrated circuit
US3560278A (en) * 1968-11-29 1971-02-02 Motorola Inc Alignment process for fabricating semiconductor devices
US3806382A (en) * 1972-04-06 1974-04-23 Ibm Vapor-solid impurity diffusion process
JPS5548704B2 (en, 2012) * 1973-06-01 1980-12-08
US3928081A (en) * 1973-10-26 1975-12-23 Signetics Corp Method for fabricating semiconductor devices using composite mask and ion implantation
US3898107A (en) * 1973-12-03 1975-08-05 Rca Corp Method of making a junction-isolated semiconductor integrated circuit device
US3933528A (en) * 1974-07-02 1976-01-20 Texas Instruments Incorporated Process for fabricating integrated circuits utilizing ion implantation

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE2855768A1 (de) * 1978-12-22 1980-06-26 Itt Ind Gmbh Deutsche Monolithisch integrierte schaltung

Also Published As

Publication number Publication date
DE2453134C3 (de) 1983-02-10
US4043849A (en) 1977-08-23
CH596668A5 (en, 2012) 1978-03-15
FR2290758B1 (en, 2012) 1981-09-04
JPS5169987A (en, 2012) 1976-06-17
DE2453134B2 (de) 1976-11-04
FR2290758A1 (fr) 1976-06-04
IT1048824B (it) 1980-12-20
DE2453134A1 (de) 1976-05-13
JPS5910589B2 (ja) 1984-03-09

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Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
PCNP Patent ceased through non-payment of renewal fee