IT1048824B - Procedimento di diffusione planare - Google Patents
Procedimento di diffusione planareInfo
- Publication number
- IT1048824B IT1048824B IT28989/75A IT2898975A IT1048824B IT 1048824 B IT1048824 B IT 1048824B IT 28989/75 A IT28989/75 A IT 28989/75A IT 2898975 A IT2898975 A IT 2898975A IT 1048824 B IT1048824 B IT 1048824B
- Authority
- IT
- Italy
- Prior art keywords
- planar diffusion
- diffusion procedure
- procedure
- planar
- diffusion
- Prior art date
Links
- 238000009792 diffusion process Methods 0.000 title 1
- 238000000034 method Methods 0.000 title 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/22—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities
- H01L21/225—Diffusion of impurity materials, e.g. doping materials, electrode materials, into or out of a semiconductor body, or between semiconductor regions; Interactions between two or more impurities; Redistribution of impurities using diffusion into or out of a solid from or into a solid phase, e.g. a doped oxide layer
- H01L21/2251—Diffusion into or out of group IV semiconductors
- H01L21/2252—Diffusion into or out of group IV semiconductors using predeposition of impurities into the semiconductor surface, e.g. from a gaseous phase
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
- H01L21/8222—Bipolar technology
- H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
- H01L27/0203—Particular design considerations for integrated circuits
- H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
- H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
- H01L27/0233—Integrated injection logic structures [I2L]
- H01L27/0244—I2L structures integrated in combination with analog structures
-
- Y—GENERAL TAGGING OF NEW TECHNOLOGICAL DEVELOPMENTS; GENERAL TAGGING OF CROSS-SECTIONAL TECHNOLOGIES SPANNING OVER SEVERAL SECTIONS OF THE IPC; TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10—TECHNICAL SUBJECTS COVERED BY FORMER USPC
- Y10S—TECHNICAL SUBJECTS COVERED BY FORMER USPC CROSS-REFERENCE ART COLLECTIONS [XRACs] AND DIGESTS
- Y10S148/00—Metal treatment
- Y10S148/087—I2L integrated injection logic
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Manufacturing & Machinery (AREA)
- Bipolar Integrated Circuits (AREA)
- Bipolar Transistors (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
DE2453134A DE2453134C3 (de) | 1974-11-08 | 1974-11-08 | Planardiffusionsverfahren |
Publications (1)
Publication Number | Publication Date |
---|---|
IT1048824B true IT1048824B (it) | 1980-12-20 |
Family
ID=5930397
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
IT28989/75A IT1048824B (it) | 1974-11-08 | 1975-11-05 | Procedimento di diffusione planare |
Country Status (7)
Country | Link |
---|---|
US (1) | US4043849A (it) |
JP (1) | JPS5910589B2 (it) |
CH (1) | CH596668A5 (it) |
DE (1) | DE2453134C3 (it) |
FR (1) | FR2290758A1 (it) |
GB (1) | GB1486099A (it) |
IT (1) | IT1048824B (it) |
Families Citing this family (18)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
DE2532608C2 (de) * | 1975-07-22 | 1982-09-02 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Planardiffusionsverfahren zum Herstellen einer monolithisch integrierten Schaltung |
JPS5338276A (en) * | 1976-09-20 | 1978-04-08 | Toshiba Corp | Semiconductor device |
DE2710878A1 (de) * | 1977-03-12 | 1978-09-14 | Itt Ind Gmbh Deutsche | Verfahren zum herstellen einer an der oberflaeche eines halbleiterkoerpers aus silicium liegenden zone einer monolithisch integrierten i hoch 2 l-schaltung |
DE2711657C2 (de) * | 1977-03-17 | 1983-08-25 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Planardiffusionsverfahren mit mindestens zwei aufeinanderfolgenden Diffusionsprozessen |
DE2715158A1 (de) * | 1977-04-05 | 1978-10-19 | Licentia Gmbh | Verfahren zur herstellung mindestens einer mit mindestens einer i hoch 2 l-schaltung integrierten analogschaltung |
US4400689A (en) * | 1977-04-07 | 1983-08-23 | Analog Devices, Incorporated | A-to-D Converter of the successive-approximation type |
US4144098A (en) * | 1977-04-28 | 1979-03-13 | Hughes Aircraft Company | P+ Buried layer for I2 L isolation by ion implantation |
US4149906A (en) * | 1977-04-29 | 1979-04-17 | International Business Machines Corporation | Process for fabrication of merged transistor logic (MTL) cells |
US4157268A (en) * | 1977-06-16 | 1979-06-05 | International Business Machines Corporation | Localized oxidation enhancement for an integrated injection logic circuit |
JPS54113276A (en) * | 1978-02-24 | 1979-09-04 | Hitachi Ltd | Rpoduction of semiconductor device |
DE2835330C3 (de) * | 1978-08-11 | 1982-03-11 | Siemens AG, 1000 Berlin und 8000 München | Integrierter bipolarer Halbleiterschaltkreis sowie Verfahren zu seiner Herstellung |
JPS5555559A (en) * | 1978-10-19 | 1980-04-23 | Toshiba Corp | Method of fabricating semiconductor device |
DE2855768C3 (de) * | 1978-12-22 | 1981-10-15 | Deutsche Itt Industries Gmbh, 7800 Freiburg | Monolithisch integrierte Schaltung |
US4272307A (en) * | 1979-03-12 | 1981-06-09 | Sprague Electric Company | Integrated circuit with I2 L and power transistors and method for making |
DE3020609C2 (de) * | 1979-05-31 | 1985-11-07 | Tokyo Shibaura Denki K.K., Kawasaki, Kanagawa | Verfahren zum Herstellen einer integrierten Schaltung mit wenigstens einem I↑2↑L-Element |
JPS5739567A (en) * | 1980-07-18 | 1982-03-04 | Nec Corp | Manufacture of semiconductor device |
JPS63166793U (it) * | 1987-04-17 | 1988-10-31 | ||
SE514707C2 (sv) * | 1998-11-04 | 2001-04-02 | Ericsson Telefon Ab L M | Metod för halvledartillverkning |
Family Cites Families (11)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL135875C (it) * | 1958-06-09 | 1900-01-01 | ||
US3551221A (en) * | 1967-11-29 | 1970-12-29 | Nippon Electric Co | Method of manufacturing a semiconductor integrated circuit |
FR1569872A (it) * | 1968-04-10 | 1969-06-06 | ||
US3655457A (en) * | 1968-08-06 | 1972-04-11 | Ibm | Method of making or modifying a pn-junction by ion implantation |
US3566218A (en) * | 1968-10-02 | 1971-02-23 | Nat Semiconductor Corp The | Multiple base width integrated circuit |
US3560278A (en) * | 1968-11-29 | 1971-02-02 | Motorola Inc | Alignment process for fabricating semiconductor devices |
US3806382A (en) * | 1972-04-06 | 1974-04-23 | Ibm | Vapor-solid impurity diffusion process |
JPS5548704B2 (it) * | 1973-06-01 | 1980-12-08 | ||
US3928081A (en) * | 1973-10-26 | 1975-12-23 | Signetics Corp | Method for fabricating semiconductor devices using composite mask and ion implantation |
US3898107A (en) * | 1973-12-03 | 1975-08-05 | Rca Corp | Method of making a junction-isolated semiconductor integrated circuit device |
US3933528A (en) * | 1974-07-02 | 1976-01-20 | Texas Instruments Incorporated | Process for fabricating integrated circuits utilizing ion implantation |
-
1974
- 1974-11-08 DE DE2453134A patent/DE2453134C3/de not_active Expired
-
1975
- 1975-10-23 US US05/625,339 patent/US4043849A/en not_active Expired - Lifetime
- 1975-10-31 GB GB45110/75A patent/GB1486099A/en not_active Expired
- 1975-11-05 IT IT28989/75A patent/IT1048824B/it active
- 1975-11-07 FR FR7534066A patent/FR2290758A1/fr active Granted
- 1975-11-07 CH CH1441575A patent/CH596668A5/xx not_active IP Right Cessation
- 1975-11-08 JP JP50133636A patent/JPS5910589B2/ja not_active Expired
Also Published As
Publication number | Publication date |
---|---|
US4043849A (en) | 1977-08-23 |
DE2453134C3 (de) | 1983-02-10 |
DE2453134A1 (de) | 1976-05-13 |
GB1486099A (en) | 1977-09-14 |
FR2290758B1 (it) | 1981-09-04 |
JPS5910589B2 (ja) | 1984-03-09 |
DE2453134B2 (de) | 1976-11-04 |
FR2290758A1 (fr) | 1976-06-04 |
JPS5169987A (it) | 1976-06-17 |
CH596668A5 (it) | 1978-03-15 |
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