GB1499389A - Monolithic semiconductor mask programmable rom and a method for manufacturing the same - Google Patents

Monolithic semiconductor mask programmable rom and a method for manufacturing the same

Info

Publication number
GB1499389A
GB1499389A GB39393/75A GB3939375A GB1499389A GB 1499389 A GB1499389 A GB 1499389A GB 39393/75 A GB39393/75 A GB 39393/75A GB 3939375 A GB3939375 A GB 3939375A GB 1499389 A GB1499389 A GB 1499389A
Authority
GB
United Kingdom
Prior art keywords
regions
igfets
substrate
semi
spaced
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
GB39393/75A
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Toshiba Corp
Original Assignee
Tokyo Shibaura Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Tokyo Shibaura Electric Co Ltd filed Critical Tokyo Shibaura Electric Co Ltd
Publication of GB1499389A publication Critical patent/GB1499389A/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C17/00—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards
    • G11C17/08—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements
    • G11C17/10—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM
    • G11C17/12—Read-only memories programmable only once; Semi-permanent stores, e.g. manually-replaceable information cards using semiconductor devices, e.g. bipolar elements in which contents are determined during manufacturing by a predetermined arrangement of coupling elements, e.g. mask-programmable ROM using field-effect devices
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/36—Gate programmed, e.g. different gate material or no gate
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B20/00—Read-only memory [ROM] devices
    • H10B20/27—ROM only
    • H10B20/30—ROM only having the source region and the drain region on the same level, e.g. lateral transistors
    • H10B20/38—Doping programmed, e.g. mask ROM
    • H10B20/387—Source region or drain region doping programmed

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
  • Read Only Memory (AREA)
  • Non-Volatile Memory (AREA)
  • Design And Manufacture Of Integrated Circuits (AREA)

Abstract

1499389 Integrated circuits TOKYO SHIBAURA ELECTRIC CO Ltd 25 Sept 1975 [26 Sept 1974] 39393/75 Heading H1K A monolithic semi-conductor mask-programmable ROM matrix comprises a plurality of enhancement mode IGFETs, those IGFETs 52P in which no information is written including a semi-conductor substrate with a plurality of strip-shaped source and drain diffused regions 54, 55, spaced metal strips 56 on a thick insulating layer on the substrate, and corresponding gate electrodes 57 on a thin layer of insulation on the substrate and integral with the metal strips 56, with at least one side thereof spaced by a given distance d 1 , d 2 from the source and drain regions respectively, and those IGFETs 51P containing written-in information include, in addition, impurity regions 59 formed by an additional doping step according to a customer's requirements, which regions 59 complete the otherwise incomplete IGFET structures. Those IGFETs 52P not containing information, i.e. without the regions 59, may be doped instead to provide opposite conductivity type regions to the regions 59 to reduce leakage currents, and both these additional regions may be formed by diffusion, or preferably by ion implantation. In an alternative embodiment, the gate electrodes 57 may be spaced from only one of the source and drain regions, and in another alternative embodiment P and N channel IGFETs may be formed in one chip by doping half of it to form a P well and a N substrate, in both of which IGFETs are formed as above. The semi-conductor chip may be Si, the dopants B and P, the electrodes Al, and the device may be passivated by a B- or P-doped glass layer.
GB39393/75A 1974-09-26 1975-09-25 Monolithic semiconductor mask programmable rom and a method for manufacturing the same Expired GB1499389A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP49110032A JPS605062B2 (en) 1974-09-26 1974-09-26 semiconductor logic circuit device

Publications (1)

Publication Number Publication Date
GB1499389A true GB1499389A (en) 1978-02-01

Family

ID=14525370

Family Applications (1)

Application Number Title Priority Date Filing Date
GB39393/75A Expired GB1499389A (en) 1974-09-26 1975-09-25 Monolithic semiconductor mask programmable rom and a method for manufacturing the same

Country Status (4)

Country Link
JP (1) JPS605062B2 (en)
DE (1) DE2543138B2 (en)
FR (1) FR2286471A1 (en)
GB (1) GB1499389A (en)

Families Citing this family (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4061506A (en) * 1975-05-01 1977-12-06 Texas Instruments Incorporated Correcting doping defects
JPS54121685A (en) * 1978-03-14 1979-09-20 Kyushu Nippon Electric Ic and method of fabricating same
JPH0626246B2 (en) * 1983-06-17 1994-04-06 株式会社日立製作所 Method of manufacturing semiconductor memory
JPS5910261A (en) * 1983-06-24 1984-01-19 Toshiba Corp Semiconductor logical circuit device
JPS6149975U (en) * 1984-09-05 1986-04-03
FR2826169A1 (en) * 2001-06-15 2002-12-20 St Microelectronics Sa READ ONLY MOS MEMORY
DE102019128071B3 (en) 2019-10-17 2021-02-04 Infineon Technologies Ag TRANSISTOR COMPONENT

Also Published As

Publication number Publication date
JPS5137578A (en) 1976-03-29
DE2543138C3 (en) 1979-01-25
DE2543138A1 (en) 1976-04-29
JPS605062B2 (en) 1985-02-08
FR2286471A1 (en) 1976-04-23
DE2543138B2 (en) 1978-05-11
FR2286471B1 (en) 1981-10-30

Similar Documents

Publication Publication Date Title
US5406110A (en) Resurf lateral double diffused insulated gate field effect transistor
GB1408180A (en) Semiconductor device manufacture
US4933730A (en) Semiconductor device having a high breakdown voltage characteristic
US20070212823A1 (en) Method for integrating DMOS into sub-micron CMOS process
KR850006656A (en) Manufacturing method of semiconductor integrated circuit device
GB1451096A (en) Semiconductor devices
GB1501249A (en) Field effect transistor
GB1335813A (en) Transistor and method of manufacturing the same
KR960035908A (en) Manufacturing method of MOS field effect transistor
GB1486099A (en) Planar diffusion method for making integrated circuits
US4001048A (en) Method of making metal oxide semiconductor structures using ion implantation
GB1499389A (en) Monolithic semiconductor mask programmable rom and a method for manufacturing the same
US4175317A (en) Method for manufacturing junction type field-effect transistors
ES486588A1 (en) Double diffused transistor structure and method of making same.
GB1298375A (en) Method of making field effect transistors
GB2055247A (en) Method of fabricating VMOS transistors
JPH0227772A (en) Field effect type thin film transistor
US3753806A (en) Increasing field inversion voltage of metal oxide on silicon integrated circuits
JPS5521102A (en) Semiconductor memory cell
KR100214854B1 (en) Fabrication method of a mask rom
KR940016961A (en) MOS transistor and its manufacturing method
JPS6173380A (en) Manufacture of semiconductor device
JPS57132357A (en) Manufacture of semiconductor element
JPH0691250B2 (en) Semiconductor device
JPS62130562A (en) Manufacture of field effect transistor

Legal Events

Date Code Title Description
PS Patent sealed [section 19, patents act 1949]
746 Register noted 'licences of right' (sect. 46/1977)
PE20 Patent expired after termination of 20 years

Effective date: 19950924