GB1443836A - Bipolar transistor construction method - Google Patents
Bipolar transistor construction methodInfo
- Publication number
- GB1443836A GB1443836A GB2339574A GB2339574A GB1443836A GB 1443836 A GB1443836 A GB 1443836A GB 2339574 A GB2339574 A GB 2339574A GB 2339574 A GB2339574 A GB 2339574A GB 1443836 A GB1443836 A GB 1443836A
- Authority
- GB
- United Kingdom
- Prior art keywords
- diffusion
- mask
- region
- emitter
- collector
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 238000010276 construction Methods 0.000 title 1
- 238000009792 diffusion process Methods 0.000 abstract 7
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 4
- 230000015572 biosynthetic process Effects 0.000 abstract 3
- MCMNRKCIXSYSNV-UHFFFAOYSA-N Zirconium dioxide Chemical compound O=[Zr]=O MCMNRKCIXSYSNV-UHFFFAOYSA-N 0.000 abstract 2
- 238000005468 ion implantation Methods 0.000 abstract 2
- 238000004519 manufacturing process Methods 0.000 abstract 2
- 230000000873 masking effect Effects 0.000 abstract 2
- 235000012239 silicon dioxide Nutrition 0.000 abstract 2
- 239000000377 silicon dioxide Substances 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 1
- PNEYBMLMFCGWSK-UHFFFAOYSA-N aluminium oxide Inorganic materials [O-2].[O-2].[O-2].[Al+3].[Al+3] PNEYBMLMFCGWSK-UHFFFAOYSA-N 0.000 abstract 1
- 239000002019 doping agent Substances 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 238000002513 implantation Methods 0.000 abstract 1
- 238000001465 metallisation Methods 0.000 abstract 1
- 238000000034 method Methods 0.000 abstract 1
- 150000004767 nitrides Chemical class 0.000 abstract 1
- 229920002120 photoresistant polymer Polymers 0.000 abstract 1
- 230000000717 retained effect Effects 0.000 abstract 1
- 229910052710 silicon Inorganic materials 0.000 abstract 1
- 239000010703 silicon Substances 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/302—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to change their surface-physical characteristics or shape, e.g. etching, polishing, cutting
- H01L21/306—Chemical or electrical treatment, e.g. electrolytic etching
- H01L21/308—Chemical or electrical treatment, e.g. electrolytic etching using masks
- H01L21/3083—Chemical or electrical treatment, e.g. electrolytic etching using masks characterised by their size, orientation, disposition, behaviour, shape, in horizontal or vertical plane
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
- H10B—ELECTRONIC MEMORY DEVICES
- H10B20/00—Read-only memory [ROM] devices
- H10B20/10—ROM devices comprising bipolar components
Abstract
1443836 Integrated bipolar transistors TRW Inc 24 May 1974 [25 May 1973 (2)] 23395/74 Heading H1K In manufacturing an integrated circuit bipolar transistor a mask used in the formation of the collector region by diffusion or ion implantation is retained during formation of base and emitter regions or more limited extent by diffusion or implantation. The mask may be of silicon nitride, alumina, zirconia or a thick layer of silicon dioxide so that it remains substantially unchanged during formation and removal by etching of any thin silicon dioxide masking layers used in subsequent manufacturing steps. Typically a number of identical transistors are formed in a P-type silicon wafer by first providing a nitride mask 14 of rectangular frame form for each device, as shown in Figs. 1 and 2, S/2 representing the tolerance in mask alignment. In each subsequent diffusion or metallization step an oxide layer is provided overall and conventionally patterned to define masks of suitable form. After forming the collector region by diffusion through the entire central opening in each frame, the base region 22 and inversion stop region 24 are simultaneously diffused and then the emitter 26 and collector contact region 28. In another generally similar process the initial mask is of thick oxide and the zone arrangement such as to permit the base electrode to be located between the emitter and collector electrodes (Fig. 27, not shown). In a further variant in which the initial mask is in the form of a rectangular perimetered figure eight (Fig. 13), overlapping zones formed by diffusion through windows 54, 56 constitute the collector region, the base region is formed by diffusion through the wider window only and the emitter zone by diffusion through half of that window. Where ion-implantation is used the thin oxide masking may be replaced by hardened photoresist. Processing details are given and dopant concentrations specified.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US36414873A | 1973-05-25 | 1973-05-25 | |
| US363995A US3885994A (en) | 1973-05-25 | 1973-05-25 | Bipolar transistor construction method |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1443836A true GB1443836A (en) | 1976-07-28 |
Family
ID=27002297
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB2339574A Expired GB1443836A (en) | 1973-05-25 | 1974-05-24 | Bipolar transistor construction method |
Country Status (1)
| Country | Link |
|---|---|
| GB (1) | GB1443836A (en) |
-
1974
- 1974-05-24 GB GB2339574A patent/GB1443836A/en not_active Expired
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed [section 19, patents act 1949] | ||
| PCNP | Patent ceased through non-payment of renewal fee |