GB1150834A - Method of fabricating semiconductor devices - Google Patents
Method of fabricating semiconductor devicesInfo
- Publication number
- GB1150834A GB1150834A GB2847467A GB2847467A GB1150834A GB 1150834 A GB1150834 A GB 1150834A GB 2847467 A GB2847467 A GB 2847467A GB 2847467 A GB2847467 A GB 2847467A GB 1150834 A GB1150834 A GB 1150834A
- Authority
- GB
- United Kingdom
- Prior art keywords
- aperture
- apertures
- layer
- masking layer
- deposited
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
- 239000004065 semiconductor Substances 0.000 title abstract 3
- 238000004519 manufacturing process Methods 0.000 title abstract 2
- 230000000873 masking effect Effects 0.000 abstract 5
- 238000000034 method Methods 0.000 abstract 4
- VYPSYNLAJGMNEJ-UHFFFAOYSA-N Silicium dioxide Chemical compound O=[Si]=O VYPSYNLAJGMNEJ-UHFFFAOYSA-N 0.000 abstract 2
- 238000009792 diffusion process Methods 0.000 abstract 2
- 239000002019 doping agent Substances 0.000 abstract 2
- 229910052581 Si3N4 Inorganic materials 0.000 abstract 1
- 229910052787 antimony Inorganic materials 0.000 abstract 1
- 229910052785 arsenic Inorganic materials 0.000 abstract 1
- 230000002708 enhancing effect Effects 0.000 abstract 1
- 238000005530 etching Methods 0.000 abstract 1
- 229910052733 gallium Inorganic materials 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229910052698 phosphorus Inorganic materials 0.000 abstract 1
- 235000012239 silicon dioxide Nutrition 0.000 abstract 1
- 239000000377 silicon dioxide Substances 0.000 abstract 1
- HQVNEWCFYHHQES-UHFFFAOYSA-N silicon nitride Chemical compound N12[Si]34N5[Si]62N3[Si]51N64 HQVNEWCFYHHQES-UHFFFAOYSA-N 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L23/00—Details of semiconductor or other solid state devices
- H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
- H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L29/00—Semiconductor devices adapted for rectifying, amplifying, oscillating or switching, or capacitors or resistors with at least one potential-jump barrier or surface barrier, e.g. PN junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/0001—Technical content checked by a classifier
- H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
Abstract
1,150,834. Semi-conductor devices. RADIO CORPORATION OF AMERICA. 20 June, 1967 [5 Oct., 1966], No. 28474/67. Heading H1K. A photomask 50 used in semi-conductor device manufacture has at least one opaque portion 52 aligned with a corresponding aperture 38 which has been initially opened in a first masking layer 33 and subsequently closed by a second masking layer 40, the opaque portion 52 being larger in area than the aperture 38 so that any slight misalignment is accommodated and the aperture 38 can be accurately reopened. The embodiment comprises an NPN transistor, formed from a Si wafer carrying a grown or deposited first masking layer (33), Fig. 4 (not shown), of silicon dioxide or nitride. Apertures (36, 38) are opened simultaneously in the layer (33) by a photolithographic process using a single photomask, and a second thinner oxide masking layer (40), Fig. 5 (not shown), is deposited to cover the entire surface, including the apertures. Two apertures (38) are then opened again, leaving the third one (36) closed, by a photolithographic etching process using the photomask 50, Fig. 6. P+ contact regions (28), Fig. 8 (not shown) are diffused from vapour through the apertures (38), suitable dopants being B, Al, Ga, or In. The layer (40) may be removed at this stage from the aperture (36) by the same technique as that used for apertures (38). Alternatively the remaining portion of layer (40) may be left on until after the next step. A further oxide layer (60), Fig. 10 (not shown), is then deposited, and the aperture (36) reopened again, also using the same technique as above. The P type base region (24) is then formed by B-diffusion through the aperture (36), linking with the P+ contact regions (28). In an alternative step the apertures (38) may be left open during diffusion of the base region (24), further enhancing the conductivity of part of the contact regions (28). The N+ type emitter region (22), Fig. 11 (not shown), is diffused into the base region (24), through the same aperture (36), the dopant being P, As or Sb, and the remaining oxide masks are removed, leaving only the original masking layer (30). Al or Au electrodes are then applied, excess material being etched away using a suitable mask. Several such transistors may be formed in a single Si slice, and subsequently separated by dicing.
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US58447966A | 1966-10-05 | 1966-10-05 |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| GB1150834A true GB1150834A (en) | 1969-05-07 |
Family
ID=24337481
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| GB2847467A Expired GB1150834A (en) | 1966-10-05 | 1967-06-20 | Method of fabricating semiconductor devices |
Country Status (4)
| Country | Link |
|---|---|
| DE (1) | DE1614375B2 (en) |
| ES (1) | ES342567A1 (en) |
| GB (1) | GB1150834A (en) |
| SE (1) | SE327015B (en) |
Families Citing this family (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS4929785B1 (en) * | 1970-10-30 | 1974-08-07 | ||
| US3928081A (en) * | 1973-10-26 | 1975-12-23 | Signetics Corp | Method for fabricating semiconductor devices using composite mask and ion implantation |
-
1967
- 1967-06-20 GB GB2847467A patent/GB1150834A/en not_active Expired
- 1967-06-22 SE SE08957/67A patent/SE327015B/xx unknown
- 1967-06-30 DE DE19671614375 patent/DE1614375B2/en not_active Ceased
- 1967-07-03 ES ES342567A patent/ES342567A1/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| SE327015B (en) | 1970-08-10 |
| DE1614375B2 (en) | 1972-11-16 |
| ES342567A1 (en) | 1968-08-01 |
| DE1614375A1 (en) | 1970-05-21 |
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Legal Events
| Date | Code | Title | Description |
|---|---|---|---|
| PS | Patent sealed | ||
| PCNP | Patent ceased through non-payment of renewal fee |