GB1347849A - Metal oxide semiconductor transistors - Google Patents

Metal oxide semiconductor transistors

Info

Publication number
GB1347849A
GB1347849A GB1347849DA GB1347849A GB 1347849 A GB1347849 A GB 1347849A GB 1347849D A GB1347849D A GB 1347849DA GB 1347849 A GB1347849 A GB 1347849A
Authority
GB
United Kingdom
Prior art keywords
argon
slice
baseplate
islands
photoresist
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired
Application number
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
National Research Development Corp UK
Original Assignee
National Research Development Corp UK
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by National Research Development Corp UK filed Critical National Research Development Corp UK
Publication of GB1347849A publication Critical patent/GB1347849A/en
Expired legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/28Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293Organic, e.g. plastic
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001Technical content checked by a classifier
    • H01L2924/0002Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Manufacturing & Machinery (AREA)
  • Ceramic Engineering (AREA)
  • Drying Of Semiconductors (AREA)

Abstract

1347849 Sputter-etching NATIONAL RESEARCH DEVELOPMENT CORP 13 July 1972 [21 April 1971] 10446/71 Heading B3V [Also in Divisions H1 and C7] A MOST comprising a N-type silicon slice oriented [111] is thermally oxidized in dry O 2 to produce a coating, subsequently annealed in N 2 and rapidly cooled in N 2 ; after which it is sputtered with Mo or Wo. It is then coated with a photoresist apertured to define selected areas, heated, and mounted on baseplate 10 of an exhausted sputtering apparatus into which argon is admitted at reduced pressure. A ceramic insulated copper electrode 2 with a molybdenum sheath 26 and insulated cooling ducts 28 shielded at 34, 35 is connected to RF generator 36 and match network 38 also connected to baseplate 10 and the slice to be etched is placed on sheath 26 (Fig. 1) and the Mo and SiO 2 layers are removed by sputter etching in the exposed areas; after which the enclosed atmosphere is changed to O 2 and sputtering continued to remove the photoresist, after which the slice has openings made to its surface between islands 44, 46 of Mo overlying SiO 2 (Fig. 4). A boron glass layer 54 is then deposited on the surface by pyrolysis of tetra ethyl ortho silicate and triethyl borate in argon carrier, and heated in argon to diffuse Bo into the areas defined by the openings to form drain and source zones 56, 58, which underlap the edges of the islands. Contact windows to the zones and the gate 52 are cut photo mechanically in the glass, and Al is vacuum evaporated and patterned to form contact pads 62, 64, 66 and interconnections; after which the device is thermally annealed in wet N 2 or O 2 .
GB1347849D 1971-04-21 1971-04-21 Metal oxide semiconductor transistors Expired GB1347849A (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB1044671 1971-04-21

Publications (1)

Publication Number Publication Date
GB1347849A true GB1347849A (en) 1974-02-27

Family

ID=9968013

Family Applications (1)

Application Number Title Priority Date Filing Date
GB1347849D Expired GB1347849A (en) 1971-04-21 1971-04-21 Metal oxide semiconductor transistors

Country Status (1)

Country Link
GB (1) GB1347849A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2159753A (en) * 1984-03-06 1985-12-11 Asm Fico Tooling Method and apparatus for cleaning lead pins and the like before soldering operations

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2159753A (en) * 1984-03-06 1985-12-11 Asm Fico Tooling Method and apparatus for cleaning lead pins and the like before soldering operations

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Legal Events

Date Code Title Description
PS Patent sealed
PLNP Patent lapsed through nonpayment of renewal fees