FR3096516B1 - Dispositif intégré de protection contre les décharges électrostatiques - Google Patents

Dispositif intégré de protection contre les décharges électrostatiques Download PDF

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Publication number
FR3096516B1
FR3096516B1 FR1905367A FR1905367A FR3096516B1 FR 3096516 B1 FR3096516 B1 FR 3096516B1 FR 1905367 A FR1905367 A FR 1905367A FR 1905367 A FR1905367 A FR 1905367A FR 3096516 B1 FR3096516 B1 FR 3096516B1
Authority
FR
France
Prior art keywords
electrostatic discharge
protection device
power
discharge protection
integrated electrostatic
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
FR1905367A
Other languages
English (en)
Other versions
FR3096516A1 (fr
Inventor
François Tailliet
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1905367A priority Critical patent/FR3096516B1/fr
Priority to US16/877,935 priority patent/US11244941B2/en
Priority to CN202020863679.8U priority patent/CN212277198U/zh
Priority to CN202010436923.7A priority patent/CN111987093A/zh
Publication of FR3096516A1 publication Critical patent/FR3096516A1/fr
Application granted granted Critical
Publication of FR3096516B1 publication Critical patent/FR3096516B1/fr
Active legal-status Critical Current
Anticipated expiration legal-status Critical

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0292—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using a specific configuration of the conducting means connecting the protective devices, e.g. ESD buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/48—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor
    • H01L23/50—Arrangements for conducting electric current to or from the solid state body in operation, e.g. leads, terminal arrangements ; Selection of materials therefor for integrated circuit devices, e.g. power bus, number of leads
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H01L23/5286—Arrangements of power or ground buses
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0259—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices using bipolar transistors as protective elements
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0248—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection
    • H01L27/0251—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices
    • H01L27/0296—Particular design considerations for integrated circuits for electrical or thermal protection, e.g. electrostatic discharge [ESD] protection for MOS devices involving a specific disposition of the protective devices

Abstract

Le circuit intégré comporte un premier rail d’alimentation comprenant un arbre d'alimentation (VDDTR) configuré pour distribuer une tension d’alimentation dans des éléments actifs du circuit (CI), et un dispositif de protection contre les décharges électrostatiques (ESD) comprenant un deuxième rail d’alimentation (VDDBUS) configuré pour écouler un courant de décharge électrostatique (IESDbus) entre une broche d’alimentation (VDD) et une broche de masse (GND), le deuxième rail d’alimentation (VDDBUS) n’étant connecté à aucun élément actif du circuit (CI). Figure de l’abrégé : figure 1
FR1905367A 2019-05-22 2019-05-22 Dispositif intégré de protection contre les décharges électrostatiques Active FR3096516B1 (fr)

Priority Applications (4)

Application Number Priority Date Filing Date Title
FR1905367A FR3096516B1 (fr) 2019-05-22 2019-05-22 Dispositif intégré de protection contre les décharges électrostatiques
US16/877,935 US11244941B2 (en) 2019-05-22 2020-05-19 Integrated device for protection from electrostatic discharges
CN202020863679.8U CN212277198U (zh) 2019-05-22 2020-05-21 集成电路
CN202010436923.7A CN111987093A (zh) 2019-05-22 2020-05-21 用于保护不受静电放电伤害的集成器件

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1905367 2019-05-22
FR1905367A FR3096516B1 (fr) 2019-05-22 2019-05-22 Dispositif intégré de protection contre les décharges électrostatiques

Publications (2)

Publication Number Publication Date
FR3096516A1 FR3096516A1 (fr) 2020-11-27
FR3096516B1 true FR3096516B1 (fr) 2021-06-04

Family

ID=67810883

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1905367A Active FR3096516B1 (fr) 2019-05-22 2019-05-22 Dispositif intégré de protection contre les décharges électrostatiques

Country Status (3)

Country Link
US (1) US11244941B2 (fr)
CN (2) CN212277198U (fr)
FR (1) FR3096516B1 (fr)

Families Citing this family (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3119493A1 (fr) 2021-01-29 2022-08-05 Stmicroelectronics (Rousset) Sas Dispositif de protection contre les décharges électrostatiques

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE59510495D1 (de) * 1995-04-06 2003-01-16 Infineon Technologies Ag Integrierte Halbleiterschaltung mit einem Schutzmittel
US6144542A (en) * 1998-12-15 2000-11-07 Taiwan Semiconductor Manufacturing Co., Ltd. ESD bus lines in CMOS IC's for whole-chip ESD protection
JP3908669B2 (ja) * 2003-01-20 2007-04-25 株式会社東芝 静電気放電保護回路装置
US7746606B2 (en) * 2004-01-12 2010-06-29 Conexant Systems, Inc. ESD protection for integrated circuits having ultra thin gate oxides
GB2430821B (en) * 2004-02-07 2008-06-04 Samsung Electronics Co Ltd Buffer circuit having electrostatic discharge protection
KR100996171B1 (ko) * 2008-12-31 2010-11-24 주식회사 하이닉스반도체 집적회로
JP2015180050A (ja) * 2014-02-26 2015-10-08 セイコーエプソン株式会社 半導体集積回路装置及びそれを用いた電子機器
US10826290B2 (en) * 2016-12-23 2020-11-03 Nxp B.V. Electrostatic discharge (ESD) protection for use with an internal floating ESD rail

Also Published As

Publication number Publication date
US11244941B2 (en) 2022-02-08
US20200373295A1 (en) 2020-11-26
FR3096516A1 (fr) 2020-11-27
CN212277198U (zh) 2021-01-01
CN111987093A (zh) 2020-11-24

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