FR3021803B1 - Cellules memoire jumelles accessibles individuellement en lecture - Google Patents

Cellules memoire jumelles accessibles individuellement en lecture

Info

Publication number
FR3021803B1
FR3021803B1 FR1454893A FR1454893A FR3021803B1 FR 3021803 B1 FR3021803 B1 FR 3021803B1 FR 1454893 A FR1454893 A FR 1454893A FR 1454893 A FR1454893 A FR 1454893A FR 3021803 B1 FR3021803 B1 FR 3021803B1
Authority
FR
France
Prior art keywords
twinly
memory cells
individually reading
accessible individually
accessible
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR1454893A
Other languages
English (en)
Other versions
FR3021803A1 (fr
Inventor
Rosa Francesco La
Stephan Niel
Arnaud Regnier
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
STMicroelectronics Rousset SAS
Original Assignee
STMicroelectronics Rousset SAS
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by STMicroelectronics Rousset SAS filed Critical STMicroelectronics Rousset SAS
Priority to FR1454893A priority Critical patent/FR3021803B1/fr
Priority to US14/671,606 priority patent/US9653470B2/en
Priority to CN201910456430.7A priority patent/CN110265077B/zh
Priority to CN201520251293.0U priority patent/CN204966056U/zh
Priority to CN201510196923.3A priority patent/CN105280229B/zh
Publication of FR3021803A1 publication Critical patent/FR3021803A1/fr
Application granted granted Critical
Publication of FR3021803B1 publication Critical patent/FR3021803B1/fr
Expired - Fee Related legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0441—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing multiple floating gate devices, e.g. separate read-and-write FAMOS transistors with connected floating gates
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/28—Manufacture of electrodes on semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/268
    • H01L21/28008—Making conductor-insulator-semiconductor electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/0603—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions characterised by particular constructional design considerations, e.g. for preventing surface leakage, for controlling electric field concentration or for internal isolations regions
    • H01L29/0642—Isolation within the component, i.e. internal isolation
    • H01L29/0649—Dielectric regions, e.g. SiO2 regions, air gaps
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42324—Gate electrodes for transistors with a floating gate
    • H01L29/42328—Gate electrodes for transistors with a floating gate with at least one additional gate other than the floating gate and the control gate, e.g. program gate, erase gate or select gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/66007—Multistep manufacturing processes
    • H01L29/66075—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials
    • H01L29/66227—Multistep manufacturing processes of devices having semiconductor bodies comprising group 14 or group 13/15 materials the devices being controllable only by the electric current supplied or the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched, e.g. three-terminal devices
    • H01L29/66409—Unipolar field-effect transistors
    • H01L29/66477—Unipolar field-effect transistors with an insulated gate, i.e. MISFET
    • H01L29/66825—Unipolar field-effect transistors with an insulated gate, i.e. MISFET with a floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7881—Programmable transistors with only two possible levels of programmation
    • H01L29/7883—Programmable transistors with only two possible levels of programmation charging by tunnelling of carriers, e.g. Fowler-Nordheim tunnelling
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/10—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the top-view layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Geometry (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)
FR1454893A 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture Expired - Fee Related FR3021803B1 (fr)

Priority Applications (5)

Application Number Priority Date Filing Date Title
FR1454893A FR3021803B1 (fr) 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture
US14/671,606 US9653470B2 (en) 2014-05-28 2015-03-27 Individually read-accessible twin memory cells
CN201910456430.7A CN110265077B (zh) 2014-05-28 2015-04-23 单独地读出可访问的配对存储器单元
CN201520251293.0U CN204966056U (zh) 2014-05-28 2015-04-23 非易失性存储器以及在半导体芯片上的集成电路
CN201510196923.3A CN105280229B (zh) 2014-05-28 2015-04-23 单独地读出可访问的配对存储器单元

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR1454893A FR3021803B1 (fr) 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture

Publications (2)

Publication Number Publication Date
FR3021803A1 FR3021803A1 (fr) 2015-12-04
FR3021803B1 true FR3021803B1 (fr) 2017-10-13

Family

ID=51168254

Family Applications (1)

Application Number Title Priority Date Filing Date
FR1454893A Expired - Fee Related FR3021803B1 (fr) 2014-05-28 2014-05-28 Cellules memoire jumelles accessibles individuellement en lecture

Country Status (3)

Country Link
US (1) US9653470B2 (fr)
CN (3) CN204966056U (fr)
FR (1) FR3021803B1 (fr)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR3021803B1 (fr) * 2014-05-28 2017-10-13 Stmicroelectronics Rousset Cellules memoire jumelles accessibles individuellement en lecture
FR3021804B1 (fr) 2014-05-28 2017-09-01 Stmicroelectronics Rousset Cellule memoire non volatile duale comprenant un transistor d'effacement
FR3025353B1 (fr) * 2014-09-03 2016-09-09 Stmicroelectronics Rousset Memoire non volatile composite a effacement par page ou par mot
FR3036221B1 (fr) 2015-05-11 2017-04-28 Stmicroelectronics Rousset Structure d'interconnexion de cellules memoire jumelles
FR3049380B1 (fr) 2016-03-22 2018-11-23 Stmicroelectronics (Rousset) Sas Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre
JP6739327B2 (ja) * 2016-12-27 2020-08-12 ルネサスエレクトロニクス株式会社 半導体装置
TWI632558B (zh) * 2017-05-01 2018-08-11 卡比科技有限公司 非揮發性記憶體裝置及其操作方法
US11011533B2 (en) 2018-01-10 2021-05-18 Ememory Technology Inc. Memory structure and programing and reading methods thereof
JP2019179799A (ja) * 2018-03-30 2019-10-17 ルネサスエレクトロニクス株式会社 半導体記憶装置

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US5182725A (en) 1987-11-20 1993-01-26 Mitsubishi Denki Kabushiki Kaisha Nonvolatile semiconductor memory device with reduced variation in source potential of floating gate type memory transistor and operating method therefor
US6433382B1 (en) * 1995-04-06 2002-08-13 Motorola, Inc. Split-gate vertically oriented EEPROM device and process
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JP3332152B2 (ja) * 1998-02-18 2002-10-07 日本電気株式会社 不揮発性半導体記憶装置
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US6828618B2 (en) 2002-10-30 2004-12-07 Freescale Semiconductor, Inc. Split-gate thin-film storage NVM cell
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JP5417853B2 (ja) * 2009-01-15 2014-02-19 凸版印刷株式会社 不揮発性半導体メモリセル及び不揮発性半導体メモリ装置
JP5193830B2 (ja) * 2008-12-03 2013-05-08 株式会社東芝 不揮発性半導体メモリ
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US8958245B2 (en) 2010-06-17 2015-02-17 Ememory Technology Inc. Logic-based multiple time programming memory cell compatible with generic CMOS processes
US8582363B2 (en) 2011-01-31 2013-11-12 Aplus Flash Technology, Inc. Method and apparatus for management of over-erasure in NAND-based NOR-type flash memory
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FR2987696B1 (fr) 2012-03-05 2014-11-21 St Microelectronics Rousset Procede de lecture ecriture de cellules memoire non volatiles
JP5972700B2 (ja) 2012-07-31 2016-08-17 ルネサスエレクトロニクス株式会社 メモリ装置
FR2996680A1 (fr) * 2012-10-10 2014-04-11 St Microelectronics Rousset Memoire non volatile comportant des transistors de selection verticaux
US20140198583A1 (en) * 2013-01-17 2014-07-17 Infineon Technologies Ag Method and System for Reducing the Size of Nonvolatile Memories
TW201508753A (zh) 2013-08-29 2015-03-01 Chrong-Jung Lin 記憶體元件、記憶體陣列與其操作方法
FR3021804B1 (fr) 2014-05-28 2017-09-01 Stmicroelectronics Rousset Cellule memoire non volatile duale comprenant un transistor d'effacement
FR3021803B1 (fr) * 2014-05-28 2017-10-13 Stmicroelectronics Rousset Cellules memoire jumelles accessibles individuellement en lecture

Also Published As

Publication number Publication date
CN110265077A (zh) 2019-09-20
CN105280229A (zh) 2016-01-27
US9653470B2 (en) 2017-05-16
CN105280229B (zh) 2019-07-16
CN204966056U (zh) 2016-01-13
CN110265077B (zh) 2023-05-12
US20150348981A1 (en) 2015-12-03
FR3021803A1 (fr) 2015-12-04

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