FR3049380B1 - Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre - Google Patents

Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre Download PDF

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Publication number
FR3049380B1
FR3049380B1 FR1652445A FR1652445A FR3049380B1 FR 3049380 B1 FR3049380 B1 FR 3049380B1 FR 1652445 A FR1652445 A FR 1652445A FR 1652445 A FR1652445 A FR 1652445A FR 3049380 B1 FR3049380 B1 FR 3049380B1
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Prior art keywords
memory device
volatile memory
reading
bitter
selection transistor
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Expired - Fee Related
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FR1652445A
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English (en)
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FR3049380A1 (fr
Inventor
Francesco La Rosa
Stephan Niel
Arnaud Regnier
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STMicroelectronics Rousset SAS
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STMicroelectronics Rousset SAS
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Priority to FR1652445A priority Critical patent/FR3049380B1/fr
Priority to US15/365,433 priority patent/US9825186B2/en
Publication of FR3049380A1 publication Critical patent/FR3049380A1/fr
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Publication of FR3049380B1 publication Critical patent/FR3049380B1/fr
Expired - Fee Related legal-status Critical Current
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    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H01L29/7889—Vertical transistors, i.e. transistors having source and drain not in the same horizontal plane
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/08—Address circuits; Decoders; Word-line control circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/34—Determination of programming status, e.g. threshold voltage, overprogramming or underprogramming, retention
    • G11C16/3418—Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • G11C16/3427—Circuits or methods to prevent or reduce disturbance of the state of a memory cell when neighbouring cells are read or written
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/788—Field effect transistors with field effect produced by an insulated gate with floating gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/792—Field effect transistors with field effect produced by an insulated gate with charge trapping gate insulator, e.g. MNOS-memory transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/20—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B41/23—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B41/27—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B41/00—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates
    • H10B41/30—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region
    • H10B41/35—Electrically erasable-and-programmable ROM [EEPROM] devices comprising floating gates characterised by the memory core region with a cell select transistor, e.g. NAND
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/20—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels
    • H10B43/23—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels
    • H10B43/27—EEPROM devices comprising charge-trapping gate insulators characterised by three-dimensional arrangements, e.g. with cells on different height levels with source and drain on different levels, e.g. with sloping channels the channels comprising vertical portions, e.g. U-shaped channels
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • H10B43/35—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region with cell select transistors, e.g. NAND

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Non-Volatile Memory (AREA)
  • Read Only Memory (AREA)

Abstract

Le dispositif de mémoire non volatile comprend des cellules-mémoires (C3,j) comprenant chacune un transistor d'état (T3,j) sélectionnable possédant une grille flottante et une grille de commande (CG3). Le transistor d'état (T3,j) est du type à appauvrissement et avantageusement configuré pour présenter une tension de seuil de préférence négative lorsque la cellule-mémoire est dans un état vierge. On peut alors appliquer lors de la lecture de la cellule-mémoire, une tension de lecture nulle sur la grille de commande (CG3) ainsi que sur les grilles de commande des transistors d'états de toutes les cellules-mémoires du dispositif de mémoire.
FR1652445A 2016-03-22 2016-03-22 Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre Expired - Fee Related FR3049380B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR1652445A FR3049380B1 (fr) 2016-03-22 2016-03-22 Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre
US15/365,433 US9825186B2 (en) 2016-03-22 2016-11-30 Read performance of a non-volatile memory device, in particular a non-volatile memory device with buried selection transistor

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FR1652445A FR3049380B1 (fr) 2016-03-22 2016-03-22 Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre
FR1652445 2016-03-22

Publications (2)

Publication Number Publication Date
FR3049380A1 FR3049380A1 (fr) 2017-09-29
FR3049380B1 true FR3049380B1 (fr) 2018-11-23

Family

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FR1652445A Expired - Fee Related FR3049380B1 (fr) 2016-03-22 2016-03-22 Amelioration des performances en lecture d'un dispositif de memoire non volatile, en particulier un dispositif de memoire non volatile avec transistor de selection enterre

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US (1) US9825186B2 (fr)
FR (1) FR3049380B1 (fr)

Families Citing this family (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11823739B2 (en) 2020-04-06 2023-11-21 Crossbar, Inc. Physically unclonable function (PUF) generation involving high side programming of bits
CN115240735A (zh) 2020-04-06 2022-10-25 昕原半导体(上海)有限公司 利用芯片上电阻存储器阵列的不可克隆特性的独特芯片标识符
FR3125351B1 (fr) * 2021-07-13 2023-06-23 St Microelectronics Rousset Dispositif de mémoire non volatile lisible uniquement un nombre de fois prédéterminé
FR3125374A1 (fr) 2021-07-13 2023-01-20 Stmicroelectronics (Rousset) Sas Dispositif de fonction physiquement non clonable
FR3133248A1 (fr) 2022-03-07 2023-09-08 Stmicroelectronics (Rousset) Sas Protection d’un circuit intégré

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05110108A (ja) * 1991-10-18 1993-04-30 Mitsubishi Electric Corp Ｅｐｒｏｍ
FR2794895B1 (fr) 1999-06-11 2001-09-14 St Microelectronics Sa Dispositif semiconducteur integre de memoire morte
US6432761B1 (en) * 1999-10-01 2002-08-13 Microchip Technology Incorporated Apparatus and method for independent threshold voltage control of memory cell and select gate in a split-EEPROM
TW484213B (en) 2001-04-24 2002-04-21 Ememory Technology Inc Forming method and operation method of trench type separation gate nonvolatile flash memory cell structure
US7457156B2 (en) * 2004-09-02 2008-11-25 Micron Technology, Inc. NAND flash depletion cell structure
KR100706789B1 (ko) 2005-11-17 2007-04-12 삼성전자주식회사 비휘발성 메모리 소자
US20120201079A1 (en) 2011-02-04 2012-08-09 Noboru Shibata Semiconductor memory device in which capacitance between bit lines is reduced, and method of manufacturing the same
US8901634B2 (en) * 2012-03-05 2014-12-02 Stmicroelectronics (Rousset) Sas Nonvolatile memory cells with a vertical selection gate of variable depth
FR3021803B1 (fr) * 2014-05-28 2017-10-13 Stmicroelectronics Rousset Cellules memoire jumelles accessibles individuellement en lecture
FR3036221B1 (fr) 2015-05-11 2017-04-28 Stmicroelectronics Rousset Structure d'interconnexion de cellules memoire jumelles

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Publication number Publication date
FR3049380A1 (fr) 2017-09-29
US9825186B2 (en) 2017-11-21
US20170278577A1 (en) 2017-09-28

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