SG11202005283YA - Auto-referenced memory cell read techniques - Google Patents
Auto-referenced memory cell read techniquesInfo
- Publication number
- SG11202005283YA SG11202005283YA SG11202005283YA SG11202005283YA SG11202005283YA SG 11202005283Y A SG11202005283Y A SG 11202005283YA SG 11202005283Y A SG11202005283Y A SG 11202005283YA SG 11202005283Y A SG11202005283Y A SG 11202005283YA SG 11202005283Y A SG11202005283Y A SG 11202005283YA
- Authority
- SG
- Singapore
- Prior art keywords
- auto
- memory cell
- cell read
- referenced memory
- read techniques
- Prior art date
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5621—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
- G11C11/5642—Sensing or reading circuits; Data output circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C11/56—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
- G11C11/5678—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/003—Cell access
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/0033—Disturbance prevention or evaluation; Refreshing of disturbed memory data
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/08—Address circuits; Decoders; Word-line control circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/10—Programming or data input circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/30—Power supply circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C16/00—Erasable programmable read-only memories
- G11C16/02—Erasable programmable read-only memories electrically programmable
- G11C16/06—Auxiliary circuits, e.g. for writing into memory
- G11C16/32—Timing circuits
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/04—Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/14—Dummy cell management; Sense reference voltage generators
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C8/00—Arrangements for selecting an address in a digital store
- G11C8/14—Word line organisation; Word line lay-out
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
- G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
- G11C13/0021—Auxiliary circuits
- G11C13/004—Reading or sensing circuits or methods
- G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2211/00—Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
- G11C2211/56—Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
- G11C2211/563—Multilevel memory reading aspects
- G11C2211/5634—Reference cells
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/71—Three dimensional array
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C2213/00—Indexing scheme relating to G11C13/00 for features not covered by this group
- G11C2213/70—Resistive array aspects
- G11C2213/76—Array using an access device for each cell which being not a transistor and not a diode
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US15/853,328 US10566052B2 (en) | 2017-12-22 | 2017-12-22 | Auto-referenced memory cell read techniques |
PCT/US2018/067287 WO2019126746A1 (en) | 2017-12-22 | 2018-12-21 | Auto-referenced memory cell read techniques |
Publications (1)
Publication Number | Publication Date |
---|---|
SG11202005283YA true SG11202005283YA (en) | 2020-07-29 |
Family
ID=66950515
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
SG11202005283YA SG11202005283YA (en) | 2017-12-22 | 2018-12-21 | Auto-referenced memory cell read techniques |
Country Status (7)
Country | Link |
---|---|
US (4) | US10566052B2 (en) |
EP (1) | EP3729429A4 (en) |
JP (1) | JP6972353B2 (en) |
KR (2) | KR102367907B1 (en) |
CN (2) | CN115527580A (en) |
SG (1) | SG11202005283YA (en) |
WO (1) | WO2019126746A1 (en) |
Families Citing this family (29)
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JP2019164850A (en) * | 2018-03-19 | 2019-09-26 | 東芝メモリ株式会社 | Memory system |
US10388362B1 (en) * | 2018-05-08 | 2019-08-20 | Micron Technology, Inc. | Half-width, double pumped data path |
US10714185B2 (en) * | 2018-10-24 | 2020-07-14 | Micron Technology, Inc. | Event counters for memory operations |
KR20200090556A (en) * | 2019-01-21 | 2020-07-29 | 에스케이하이닉스 주식회사 | Storage device and operating method thereof |
KR102656527B1 (en) * | 2019-04-05 | 2024-04-15 | 삼성전자주식회사 | Memory device |
US11386946B2 (en) | 2019-07-16 | 2022-07-12 | Micron Technology, Inc. | Apparatuses and methods for tracking row accesses |
US11164619B2 (en) * | 2019-08-19 | 2021-11-02 | Micron Technology, Inc. | Distribution-following access operations for a memory device |
US10908845B1 (en) | 2019-08-27 | 2021-02-02 | Micron Technology, Inc. | Managing threshold voltage drift based on a temperature-dependent slope of the threshold voltage drift of a memory sub-system |
US11349069B2 (en) * | 2019-12-16 | 2022-05-31 | Taiwan Semiconductor Manufacturing Company Limited | Resistive memory devices using a carbon-based conductor line and methods for forming the same |
US11262937B2 (en) | 2020-05-01 | 2022-03-01 | Micron Technology, Inc. | Balancing data for storage in a memory device |
CN115485776A (en) | 2020-05-13 | 2022-12-16 | 美光科技公司 | Counter-based method and system for accessing memory cells |
US11302390B2 (en) | 2020-07-10 | 2022-04-12 | Micron Technology, Inc. | Reading a multi-level memory cell |
US11355209B2 (en) | 2020-07-10 | 2022-06-07 | Micron Technology, Inc. | Accessing a multi-level memory cell |
WO2022013589A1 (en) * | 2020-07-14 | 2022-01-20 | Micron Technology, Inc | Methods and systems for improving access to memory cells |
US11288160B2 (en) * | 2020-08-17 | 2022-03-29 | Micron Technology, Inc. | Threshold voltage distribution adjustment for buffer |
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US11514983B2 (en) | 2021-04-02 | 2022-11-29 | Micron Technology, Inc. | Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells |
US11514985B2 (en) | 2021-04-05 | 2022-11-29 | Micron Technology, Inc. | Spike current suppression in a memory array |
US11348640B1 (en) | 2021-04-05 | 2022-05-31 | Micron Technology, Inc. | Charge screening structure for spike current suppression in a memory array |
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US11527287B1 (en) | 2021-05-27 | 2022-12-13 | Micron Technology, Inc. | Drift aware read operations |
US11664074B2 (en) | 2021-06-02 | 2023-05-30 | Micron Technology, Inc. | Programming intermediate state to store data in self-selecting memory cells |
US11694747B2 (en) | 2021-06-03 | 2023-07-04 | Micron Technology, Inc. | Self-selecting memory cells configured to store more than one bit per memory cell |
US11538522B1 (en) | 2021-06-30 | 2022-12-27 | Micron Technology, Inc. | Systems and methods for adaptive self-referenced reads of memory devices |
US11562790B1 (en) | 2021-06-30 | 2023-01-24 | Micron Technology, Inc. | Systems and methods for adaptive self-referenced reads of memory devices |
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-
2017
- 2017-12-22 US US15/853,328 patent/US10566052B2/en active Active
-
2018
- 2018-12-21 CN CN202210948644.8A patent/CN115527580A/en active Pending
- 2018-12-21 CN CN201880081341.2A patent/CN111480200B/en active Active
- 2018-12-21 EP EP18891040.0A patent/EP3729429A4/en active Pending
- 2018-12-21 SG SG11202005283YA patent/SG11202005283YA/en unknown
- 2018-12-21 JP JP2020533220A patent/JP6972353B2/en active Active
- 2018-12-21 KR KR1020207020354A patent/KR102367907B1/en active IP Right Grant
- 2018-12-21 KR KR1020227005290A patent/KR102461132B1/en active IP Right Grant
- 2018-12-21 WO PCT/US2018/067287 patent/WO2019126746A1/en unknown
-
2019
- 2019-12-27 US US16/729,061 patent/US10741243B2/en active Active
-
2020
- 2020-07-07 US US16/922,883 patent/US10937491B2/en active Active
-
2021
- 2021-02-02 US US17/165,579 patent/US11282571B2/en active Active
Also Published As
Publication number | Publication date |
---|---|
EP3729429A4 (en) | 2021-07-28 |
KR102461132B1 (en) | 2022-11-01 |
US10937491B2 (en) | 2021-03-02 |
US10741243B2 (en) | 2020-08-11 |
EP3729429A1 (en) | 2020-10-28 |
US11282571B2 (en) | 2022-03-22 |
US20210257022A1 (en) | 2021-08-19 |
US20200335159A1 (en) | 2020-10-22 |
CN111480200B (en) | 2022-08-23 |
US20200211641A1 (en) | 2020-07-02 |
JP6972353B2 (en) | 2021-11-24 |
KR102367907B1 (en) | 2022-02-25 |
WO2019126746A1 (en) | 2019-06-27 |
JP2021508107A (en) | 2021-02-25 |
US10566052B2 (en) | 2020-02-18 |
US20190198096A1 (en) | 2019-06-27 |
KR20200089761A (en) | 2020-07-27 |
CN111480200A (en) | 2020-07-31 |
KR20220030302A (en) | 2022-03-10 |
CN115527580A (en) | 2022-12-27 |
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