EP3729429A4 - Auto-referenced memory cell read techniques - Google Patents

Auto-referenced memory cell read techniques Download PDF

Info

Publication number
EP3729429A4
EP3729429A4 EP18891040.0A EP18891040A EP3729429A4 EP 3729429 A4 EP3729429 A4 EP 3729429A4 EP 18891040 A EP18891040 A EP 18891040A EP 3729429 A4 EP3729429 A4 EP 3729429A4
Authority
EP
European Patent Office
Prior art keywords
auto
memory cell
cell read
referenced memory
read techniques
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18891040.0A
Other languages
German (de)
French (fr)
Other versions
EP3729429A1 (en
Inventor
Graziano Mirichigni
Marco Sforzin
Alessandro ORLANDO
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Publication of EP3729429A1 publication Critical patent/EP3729429A1/en
Publication of EP3729429A4 publication Critical patent/EP3729429A4/en
Pending legal-status Critical Current

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5621Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using charge storage in a floating gate
    • G11C11/5642Sensing or reading circuits; Data output circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C11/00Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/56Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency
    • G11C11/5678Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using storage elements with more than two stable states represented by steps, e.g. of voltage, current, phase, frequency using amorphous/crystalline phase transition storage elements
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/003Cell access
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/0033Disturbance prevention or evaluation; Refreshing of disturbed memory data
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/08Address circuits; Decoders; Word-line control circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/10Programming or data input circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/30Power supply circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C16/00Erasable programmable read-only memories
    • G11C16/02Erasable programmable read-only memories electrically programmable
    • G11C16/06Auxiliary circuits, e.g. for writing into memory
    • G11C16/32Timing circuits
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/04Arrangements for writing information into, or reading information out from, a digital store with means for avoiding disturbances due to temperature effects
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • G11C7/1006Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/14Dummy cell management; Sense reference voltage generators
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/14Word line organisation; Word line lay-out
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C13/00Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021Auxiliary circuits
    • G11C13/004Reading or sensing circuits or methods
    • G11C2013/0054Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2211/00Indexing scheme relating to digital stores characterized by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C2211/56Indexing scheme relating to G11C11/56 and sub-groups for features not covered by these groups
    • G11C2211/563Multilevel memory reading aspects
    • G11C2211/5634Reference cells
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/71Three dimensional array
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C2213/00Indexing scheme relating to G11C13/00 for features not covered by this group
    • G11C2213/70Resistive array aspects
    • G11C2213/76Array using an access device for each cell which being not a transistor and not a diode
EP18891040.0A 2017-12-22 2018-12-21 Auto-referenced memory cell read techniques Pending EP3729429A4 (en)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US15/853,328 US10566052B2 (en) 2017-12-22 2017-12-22 Auto-referenced memory cell read techniques
PCT/US2018/067287 WO2019126746A1 (en) 2017-12-22 2018-12-21 Auto-referenced memory cell read techniques

Publications (2)

Publication Number Publication Date
EP3729429A1 EP3729429A1 (en) 2020-10-28
EP3729429A4 true EP3729429A4 (en) 2021-07-28

Family

ID=66950515

Family Applications (1)

Application Number Title Priority Date Filing Date
EP18891040.0A Pending EP3729429A4 (en) 2017-12-22 2018-12-21 Auto-referenced memory cell read techniques

Country Status (7)

Country Link
US (4) US10566052B2 (en)
EP (1) EP3729429A4 (en)
JP (1) JP6972353B2 (en)
KR (2) KR102367907B1 (en)
CN (2) CN115527580A (en)
SG (1) SG11202005283YA (en)
WO (1) WO2019126746A1 (en)

Families Citing this family (29)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2019164850A (en) * 2018-03-19 2019-09-26 東芝メモリ株式会社 Memory system
US10388362B1 (en) * 2018-05-08 2019-08-20 Micron Technology, Inc. Half-width, double pumped data path
US10714185B2 (en) * 2018-10-24 2020-07-14 Micron Technology, Inc. Event counters for memory operations
KR20200090556A (en) * 2019-01-21 2020-07-29 에스케이하이닉스 주식회사 Storage device and operating method thereof
KR102656527B1 (en) * 2019-04-05 2024-04-15 삼성전자주식회사 Memory device
US11386946B2 (en) 2019-07-16 2022-07-12 Micron Technology, Inc. Apparatuses and methods for tracking row accesses
US11164619B2 (en) * 2019-08-19 2021-11-02 Micron Technology, Inc. Distribution-following access operations for a memory device
US10908845B1 (en) 2019-08-27 2021-02-02 Micron Technology, Inc. Managing threshold voltage drift based on a temperature-dependent slope of the threshold voltage drift of a memory sub-system
US11349069B2 (en) * 2019-12-16 2022-05-31 Taiwan Semiconductor Manufacturing Company Limited Resistive memory devices using a carbon-based conductor line and methods for forming the same
US11262937B2 (en) 2020-05-01 2022-03-01 Micron Technology, Inc. Balancing data for storage in a memory device
JP2023525118A (en) 2020-05-13 2023-06-14 マイクロン テクノロジー,インク. Counter-based method and system for accessing memory cells
US11302390B2 (en) 2020-07-10 2022-04-12 Micron Technology, Inc. Reading a multi-level memory cell
US11355209B2 (en) 2020-07-10 2022-06-07 Micron Technology, Inc. Accessing a multi-level memory cell
WO2022013589A1 (en) * 2020-07-14 2022-01-20 Micron Technology, Inc Methods and systems for improving access to memory cells
US11288160B2 (en) * 2020-08-17 2022-03-29 Micron Technology, Inc. Threshold voltage distribution adjustment for buffer
FR3118829A1 (en) * 2021-01-14 2022-07-15 Commissariat A L'energie Atomique Et Aux Energies Alternatives MATRIX OF ELEMENTARY SWITCHES FORMING A MESSAGE, ASSOCIATED WRITING AND READING PROCESSES
US11367484B1 (en) 2021-01-21 2022-06-21 Micron Technology, Inc. Multi-step pre-read for write operations in memory devices
CN112863573B (en) * 2021-01-27 2023-04-14 长江先进存储产业创新中心有限责任公司 Method for determining reference voltage for performing operation on memory
US11514983B2 (en) 2021-04-02 2022-11-29 Micron Technology, Inc. Identify the programming mode of memory cells based on cell statistics obtained during reading of the memory cells
US11664073B2 (en) 2021-04-02 2023-05-30 Micron Technology, Inc. Adaptively programming memory cells in different modes to optimize performance
US11615854B2 (en) 2021-04-02 2023-03-28 Micron Technology, Inc. Identify the programming mode of memory cells during reading of the memory cells
US11715520B2 (en) 2021-04-05 2023-08-01 Micron Technology, Inc. Socket structure for spike current suppression in a memory array
US11514985B2 (en) 2021-04-05 2022-11-29 Micron Technology, Inc. Spike current suppression in a memory array
US11348640B1 (en) 2021-04-05 2022-05-31 Micron Technology, Inc. Charge screening structure for spike current suppression in a memory array
US11527287B1 (en) 2021-05-27 2022-12-13 Micron Technology, Inc. Drift aware read operations
US11664074B2 (en) 2021-06-02 2023-05-30 Micron Technology, Inc. Programming intermediate state to store data in self-selecting memory cells
US11694747B2 (en) 2021-06-03 2023-07-04 Micron Technology, Inc. Self-selecting memory cells configured to store more than one bit per memory cell
US11562790B1 (en) 2021-06-30 2023-01-24 Micron Technology, Inc. Systems and methods for adaptive self-referenced reads of memory devices
US11538522B1 (en) 2021-06-30 2022-12-27 Micron Technology, Inc. Systems and methods for adaptive self-referenced reads of memory devices

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050018519A1 (en) * 2003-07-24 2005-01-27 Renesas Technology Corp. Semiconductor memory device capable of reducing power consumption during reading and standby
US20130272078A1 (en) * 2012-04-16 2013-10-17 Sony Corporation Storage controlling apparatus, memory system, information processing system and storage controlling method
WO2017018008A1 (en) * 2015-07-24 2017-02-02 ソニー株式会社 Encoding device, memory controller, communication system, and encoding method

Family Cites Families (41)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6781880B2 (en) 2002-07-19 2004-08-24 Micron Technology, Inc. Non-volatile memory erase circuitry
AU2002331580A1 (en) * 2002-08-14 2004-03-03 Intel Corporation Method for reading a structural phase-change memory
US6738298B1 (en) 2002-11-18 2004-05-18 Micron Technology, Inc. Automatic reference voltage regulation in a memory device
DE60317768T2 (en) 2003-04-10 2008-11-27 Stmicroelectronics S.R.L., Agrate Brianza Method for reading out a non-volatile memory device and associated device
WO2004109704A1 (en) * 2003-06-05 2004-12-16 Koninklijke Philips Electronics N.V. Integrity control for data stored in a non-volatile memory
JP2005100527A (en) 2003-09-25 2005-04-14 Matsushita Electric Ind Co Ltd Semiconductor nonvolatile storage device
US7079436B2 (en) * 2003-09-30 2006-07-18 Hewlett-Packard Development Company, L.P. Resistive cross point memory
DE602005018738D1 (en) 2005-03-03 2010-02-25 St Microelectronics Srl A time shift based reference cell emulation memory device
EP1699054A1 (en) 2005-03-03 2006-09-06 STMicroelectronics S.r.l. A memory device with a ramp-like voltage biasing structure and reduced number of reference cells
ITVA20050028A1 (en) 2005-05-03 2006-11-04 St Microelectronics Srl RAMP GENERATOR AND RELATIVE ROW DECODER FOR FLASH MEMORY
JP4936746B2 (en) * 2006-03-08 2012-05-23 ルネサスエレクトロニクス株式会社 Semiconductor device
CN100590735C (en) * 2006-08-23 2010-02-17 财团法人工业技术研究院 Multi-stable state read amplifier used for memory device
JP5214422B2 (en) 2008-02-15 2013-06-19 株式会社東芝 Data storage system
US7660152B2 (en) * 2008-04-30 2010-02-09 International Business Machines Corporation Method and apparatus for implementing self-referencing read operation for PCRAM devices
US8406048B2 (en) * 2008-08-08 2013-03-26 Marvell World Trade Ltd. Accessing memory using fractional reference voltages
JP2011181134A (en) 2010-02-26 2011-09-15 Elpida Memory Inc Method of controlling nonvolatile semiconductor device
US8531888B2 (en) * 2010-07-07 2013-09-10 Marvell World Trade Ltd. Determining optimal reference voltages for progressive reads in flash memory systems
US8737138B2 (en) 2010-11-18 2014-05-27 Micron Technology, Inc. Memory instruction including parameter to affect operating condition of memory
US8693252B2 (en) 2011-07-12 2014-04-08 Samsung Electronics Co., Ltd. Method and system for adjusting read voltage in flash memory device
US8767482B2 (en) 2011-08-18 2014-07-01 Micron Technology, Inc. Apparatuses, devices and methods for sensing a snapback event in a circuit
US8495285B2 (en) 2011-08-31 2013-07-23 Micron Technology, Inc. Apparatuses and methods of operating for memory endurance
JP5293860B1 (en) 2012-05-16 2013-09-18 富士ゼロックス株式会社 Serial communication system, image forming system, and transmission apparatus
JP5929790B2 (en) 2012-06-19 2016-06-08 ソニー株式会社 Storage control device, storage device, information processing system, and processing method therefor
US8832530B2 (en) * 2012-09-26 2014-09-09 Intel Corporation Techniques associated with a read and write window budget for a two level memory system
KR101934892B1 (en) 2012-10-17 2019-01-04 삼성전자 주식회사 Method for determining deterioration state of memory device and memory system using method thereof
US9141534B2 (en) 2012-12-14 2015-09-22 Sandisk Technologies Inc. Tracking read accesses to regions of non-volatile memory
US9275740B2 (en) 2013-08-05 2016-03-01 CNEXLABS, Inc. Method and apparatus for improving data integrity using threshold voltage recalibration
US9263136B1 (en) 2013-09-04 2016-02-16 Western Digital Technologies, Inc. Data retention flags in solid-state drives
US9312005B2 (en) * 2013-09-10 2016-04-12 Micron Technology, Inc. Accessing memory cells in parallel in a cross-point array
US9019754B1 (en) * 2013-12-17 2015-04-28 Micron Technology, Inc. State determination in resistance variable memory
DE102014207296A1 (en) 2014-04-16 2015-10-22 Robert Bosch Gmbh Apparatus and method for processing data
US9142271B1 (en) * 2014-06-24 2015-09-22 Intel Corporation Reference architecture in a cross-point memory
JP2016054017A (en) 2014-09-04 2016-04-14 株式会社東芝 Semiconductor memory device
US10320429B2 (en) 2015-03-04 2019-06-11 Toshiba Memory Corporation Memory controller, memory system and memory control method
US9460784B1 (en) 2015-04-22 2016-10-04 Micron Technology, Inc. Reference voltage generation apparatuses and methods
US10134470B2 (en) 2015-11-04 2018-11-20 Micron Technology, Inc. Apparatuses and methods including memory and operation of same
US9607691B1 (en) 2016-02-17 2017-03-28 Micron Technology, Inc. Memory cell architecture for multilevel cell programming
US10083731B2 (en) * 2016-03-11 2018-09-25 Micron Technology, Inc Memory cell sensing with storage component isolation
US10192606B2 (en) 2016-04-05 2019-01-29 Micron Technology, Inc. Charge extraction from ferroelectric memory cell using sense capacitors
US9892776B2 (en) 2016-06-13 2018-02-13 Micron Technology, Inc. Half density ferroelectric memory and operation
CN106898371B (en) * 2017-02-24 2020-08-28 中国科学院上海微系统与信息技术研究所 Three-dimensional memory reading circuit and word line and bit line voltage configuration method thereof

Patent Citations (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20050018519A1 (en) * 2003-07-24 2005-01-27 Renesas Technology Corp. Semiconductor memory device capable of reducing power consumption during reading and standby
US20130272078A1 (en) * 2012-04-16 2013-10-17 Sony Corporation Storage controlling apparatus, memory system, information processing system and storage controlling method
WO2017018008A1 (en) * 2015-07-24 2017-02-02 ソニー株式会社 Encoding device, memory controller, communication system, and encoding method
US20180143871A1 (en) * 2015-07-24 2018-05-24 Sony Corporation Encoding device, memory controller, communication system, and encoding method

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2019126746A1 *

Also Published As

Publication number Publication date
US20200211641A1 (en) 2020-07-02
CN111480200A (en) 2020-07-31
KR102461132B1 (en) 2022-11-01
KR20220030302A (en) 2022-03-10
JP2021508107A (en) 2021-02-25
SG11202005283YA (en) 2020-07-29
US11282571B2 (en) 2022-03-22
US10937491B2 (en) 2021-03-02
WO2019126746A1 (en) 2019-06-27
US20200335159A1 (en) 2020-10-22
US20210257022A1 (en) 2021-08-19
EP3729429A1 (en) 2020-10-28
US20190198096A1 (en) 2019-06-27
US10566052B2 (en) 2020-02-18
US10741243B2 (en) 2020-08-11
CN115527580A (en) 2022-12-27
KR102367907B1 (en) 2022-02-25
CN111480200B (en) 2022-08-23
JP6972353B2 (en) 2021-11-24
KR20200089761A (en) 2020-07-27

Similar Documents

Publication Publication Date Title
EP3729437A4 (en) Auto-referenced memory cell read techniques
EP3729429A4 (en) Auto-referenced memory cell read techniques
EP3507804A4 (en) Ferroelectric memory cells
EP3718110A4 (en) Operations on memory cells
EP3443461A4 (en) Memory device with direct read access
EP3507831A4 (en) Memory cells and memory arrays
EP3662478A4 (en) Memory devices with read level calibration
EP3635782A4 (en) Memory arrays
EP3635783A4 (en) Memory arrays
EP3259757A4 (en) Memory cells
EP3507830A4 (en) Memory cells and memory arrays
EP3507832A4 (en) Memory cells and memory arrays
EP3732685A4 (en) Polarity-conditioned memory cell write operations
EP3430626A4 (en) Ferroelectric memory cell sensing
EP3117435A4 (en) Mitigating read disturb in a cross-point memory
EP3507829A4 (en) Memory cells and memory arrays
EP3516659A4 (en) Adaptive memory cell write conditions
EP3304554A4 (en) Ferroelectric based memory cell with non-volatile retention
EP3440673A4 (en) Supply-switched dual cell memory bitcell
EP3662379A4 (en) Memory addressing
EP3427264A4 (en) Memory cell sensing with storage component isolation
EP3427265A4 (en) Parallel access techniques within memory sections through section independence
EP3146524A4 (en) Read cache memory
EP3676835A4 (en) Memory circuitry
EP3459079A4 (en) Improved flash memory cell associated decoders

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20200529

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
A4 Supplementary search report drawn up and despatched

Effective date: 20210628

RIC1 Information provided on ipc code assigned before grant

Ipc: G11B 20/10 20060101AFI20210622BHEP

Ipc: G11C 13/02 20060101ALI20210622BHEP

Ipc: G11C 7/04 20060101ALI20210622BHEP

Ipc: G11C 7/10 20060101ALI20210622BHEP

Ipc: G11C 13/00 20060101ALI20210622BHEP

Ipc: G11C 11/56 20060101ALI20210622BHEP

Ipc: G11C 16/10 20060101ALI20210622BHEP

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: EXAMINATION IS IN PROGRESS

17Q First examination report despatched

Effective date: 20230421