AU2002331580A1 - Method for reading a structural phase-change memory - Google Patents

Method for reading a structural phase-change memory

Info

Publication number
AU2002331580A1
AU2002331580A1 AU2002331580A AU2002331580A AU2002331580A1 AU 2002331580 A1 AU2002331580 A1 AU 2002331580A1 AU 2002331580 A AU2002331580 A AU 2002331580A AU 2002331580 A AU2002331580 A AU 2002331580A AU 2002331580 A1 AU2002331580 A1 AU 2002331580A1
Authority
AU
Australia
Prior art keywords
reading
change memory
structural phase
structural
phase
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Abandoned
Application number
AU2002331580A
Inventor
Tyler A. Lowrey
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Intel Corp
Original Assignee
Intel Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Intel Corp filed Critical Intel Corp
Publication of AU2002331580A1 publication Critical patent/AU2002331580A1/en
Abandoned legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/02—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using elements whose operation depends upon chemical change
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/0069—Writing or programming circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0004—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements comprising amorphous/crystalline phase transition cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C13/00—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00
    • G11C13/0002—Digital stores characterised by the use of storage elements not covered by groups G11C11/00, G11C23/00, or G11C25/00 using resistive RAM [RRAM] elements
    • G11C13/0021—Auxiliary circuits
    • G11C13/004—Reading or sensing circuits or methods
    • G11C2013/0054—Read is performed on a reference element, e.g. cell, and the reference sensed value is used to compare the sensed value of the selected cell
AU2002331580A 2002-08-14 2002-08-14 Method for reading a structural phase-change memory Abandoned AU2002331580A1 (en)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
PCT/US2002/025932 WO2004017328A1 (en) 2002-08-14 2002-08-14 Method for reading a structural phase-change memory

Publications (1)

Publication Number Publication Date
AU2002331580A1 true AU2002331580A1 (en) 2004-03-03

Family

ID=31886104

Family Applications (1)

Application Number Title Priority Date Filing Date
AU2002331580A Abandoned AU2002331580A1 (en) 2002-08-14 2002-08-14 Method for reading a structural phase-change memory

Country Status (5)

Country Link
KR (1) KR100634330B1 (en)
CN (1) CN1628357B (en)
AU (1) AU2002331580A1 (en)
DE (1) DE10297767T5 (en)
WO (1) WO2004017328A1 (en)

Families Citing this family (23)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6944041B1 (en) * 2004-03-26 2005-09-13 Bae Systems Information And Electronic Systems Integration, Inc. Circuit for accessing a chalcogenide memory array
DE102004040753A1 (en) * 2004-08-23 2006-03-09 Infineon Technologies Ag Circuit arrangement for information storage in cells of the CBRAM-type, has write transistor and constant current source arranged in symmetrical current circuit
DE102004041330B3 (en) 2004-08-26 2006-03-16 Infineon Technologies Ag Memory circuit with a memory element having memory element resistance
DE102006016514A1 (en) * 2006-04-07 2007-10-18 Infineon Technologies Ag Logic circuit e.g. dynamic programmable logic array, has NMOS-base transistor and two transistors, which are parallely arranged, where parameter of current flowing through NMOS-base transistor is determined by resistance values
JP5396011B2 (en) * 2007-06-19 2014-01-22 ピーエスフォー ルクスコ エスエイアールエル Phase change memory device
US8362821B2 (en) * 2007-11-22 2013-01-29 Nxp B.V. Charge carrier stream generating electronic device and method
US7729163B2 (en) * 2008-03-26 2010-06-01 Micron Technology, Inc. Phase change memory
US8027192B2 (en) 2008-08-20 2011-09-27 Samsung Electronics Co., Ltd. Resistive memory devices using assymetrical bitline charging and discharging
KR101416834B1 (en) * 2008-08-20 2014-07-08 삼성전자주식회사 Nonvolatile memory device using variable resistive element
WO2011055669A1 (en) * 2009-11-06 2011-05-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8649212B2 (en) * 2010-09-24 2014-02-11 Intel Corporation Method, apparatus and system to determine access information for a phase change memory
JP5598338B2 (en) * 2011-01-13 2014-10-01 ソニー株式会社 Storage device and operation method thereof
WO2012120401A1 (en) * 2011-03-10 2012-09-13 International Business Machines Corporation Cell-state determination in phase-change memory
DE102012102326A1 (en) * 2012-03-20 2013-09-26 Helmholtz-Zentrum Dresden - Rossendorf E.V. Integrated non-volatile memory device e.g. analog memory has surface contact terminal zone formed in non-volatile space charge regions, while counter-contact connector is formed in area of ferroelectric layer
US9520445B2 (en) 2011-07-12 2016-12-13 Helmholtz-Zentrum Dresden-Rossendorf E. V. Integrated non-volatile memory elements, design and use
DE112012005424T5 (en) * 2011-12-21 2014-09-18 International Business Machines Corporation Read / write operations in semiconductor memory devices
US10134470B2 (en) 2015-11-04 2018-11-20 Micron Technology, Inc. Apparatuses and methods including memory and operation of same
US9530513B1 (en) * 2015-11-25 2016-12-27 Intel Corporation Methods and apparatus to read memory cells based on clock pulse counts
US10446226B2 (en) 2016-08-08 2019-10-15 Micron Technology, Inc. Apparatuses including multi-level memory cells and methods of operation of same
US10157670B2 (en) * 2016-10-28 2018-12-18 Micron Technology, Inc. Apparatuses including memory cells and methods of operation of same
US10566052B2 (en) 2017-12-22 2020-02-18 Micron Technology, Inc. Auto-referenced memory cell read techniques
US10431301B2 (en) 2017-12-22 2019-10-01 Micron Technology, Inc. Auto-referenced memory cell read techniques
WO2024060059A1 (en) * 2022-09-21 2024-03-28 Yangtze Advanced Memory Industrial Innovation Center Co., Ltd. Memory device and controlling method thereof

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
CN1206195A (en) * 1997-06-18 1999-01-27 日本电气株式会社 Semiconductor memory device with input/output masking function without destruction of data bit
US6314014B1 (en) * 1999-12-16 2001-11-06 Ovonyx, Inc. Programmable resistance memory arrays with reference cells

Also Published As

Publication number Publication date
WO2004017328A1 (en) 2004-02-26
KR20050018639A (en) 2005-02-23
WO2004017328A8 (en) 2004-08-26
CN1628357A (en) 2005-06-15
DE10297767T5 (en) 2005-08-04
KR100634330B1 (en) 2006-10-16
CN1628357B (en) 2010-05-05

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Legal Events

Date Code Title Description
MK6 Application lapsed section 142(2)(f)/reg. 8.3(3) - pct applic. not entering national phase