CN1206195A - Semiconductor memory device with input/output masking function without destruction of data bit - Google Patents
Semiconductor memory device with input/output masking function without destruction of data bit Download PDFInfo
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- CN1206195A CN1206195A CN 98102515 CN98102515A CN1206195A CN 1206195 A CN1206195 A CN 1206195A CN 98102515 CN98102515 CN 98102515 CN 98102515 A CN98102515 A CN 98102515A CN 1206195 A CN1206195 A CN 1206195A
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Abstract
A semiconductor synchronous dynamic random access memory device has an input/output masking function in a block write mode, plural bit line pairs are concurrently connected to a pair of data lines (IOBT/IOBN) charged to a power voltage level by a precharge circuit (15) in the input/output masking function so as to prevent memory cells from current flowing out from differential amplifiers, and the precharge circuit has not only p-channel type charging transistors but also n-channel enhancement type charging transistors; even if the bit line Paris are connected to the pair of data lines, the n-channel enhancement type charging transistors supplement the current through the data line pair to the bit line Pairs, and prevent potential differences on the bit line pairs from undesirable destruction.
Description
The present invention relates to a kind of semiconductor storage unit, particularly relate to a kind of semiconductor synchronous memory device with I/O mask function.
Fig. 1 in the accompanying drawing shows a kind of typical semiconductor synchronous dynamic random access memory devices.Formerly the semiconductor synchronous dynamic random access memory devices comprises 3, one write control circuits 4 of 2, one selector switchs in 1, one sensor amplifier unit of a memory cell array and a pre-charge circuit 5 in the technology.Memory cell array 1 comprises a plurality of storage unit 1a ..., 1n, and each storage unit 1a to 1n is composed in series by a memory capacitance 1c and a n channel enhancement field effect transistor 1d.The selected bit line that is connected to of storage unit 1a to 1n arrives BLn/BLnB to BL1/BL1B.The selected grid that is connected to n channel enhancement field effect transistor 1d of word line WL, the relevant n channel enhancement field effect transistor 1d conducting of drive signal φ WL order that acts on the selecteed word line.
Formerly the semiconductor synchronous dynamic random access memory devices in the technology has a kind of WriteMode, and in the piece WriteMode, one writes data bit and is provided for bit line to BL1/BL1B to BLn/BLnB from data bus IOBT/IOBN.This piece write operation needs I/O mask function as described below.
Fig. 2 shows the I/O mask function under the piece WriteMode.In Fig. 2, " V
Dd" and " GND " represent respectively supply voltage and ground, " BLn/BLnB ", " 2n " and " Qnn1/Qnn2 " suppose to represent respectively a plurality of bit lines right, a plurality of differential amplifiers and a plurality of n channel enhancement field effect transistor are right.
At T1 in the time, activation signal φ SP/ φ SN, bit line all equals V to BL1/BL1B to BLn/BLnB
Dd/ 2, and data bus IOBT/IOBN is charged to V
DdTiming signal φ W, data-signal φ D and drive signal φ WL are maintained at ground level.
When the execution data were read from T1 to T2, drive signal φ WL changed into V
Dd, cause the n channel enhancement field effect transistor 1d conducting among the related memory cell 1a to 1n.Then, relevant memory capacitance 1c just with bit line BL1 and bit line BLn conducting, then between bit line is to BL1/BL1B and bit line to just having occurred electric potential difference between the BLn/BLnB.
Activation signal φ SP and activation signal φ SN are respectively from V
Dd/ 2 become V
DdAnd GND, activated differential amplifier 2n and differential amplifier 2n.Differential amplifier 2a and differential amplifier 2n improved bit line to the electric potential difference between the BL1/BL1B and bit line to the electric potential difference between the BLN/BLnB.
The differential T3 of being amplified in finishes.Current potential on bit line BL1 and the bit line BL1B reaches GND and V respectively
DdOn the other hand, bit line BLn and bit line BLnB become V respectively
DdAnd GND.Thereby, bit line to the electric potential difference between the BL1/BL1B and bit line to the potential difference of opposite polarity between the BLn/BLnB.
When data were read execution to 74, all selection signal psi 1 to φ n became V
DdIn order to obtain the I/O mask function, timing signal φ W, data-signal φ D and precharge control signal φ D remain on GND, and p channel enhancement field effect transistor Qp3/Qp4 makes data bus IOBT/IOBN remain on V
DdData bus IOBT/IOBN is charged to V
Dd, this electric current that has prevented storage unit 1a to 1n as described below flows out from differential amplifier 2a to 2n.The electromotive force of bit line BL1 and bit line BLnB is GND, and this causes n channel enhancement field effect transistor Qn11 and n channel enhancement field effect transistor Qnn2 conducting.
Although p channel enhancement field effect transistor Qp4 provide V to data bus IOBN
Dd, but the n channel enhancement field effect transistor Qn2 of a plurality of differential amplifier 2n is pulled down to GND with data bus IOBN.Promptly, n channel enhancement field effect transistor Qn12 conducting, although the electric current of supplying with by the p channel enhancement field effect transistor Qp2 among p channel enhancement field effect transistor Qp4 and the differential amplifier 2a is arranged, the n channel enhancement field effect transistor Qn2 on the differential amplifier 2n has drawn the level on the bit line BL1B to get off.On the other hand, although during the potential decay of the p channel enhancement field effect transistor Qp1 of the n channel enhancement field effect transistor Qn1 of differential amplifier 2a and differential amplifier 2n on data bus IOBT, IOBT provides electric current to data bus, but p channel enhancement field effect transistor Qp3 will draw on the current potential of bit line BL1.The result is, bit line BL1 rises to a positive potential, and this current potential is lower than V
Dd, be V
DdDeduct the threshold value V of n channel enhancement field effect transistor Qn11
Thn
Data bus BLn remains on V
DdP channel enhancement field effect transistor Qp4 by data bus IOBN and n channel enhancement field effect transistor Qnn2 to bit line BLnB supplying electric current.Bit line BLnB rises to a certain specific potential, and this current potential is lower than V
Dd, be V
DdDeduct the threshold value V of n channel enhancement field effect transistor Qnn2
ThnThereby electric current flows between pre-charge circuit 5 and differential amplifier 2a to 2n, and storage unit 1a to 1n has avoided going up the interference that exists between the sense data position from data bus IOBT/IOBN.
Read when carrying out to T5 when data, select signal psi 1 to φ n to change to GND, n channel enhancement field effect transistor Qn11/Qn12 to Qnn1/Qnn2 ends.P channel enhancement field effect transistor Qp3/Qp4 charges to V with data bus IOBT/IOBN
DdBit line BL1/BL1B and bit line return to initial electric potential difference to BLn/BLnB.
When the data read operation was carried out to T6, drive signal φ WL became low level, and n channel enhancement field effect transistor 1d ends.Therefore, although all n channel enhancement field effect transistor Qn11/Qn12 to Qnn1/Qnn2 are switched on, pre-charge circuit 5 is pulled to V with data bus IOBT/IOBN
Dd, and pre-charge circuit 5 and sensor amplifier 2 have stoped the unnecessary destruction of in the I/O mask function storage unit 1a to 1n being caused.
However, formerly still there is a problem in the semiconductor synchronous dynamic random access memory devices in the technology, and promptly the potential drop on the data bus has destroyed a data bit that will be resumed in a storage unit.Specifically, if as mentioned above, bit line is opposite to the logic level of the data bit of BLn/BLnB with bit line to the logic level of the data bit on the BL1/BL1B, and then data bus IOBN discharges to ground wire 2c by n channel enhancement field effect transistor Qnn2 and a plurality of n channel enhancement field effect transistor Qn2.When data bus IOBN reaches a certain particular level, promptly be lower than forward supply voltage V
DdBe V
DdWhen deducting the threshold value of n channel enhancement field effect transistor Qn12, then n channel enhancement field effect transistor Qn12 conducting causes bit line BL1B from forward high voltage V
DdDescend.The result is, the electric potential difference between bit line BL1 and the bit line BL1B reduces, and falls the data bit on the BL1/BL1B is destroyed at bit line.
Another problem is the pre-charge level instability.This is because at n channel enhancement field effect transistor Qn11, n channel enhancement field effect transistor Qnn1, n channel enhancement field effect transistor Qn1/Qn2 in the single differential amplifier 2a, p channel enhancement field effect transistor Qp1/Qp2 in the single differential amplifier 2a, n channel enhancement field effect transistor Qn1/Qn2 in a plurality of differential amplifier 2n, between the p channel enhancement field effect transistor Qp1/Qp2 in a plurality of differential amplifier 2n and since the difference of technological parameter cause the current drives capacity difference caused.
Thereby a free-revving engine of the present invention is to provide a kind of semiconductor synchronous memory device, and it can access I/O markers control function highly reliably, and can not destroy data.
Another free-revving engine of the present invention provides a kind of semiconductor synchronous memories, and it can produce stable pre-charge level on data bus, and does not have the fluctuating change of technological parameter.
For reaching these purposes, the present invention proposes data bus is pulled to a certain definite level, it is lower than supply voltage, is the such technical scheme of threshold value that supply voltage deducts second charging transistor.
According to one aspect of the present invention, a kind of semiconductor storage unit spare is provided, it comprises, a plurality of storage unit are used for stored data bit; A plurality of bit lines are right, and they are connected on a plurality of storage unit selectively, are used for from the electric potential difference signal of a plurality of storage unit conduction representative datas position; A plurality of differential amplifiers are connected between one first power voltage line and the second source pressure-wire different with the first power voltage line current potential, are used for improving the amplitude of a plurality of bit lines to last electric potential difference after the activation; A data line is right; A selector switch, it be connected a plurality of bit lines to and data line between, be used at mask function according to selecting signal, with a plurality of bit lines to being connected to data line simultaneously to last; With a pre-charge circuit, it is connected to data line to last, comprise one first charging transistor, this transistor is connected between the right data line of one the 3rd power voltage line and data line, form a kind of first conductive channel of conduction type according to precharge control signal, be used for data line is charged to the supply voltage of the 3rd power voltage line, with one second charging transistor, this transistor is connected between the 3rd power voltage line and the data line, complementary signal according to a precharge control signal, form second conductive channel of films of opposite conductivity, data line is charged to a certain level, this level is lower than the 3rd supply voltage, is the threshold value that the 3rd supply voltage deducts second charging transistor.
In conjunction with following the description of the drawings, the characteristics and the advantage of semiconductor synchronous memory device among the present invention will be more readily understood.
Fig. 1 is circuit theory diagrams, shows the circuit of technology semiconductor synchronous RAM spare formerly;
Fig. 2 is a sequential chart, shows the I/O mask function of technology semiconductor synchronous dynamic random access memory devices under the piece WriteMode formerly;
Fig. 3 is circuit theory diagrams, shows the circuit according to semiconductor synchronous dynamic random access memory devices of the present invention; With
Fig. 4 is a sequential chart, shows the I/O sequential function of this semiconductor synchronous RAM spare under the piece WriteMode.
With reference to accompanying drawing 3, realize that a semiconductor synchronous RAM spare of the present invention mainly comprises: 13, one write control circuits 14 of 12, one column selectors in 11, one sensor amplifier unit of a memory cell array and a pre-charge circuit 15.Memory cell array 11, sensor amplifier 12, column selector 13 and write control circuit 14 on circuit arrangement respectively with memory cell array 1, sensor amplifier unit 2, selector switch 3 and write control circuit 4 are similar.Therefore, do not specify if having, circuit component still be marked by with technology semiconductor synchronous RAM formerly in the identical sign of element.Bit line to data bus also be still adopt with technology semiconductor synchronous RAM formerly in identical sign.
In this example, n channel enhancement field effect transistor Qn22 equates on the current drives capacity with the n channel enhancement field effect transistor Qn2 of a plurality of differential amplifier 2n, and p channel enhancement field effect transistor Q φ 22 equates on the current drives capacity with the n channel enhancement field effect transistor Qn2 of single differential amplifier 2a.Same, n channel enhancement field effect transistor Qn21 equates on the current drives capacity with the n channel enhancement field effect transistor Qn1 of a plurality of differential amplifier 2n, and p channel enhancement field effect transistor Qp21 equates on the current drives flow with the n channel enhancement field effect transistor Qn1 of single differential amplifier 2a.
This semiconductor synchronous RAM is to realize the I/O mask function as follows.Fig. 4 shows the I/O mask function in the piece WriteMode.In Fig. 4, " V
Dd" and " GND " still represent power level and ground level respectively, " BLn/BLnB ", " 2n " and " Qnn1/Qnn2 " represents a plurality of bit lines right respectively, a plurality of differential amplifiers and a plurality of n channel enhancement field effect transistor are right.
Activation signal φ SP/ φ SN, bit line all equals V to BL1/BL1B to BLn/BLnB at T1 in the time
Dd/ 2, the precharge control signal φ P of ground level makes p channel enhancement field effect transistor Qp21/Qp22 that data bus IOBT/IOBN is charged to V
DdTiming signal φ W, data-signal φ D and drive signal φ WL remain on ground level.
When the data read operation when T1 carries out T2, drive signal φ WL changes into V
Dd, make the n channel enhancement field effect transistor 1d conducting of related memory cell 1a in the 1n.Associated storage electric capacity 1c is connected on bit line BL1 and the BLn, and bit line is to electric potential difference having occurred on BL1/BL1B and the bit line position BLn/BLnB.
Activation signal φ SP and activation signal φ SN are respectively from V
Dd/ 2 become V
DdAnd GND, activate differential amplifier 2a and differential amplifier 2n.Differential amplifier 2a and differential amplifier 2n improved bit line to the electric potential difference between the BL1/BL1B and bit line to the electric potential difference between the BLn/BLnB.
Differential amplifier is finished at T3.Bit line BL1 and bit line BL1B become GND and V respectively
DdOn the other hand, bit line BLn and bit line BLnB become V respectively
DdAnd GND.Therefore, opposite with bit line at bit line to the electric potential difference direction on the BLn/BLnB to the electric potential difference on the BL1/BL1B.
In order to realize the I/O mask function, timing signal φ W and precharge control signal φ P are maintained at ground level.Draw data bus IOBT/IOBN to forward supply voltage V on the p channel enhancement field effect transistor Qp21/Qp22
Dd, and stoped the electric current among the storage unit 1a to 1n from differential amplifier 2a to 2n, to flow out.
When the data read operation was carried out to T4, all selection signal psi 1 to φ n became V
DdGround level on bit line BL1 and the bit line BLnB makes n channel enhancement field effect transistor Qn11 and Qnn2 conducting.Although p channel enhancement field effect transistor Qp4 supplies with V to data bus IOBN
Dd, but the n channel enhancement field effect transistor Qn2 of a plurality of differential amplifier 2n still attempts data bus IOBN is pulled down to GND.Yet the n channel enhancement field effect transistor Qn2 of a plurality of differential amplifier 2n equates on the current drives capacity with n channel enhancement field effect transistor Qn22.For this reason, data bus IOBN is adjusted to a certain particular level, and this level is less than forward supply voltage V
Dd, be V
DdDeduct the threshold value of n channel enhancement field effect transistor Qnn2.
Current potential (V on data bus IOBN
Dd-V
Thn) cause n channel enhancement field effect transistor Qn2 conducting.Yet the p channel enhancement field effect transistor Qp2 among the single differential amplifier 2a is to bit line BL1B supplying electric current, and bit line BL1B is charged between V
DdAnd specific potential (V
Dd-V
Thn) between a current potential.
Select signal psi 1 to make n channel enhancement field effect transistor Qn11 conducting.Although the n channel enhancement field effect transistor Qn1 of single differential amplifier 2a has discharged electric current, but n channel enhancement field effect transistor Qn21, draw bit line BL1 to forward supply voltage V on the p channel enhancement field effect transistor Qp1 among p channel enhancement field effect transistor Qp21 and a plurality of differential amplifier 2n
DdWhen the current potential on bit line BL1 arrives particular level (V
Dd-V
Thn) time, n channel enhancement field effect transistor Qn11 ends, and then bit line BL1 remains on this particular level (V
Dd-V
Thn).
Data bus BLn remains on V
Dd, because there is the p channel enhancement field effect transistor Qp1 among the differential amplifier 2n to supply with its electric current.Forward supply voltage V on bit line BLn
DdMake n channel enhancement field effect transistor Qnn1 end.
The n channel enhancement field effect transistor Qn2 of a plurality of differential amplifier 2n and n channel enhancement field effect transistor Qn22 average out, and p channel enhancement field effect transistor Qp22 charges to particular level (V with bit line BLnB
Dd-V
Thn).Bit line BLnB is at (V
Dd-V
Thn) under balance.
Read when proceeding to T5 when data, select signal psi 1 to φ n to become GND, n channel enhancement field effect transistor Qn11/Qn12～Qnn1/Qnn21d ends.P channel enhancement field effect transistor Qp21/Qp22 is charged to V with data bus IOBT/IOBN
DdBit line BL1/BL1B and bit line revert to initial potential difference (PD) to BLn/BLnB.Like this, little potential difference (PD) is only arranged at bit line on to BL1/BL1B～BLn/BLnB.
Read when proceeding to T6 when data, drive signal φ WL becomes low level, and n channel enhancement field effect transistor 1d ends.Like this, both made all conductings of n channel enhancement field effect transistor Qn11/Qn12～Qnn1/Qnn2, pre-charge circuit 5 will be moved V to by data bus IOBT/IOBN
Dd, differential amplifier 2a～2n has increased little potential difference (PD).Consequently original data bit is recovered in storage unit 1a～1n, so the I/O mask function can not destroy the data bit in the storage unit.
By further description, will sharpen understanding, pre-charge circuit 15 not only contains p channel enhancement field effect transistor Qp21/Qp22, also contain n channel enhancement field effect transistor Qn21/Qn22, n channel enhancement field effect transistor Qn21/Qn22 has stoped in the I/O function, and data bus IOBN/IOBT is at specific potential (V
Dd-V
Thn) under current potential postpone.This restriction does not allow data line to bit line is anti-phase to last electric potential difference, thereby the data bit that is stored in the storage unit can be not destroyed.
Although only illustrate and described a special embodiment of the present invention,, without departing from the spirit and scope of the present invention, the present invention is carried out various modifications and imitation may be accomplished to those of ordinary skill in the art.
The current drives capacity of n channel enhancement field effect transistor Qn21/Qn22 can be greater than the current drives capacity of the n channel enhancement field effect transistor Qn2 among a plurality of difference amplifier 2n.
Claims (6)
1. semiconductor storage unit comprises:
A plurality of storage unit (1a to 1n) are used for stored data bit;
A plurality of bit lines are connected in described a plurality of storage unit selectively to (BL1/BL1B to BLn/BLnB), are used for from the electric potential difference signal of described a plurality of storage unit conduction representative datas position;
A plurality of differential amplifiers (2a to 2n), be connected between one first power voltage line (2b) and the second source pressure-wire (2c) different, be used for improving the amplitude of described a plurality of bit line after the activation last described electric potential difference with the described first power voltage line current potential;
A data line is to (IOBT/IOBN);
A selector switch (13), it be connected described a plurality of bit line to and described data line between, be used at mask function according to selecting signal (φ 1 to φ n), with described a plurality of bit lines to being connected to described data line simultaneously to last; With
A pre-charge circuit (15), it is connected to described data line to last, be used for to data line to the charging, it is characterized in that in described pre-charge circuit, comprising:
First charging transistor (Qp21/Qp22), it is connected between the right data line of one the 3rd power voltage line and described data line, form first conductive channel of a kind of conduction type (P) according to precharge control signal (φ P), be used for described data line is charged to the supply voltage of described the 3rd power voltage line; With
Second charging transistor (Qn21/Qn22), it is connected between described the 3rd power voltage line and the described data line, complementary signal (φ PB) according to described precharging signal, form second conductive channel of films of opposite conductivity (N), described data line is charged to a particular level (Vdd-Vthn), this level is lower than described the 3rd supply voltage, is the threshold value that described the 3rd supply voltage deducts described second charging transistor.
2. semiconductor storage unit as claimed in claim 1, it is characterized in that: each described second charging transistor (Qn21/Qn22) is compared with each described first charging transistor (Qp21/Qp22), bigger on the current drives capacity, thereby in described mask function, described data line is decayed to described particular level selectively.
3. semiconductor storage unit as claimed in claim 1 is characterized in that: described a plurality of differential amplifiers (2a to 2n) have, first discharge transistor (Qn1), and they are connected respectively to first bit line (BL1 to BLn) of described a plurality of bit line pairs; With second discharge transistor (Qn2), they are connected to second bit line (BL1B to BLnB) of described a plurality of bit line pairs respectively, and each described second discharge transistor is equal to or greater than described first discharge transistor of being chosen on the current drives capacity, second discharge transistor of perhaps being chosen of discharge simultaneously on first bit line that links to each other or continuous second bit line.
4. semiconductor storage unit as claimed in claim 1, it is characterized in that: described first charging transistor (Qp21/Qp22) is a p channel enhancement field effect transistor, and described second charging transistor (Qn21/Qn22) is a n channel enhancement field effect transistor.
5. semiconductor storage unit as claimed in claim 1 is characterized in that: each described storage unit is composed in series by a switching transistor (1d) and a memory capacitance (1c).
6. semiconductor storage unit as claimed in claim 1, it is characterized in that: also comprise a selector switch (13), it be connected described a plurality of bit line to and described data line between, according to selecting signal (φ 1 to φ n), in a standard read operation, selectively with described a plurality of bit lines to being connected to described data line to last, and described selection signal allow described selector switch in mask function simultaneously with described a plurality of bit lines to be connected to described data line on.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| CN 98102515 CN1206195A (en) | 1997-06-18 | 1998-06-17 | Semiconductor memory device with input/output masking function without destruction of data bit |
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP160707/97 | 1997-06-18 | ||
| CN 98102515 CN1206195A (en) | 1997-06-18 | 1998-06-17 | Semiconductor memory device with input/output masking function without destruction of data bit |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CN1206195A true CN1206195A (en) | 1999-01-27 |
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ID=5217386
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CN 98102515 Pending CN1206195A (en) | 1997-06-18 | 1998-06-17 | Semiconductor memory device with input/output masking function without destruction of data bit |
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|---|---|
| CN (1) | CN1206195A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6842388B2 (en) | 2001-11-20 | 2005-01-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device with bit line precharge voltage generating circuit |
| CN100433189C (en) * | 2004-08-09 | 2008-11-12 | 凌阳科技股份有限公司 | Data exchange circuit and method for synchronous DRAM |
| CN1628357B (en) * | 2002-08-14 | 2010-05-05 | 英特尔公司 | Method for reading structural phase-Change memory |
-
1998
- 1998-06-17 CN CN 98102515 patent/CN1206195A/en active Pending
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US6842388B2 (en) | 2001-11-20 | 2005-01-11 | Matsushita Electric Industrial Co., Ltd. | Semiconductor memory device with bit line precharge voltage generating circuit |
| CN1628357B (en) * | 2002-08-14 | 2010-05-05 | 英特尔公司 | Method for reading structural phase-Change memory |
| CN100433189C (en) * | 2004-08-09 | 2008-11-12 | 凌阳科技股份有限公司 | Data exchange circuit and method for synchronous DRAM |
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