CN103996409A - Memory apparatus and method for improving memory reading rate - Google Patents
Memory apparatus and method for improving memory reading rate Download PDFInfo
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- CN103996409A CN103996409A CN201310051220.2A CN201310051220A CN103996409A CN 103996409 A CN103996409 A CN 103996409A CN 201310051220 A CN201310051220 A CN 201310051220A CN 103996409 A CN103996409 A CN 103996409A
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Abstract
The invention discloses a memory apparatus and a method for improving memory reading rate. The memory apparatus comprises a memory cell array, a plurality of sense amplifiers in coupling connection with the memory cell array, a plurality of output data lines for receiving output signals of corresponding sense amplifiers in a plurality of the sense amplifiers, and a plurality of pre-charging circuits for applying pre-charging voltage on the output data lines. The apparatus also comprises a controller, and the controller provides a control signal for the sense amplifiers and the pre-charging circuits, and the pre-charging circuits pre-charge the output data lines before the sense amplifiers is driven to output a data signal to the output data lines. A plurality of the sense amplifiers comprise a plurality of rows of the sense amplifiers, and each row of the sense amplifiers comprise one sense amplifier which possesses an output driver driving each of the output data lines. The memory apparatus comprises a data output multifunction multiplexer which possesses the input terminals coupled with the output data lines, and the pre-charging circuits are coupled with the output data lines between the output terminals of the sense amplifiers and the data output multifunction multiplexer.
Description
Technical field
The present invention is about integrated circuit memory devices, and is set up for the circuit of output data is provided about this type of memory device, especially a kind of for improving storage arrangement and the method for storer reading rate.
Background technology
It is more intensive and faster that integrated circuit memory devices becomes.Sensing amplifier group is used to from memory array reading out data.The output circuit that useful mass data line is set up from a pile sensing amplifier transmission output data to memory device, this storage arrangement can comprise a plurality of many merits multiplexers and output buffer.In order to save layout area, data line can be placed closely together.Yet bad reaction is that the capacitive couplings effect between data line makes the decline of signal fringe time, and due to the delay between output circuit that exports to from sensing amplifier, makes reading rate slack-off.
By addressing these problems, the reading rate improving on integrated circuit is expected.
Summary of the invention
In view of this, fundamental purpose of the present invention is to provide a kind of for improving storage arrangement and the method for storer reading rate.
This storage arrangement comprises a plurality of sensing amplifiers that couple with memory cell array, and a plurality of output data lines that receive a plurality of outputs of a plurality of corresponding sense amplifiers in the plurality of sensing amplifier.This storage arrangement comprises a plurality of pre-charge circuits, and it is configured to apply pre-charge voltage in output online data.Pre-charge circuit at sensing amplifier driver output data-signal to this output data line of first precharge before output data line.Storage arrangement comprises controller, it provides this sensing amplifier controlling signal in the plurality of sensing amplifier, and to this pre-charge circuit in the plurality of pre-charge circuit, comprise make this pre-charge circuit at sensing amplifier driver output data-signal to this output data line of first precharge before output data line.A plurality of rows that the plurality of sensing amplifier comprises sensing amplifier, and each package is containing a sensing amplifier, and it has an output, and this output drives each output data line in the plurality of output data line.Storage arrangement more comprises data and exports many merits multiplexer, and it has the input that is coupled to this output data line, and output and data that this pre-charge circuit is coupled to sensing amplifier are exported the output data line between many merits multiplexer.
For coming the method for sense data to be also provided with this storage arrangement.
Consult graphic, following detailed description and claim scope can be seen other aspects of the present invention and advantage.
Accompanying drawing explanation
Fig. 1 is the simplification calcspar of storage arrangement, and it is illustrated for carrying from selected storer row the output data line that sense data to data are exported many merits multiplexer.
Fig. 2 is the schematic diagram of illustrating a circuit that comprises output data line, and this output data line receives the output of sensing amplifier and between it, has stray capacitance (prior art).
Fig. 3 is a sequential chart, and it is illustrated in the switching time of the output online data of the circuit of describing in Fig. 2 (prior art).
Fig. 4 is the schematic diagram of illustrating the embodiment of a pre-charge circuit, and this pre-charge circuit is that the output online data being configured in storage arrangement according to the present invention applies pre-charge voltage.
Fig. 5 is the schematic diagram of illustrating an example of output data line, and this output data line is to drive and be coupled to the pre-charge circuit in the storage arrangement with control signal by sensing amplifier.
Fig. 6 and Fig. 7 are the sequential charts of the embodiment of the pre-charge circuit described for Fig. 4 and Fig. 5.
Fig. 8 is the schematic diagram of illustrating the second embodiment of pre-charge circuit, and it is that the output online data being configured in storage arrangement according to the present invention applies pre-charge voltage.
Fig. 9 and Figure 10 are the sequential charts of the embodiment of the pre-charge circuit described for Fig. 8.
Figure 11 is the simplification calcspar according to the storage arrangement of an embodiment.
[symbol description]
140,1140 column decoders
150,1150 row's code translators
170,1170 line decoders
180,221-227,421-427,821-827 sensing amplifier
190,451-457,851-856,1190 pre-charge circuits
193,293,493,893,1193 data are exported many merits multiplexer
195,295,495,895,1195 data lines
197,297,497,897,1197 output drivers
251-256,441-446,841-846 stray capacitance
310,320,610,620,630,640 conversions
541,551 sensing circuits
545,555 sense datas
547,557 output buffer circuits
560 branch circuits
561 non-grid
563 Sheffer stroke gates
650,750,950,1050 pre-charge voltages
1100 integrated circuit
1105 Data In-Lines
1110 controllers
1111 sensing signals
1112 output signals
1113 precharging signals
1120 bias voltage arrangement supply voltages
1145 word lines
1130,1155 buses
1160 memory arrays
1165 bit lines
1175 data buss
1180 sensing amplifiers and data input structure
1185 output data lines
Embodiment
The detailed description of the embodiment of the present invention provides with reference to Fig. 1-Figure 11.
Fig. 1 is the simplification calcspar of illustrating storage arrangement, and this storage arrangement comprises for carrying from selected storer row the output data line that sense data to data are exported many merits multiplexer.A plurality of output data lines of the output that this storage arrangement comprises a plurality of sensing amplifiers of coupling with memory cell array, receive corresponding sense amplifier in the plurality of sensing amplifier and be configured to apply pre-charge voltage at a plurality of pre-charge circuits of this output online data.The plurality of sensing amplifier comprises a plurality of sensing amplifier rows, and each package contains a sensing amplifier with an output, each output data line in the plurality of output data line of this output driving.
In the example marking at Fig. 1, this storage arrangement comprises N storer row, arrange 1, row 2 ... row N, wherein N can be 4,8,16 etc.This storage arrangement comprises 128 output data lines, and it comprises output data line DL
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128.Each storer row can comprise memory cell array, and it comprises a plurality of row and a plurality of row.In the example shown in Fig. 1, each row can comprise 128 row.One column decoder 140 is coupled to a plurality of character lines, and line decoder 170 is coupled to a plurality of bit lines.A plurality of sensing amplifiers 180 are these line decoders 170 that couple as for the input of sensing amplifier 180.
In the example marking at Fig. 1, this storage arrangement more comprises data and exports many merits multiplexer 193, and it has the output data line of being coupled to DL
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128input.Pre-charge circuit 190 is coupled to output data line, and for example the output of sensing amplifier 180 and this data are exported the DL between the input of many merits multiplexer 193
1, DL
2..., DL
n+1, DL
n, DL
n+1..., DL
127, and DL
128.Output data are via output data line DL
1, DL
2..., DL
n-1, DL
n, DL
n+1..., DL
127, and DL
128and provide the input of exporting many merits multiplexer 193 to these data from the output of sensing amplifier 180.Data are exported the sense datas that many merits multiplexer 193 is selected 128 output online data, and from the subset output sensing data of 128 output data lines.In one embodiment, data are exported many merits multiplexer 193 and can be exported the data of 16 by 16 output data lines from 128 output data lines.Output driver 197 has via data line 195 and is coupled to the input that data are exported the output of many merits multiplexer 193.Output driver 197 drives selected sense data to the destination in storage arrangement outside.
Article 128, the output data line in output data line (for example DLn) can be coupled to the corresponding sense amplifier in each storer row in N storer row.For example, if N=16, this output data line DLn can be coupled to the output of 16 sensing amplifiers, and wherein in these 16 sensing amplifiers, each is from different storer rows.If a storer row is selected, for example by row's code translator 150, selected, for an output buffer of this storer row's a sensing amplifier can active drive one output data line (DL for example
n) to the voltage level corresponding to the data of new logic level (1 or 0).Or if a storer row is selected, the output buffer of a sensing amplifier of arranging for this storer can, in a high impedance status, not drive this output data line of the output that receives sensing amplifier.If a storer row is selected, an output buffer of a sensing amplifier of arranging for this storer, in high impedance status, does not drive this output data line of the output that receives sensing amplifier.
Repeatability (for example 128), the length of output data line and the compact configuration of output data line due to output data line, stray capacitance between output data line can require the extra duration of charging during data-switching, and therefore affects the data transfer rate in output online data data-switching.For example, output data line can have approximately 5,000 length of μ m (micron), the stray capacitance of 0.5pF (micromicrofarad) between the interval between the two adjacent output data lines of the thickness of the width of approximately 0.4 μ m, approximately 0.8 μ m, approximately 0.4 μ m and two adjacent output data lines.Most of output data line has adjacent output data line in its both sides, therefore be coupled to the twice that the stray capacitance of the combination of single output data line can be 0.5pF or 1pF.
For minimum parasitic capacitance is for the impact of data-switching time and the therefore impact on data transfer rate, pre-charge circuit 190 is carried out the stray capacitance between precharge output data line in sense operation at sensing amplifier 180.The operation of pre-charge circuit 190 and pre-charge circuit 190 is further described in this.
Fig. 2 is the schematic diagram of illustrating a circuit that comprises output data line, and this output data line receives the output of sensing amplifier and between it, has stray capacitance (prior art).Output data line carries sense data to data from the output of sensing amplifier and exports many merits multiplexer.In the example marking at Fig. 2, data are exported many merits multiplexer 293 and are selected the sense data of 128 output online data from a storer row, and from a subset of 128 output data lines, provide sense data to this output driver 297 via data line 295.This output data line has stray capacitance between adjacent output data line.For example, Fig. 2 describes the output data line DL in a memory array
1, DL
2..., DL
n-1, DL
n, DL
n+1..., DL
127, and DL
128.In an embodiment, the number of output data line can be 64,128,256 etc., and it is corresponding to the line number in a memory array.Each output data line is to be driven by a sensing amplifier.For example, as shown in the figure, output data line DL
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128to be driven by sensing amplifier 221-227.
Fig. 2 illustrates output data line DL
1, DL
2..., DL
n-1, DL
n, DL
n+1..., DL
127, and DL
128between stray capacitance 251-256.In the example shown in Fig. 2, stray capacitance 251 is between adjacent output data line DL
1and DL
2between, and stray capacitance 256 is between adjacent output data line DL
127and DL
128between.
In the example shown in Fig. 2, in sensing amplifier (representing with SA in the drawings) 221-227, each has a sense node V
cELL, be coupled to a reference voltage V
rEFone second input and the output that is connected to output data line.This sense node V
cELLto be coupled to the selected storage unit in this memory array via line decoder.Sensing signal SAEN and output control signal SAOUT are coupled to each of sensing amplifier 221-227.
Fig. 3 illustrates the sequential chart in the switching time of output online data for the circuit described in Fig. 2 (prior art).Fig. 3 describes output data line DL
n-1, DL
n, and DL
n+1on data, it switches between the first voltage level VDD corresponding to logic high data and the second voltage level GND corresponding to logic-low data.Fig. 3 be illustrated in sensing signal SAEN at time t1 the conversion from logic low to logic high 310 and among output control signal SAOUT at time t2 the sensing interval between the conversion from logic low to logic high 320.Or the conversion in sensing signal SAEN can be from logic high to logic low, and the conversion in output control signal SAOUT can be from logic high to logic low.During ending at the initial gap of time t1, output data line DL
n-1, DL
n, and DL
n+1on data be to keep from previous sense operation.Sensing interim between time t1 and time t2, output data line DL
n-1, DL
n, and DL
n+1on data remain unchanged.An output gap after sensing interval originates in time t2, output data line DL
n-1, DL
n, and DL
n+1on data start to change, as the output buffer in sensing amplifier drives, the voltage level of the data that keep from the sense operation corresponding to from previous is changed into the voltage level corresponding to current sense data.
In the example marking at Fig. 3, output data line DL
n-1and DL
n+1on data from VDD, change into GND, and output data line DL
non data from GND, change into VDD.With reference to figure 2, stray capacitance 253 is between output data line DLn-1 and DL
nbetween, and stray capacitance 254 is between output data line DL
nand DL
n+1between.Therefore, the voltage on an end points of stray capacitance 253 is changed into GND from VDD, and voltage on another end points of stray capacitance 253 is changed into VDD from GND.Moreover the voltage on an end points of stray capacitance 254 is changed into VDD from GND, and voltage on another end points of stray capacitance 254 is changed into GND from VDD.
Generally speaking, the change that strides across the voltage difference of stray capacitance can cause capacitor charging, owing to being the function of electric capacity switching time, therefore itself then cause the delay of the switching time from a voltage level to another voltage level.Stray capacitance 253 and stray capacitance 254 are all coupled to output data line DL
n.For output data line DL
n, situation worst of aspect switching time occurs in as output data line DL
n-1and DL
n+1have and DL
nvoltage change the voltage that direction (for example, from GND to VDD) is contrary and change direction (for example, from VDD to GND), and be all coupled to output data line DL
ntwo stray capacitances be coupled to output data line DL
nsensing amplifier charge simultaneously, this causes extra time delay.
If an output data line charges to VDD by a stray capacitance from GND via the wherein one end at the two ends of stray capacitance, for example, and the other end at these two ends remains on GND (0V) during charging procedure, the electric charge that being coupled to the sensing amplifier of output data line provides can be characterized as CC * VDD, and wherein CC is the electric capacity of this stray capacitance.
An if output data line (DL for example
n) via each the wherein one end at two ends of two stray capacitances, two stray capacitances (for example 253,254) are charged to VDD from GND, and each the other end at two ends of these two stray capacitances remains on GND during charging procedure, is coupled to output data line DL
nthe total electrical charge that provides of sensing amplifier can be characterized as 2 * CC * VDD.
In the worst case example shown in Fig. 3, an output data line (DL for example
n) via the first end at the two ends of two stray capacitances, two stray capacitances (for example 253,254) are charged to VDD from GND, and the voltage of second end at the two ends of these two stray capacitances is changed into GND from VDD simultaneously.Worst in the situation that, the total electrical charge that being coupled to the sensing amplifier of output data line DLn provides can be characterized as 2 * 2 * CC * VDD.
In 2 * 2 * CC * VDD, one of them factor 2 is for the charge fact of two stray capacitances being coupled to an output data line of sensing amplifier simultaneously.Another factor 2 be for, at charging procedure therebetween, first voltage at the first end place at the two ends of two stray capacitances changes direction (for example, from GND to VDD) in contrast to the second voltage change direction (for example, from VDD to GND) of second end at the two ends of two stray capacitances.Reverse direction also can comprise first end place and from the second voltage of GND to VDD, change direction from the first voltage change direction and the second end of VDD to GND.Therefore the maximum total voltage, swinging between each two ends of two stray capacitances is 2 * VDD.
Fig. 4 is the schematic diagram of illustrating the embodiment of a pre-charge circuit, and this pre-charge circuit is that the output online data being configured in storage arrangement according to the present invention applies pre-charge voltage.This storage arrangement comprises memory cell array.This storage arrangement comprise be coupled to a plurality of sensing amplifiers of this array, a plurality of output data lines and being configured to that receive the output of corresponding sense amplifier in the plurality of sensing amplifier apply pre-charge voltage at a plurality of pre-charge circuits of output online data.This output data line is carried into data by sense data from the output of sensing amplifier and exports many merits multiplexer 493.Data are exported many merits multiplexer 493 and are selected the sense data of 128 output online data from a storer row, and from a subset of 128 output data lines, provide sense data to output driver 497 via data line 495.
In the example marking at Fig. 4, storage arrangement comprises many output data lines, comprises output data line DL
1, DL
2..., DL
n-1, DL
n, DL
n+1..., DL
127, and DL
128.In an embodiment, the number of output data line can be 64,128,256 etc., and it is corresponding to the line number in a memory array.Each output data line is at least one output that is coupled to sensing amplifier.For example, output data line DL
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128be coupled to the output of sensing amplifier 421-427.Fig. 4 illustrates output data line DL
1, DL
2..., DL
n-1, DL
n, DL
n+1..., DL
127, and DL
128between stray capacitance 441-446.For example, stray capacitance 441 is between adjacent output data line DL
1and DL
2between, and stray capacitance 446 is between adjacent output data line DL
127and DL
128between.
In the example shown in Fig. 4, in sensing amplifier 421-427, each has a sense node V
cELL, be coupled to a reference voltage V
rEFone second input and an output that drives an output data line.This sense node V
cELLbe coupled to the selected storage unit in this memory array.Sensing signal SAEN and output control signal SAOUT are coupled to each of sensing amplifier 421-427.
In the present embodiment, pre-charge circuit (for example 451) is coupled to an output data line in the plurality of output data line (DL for example
1).This pre-charge circuit comprise be coupled to pre-charge voltage (for example VDD) first end, be coupled to this output data line (DL for example
1) the second end and the gate terminal that is coupled to the precharging signal PRESETB that controller provides.In the example shown in Fig. 4, pre-charge circuit 451-457 is coupled to respectively output data line DL
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128.
Electrically upper, output data line switches between the first voltage level VDD corresponding to logic high data and the second voltage level GND corresponding to logic-low data.Although pre-charge voltage is rendered as VDD in Fig. 4, the pre-charge voltage that is coupled to the first end of pre-charge circuit can be VDD or GND.
Although for example, for pre-charge circuit (451) PMOS transistor is only shown in Fig. 4, pre-charge circuit can comprise PMOS transistor, nmos pass transistor or CMOS transistor.If pre-charge circuit comprises a CMOS transistor, this pre-charge circuit has that to be coupled to a second gate of complementary precharging signal extreme, and this complementation precharging signal is to be provided by controller.
Fig. 5 is the schematic diagram of illustrating an example of output data line, and this output data line is to drive and be coupled to the pre-charge circuit in the storage arrangement with control signal by sensing amplifier.This storage arrangement comprises a controller, and it provides this control signal, comprises a sensing signal SAEN, output control signal SAOUT and a precharging signal PRESETB.This precharging signal is to produce with at least one of them coordination of this sensing signal SAEN and this output signal, to determine that the precharge operation of pre-charge circuit is to complete with the sense operation of sensing amplifier simultaneously, (for example 193, the output online data between Fig. 1) does not increase time delay to make this precharge operation export many merits multiplexer in the sensing amplifier of driver output data line and the data that receive data in output online data.
This controller for example enables some sensing amplifiers in the plurality of sensing amplifier (for example 424,425) via sensing signal SAEN and in the sensing interim that starts from the very first time, is sensed in the data input (V for example of sensing amplifier (for example 424,425)
cELL) data.This controller for example for example enables the second time output sensing data of this sensing amplifier (for example 424,425) after the very first time, to this output data line (DL via output control signal SAOUT
n, DL
n+1).This controller for example enables for example, during the pre-charge interval of this pre-charge circuit (454,455) before the second time this output data line of precharge (DL for example via precharging signal PRESETB
n, DL
n+1).This pre-charge interval can be shorter than or equal this sensing interval.
In the example shown in Fig. 5, precharging signal PRESETB is for example produced as at least function of one of them of this sensing signal SAEN and this output control signal SAOUT by branch circuit (sub-circuit) 560.This branch circuit 560 uses a Sheffer stroke gate (NAND gate) 563 and one reverser or non-grid (NOT gate) 561.The function of precharging signal can be represented as PRESETB=(SAEN NAND (NOT SAOUT)).This area has the variation that common skill person can find out this function easily.Example time relationship between precharging signal PRESETB and sensing signal SAEN and output control signal SAOUT is described in Fig. 6, Fig. 7, Fig. 9 and Figure 10.
In the example shown in Fig. 5, two sensing amplifiers 424 and 425 are described more in detail compared to Fig. 4.Each sensing amplifier has a sense node V
cELL, be coupled to reference voltage V
rEFone second input, an and output that is connected to output data line.One sense node V
cELLbe connected to the selected storage unit in this memory array.Sensing signal SAEN and output control signal SAOUT are coupled to this sensing amplifier 424 and 425.Pre-charge circuit 454 and 455 is coupled to respectively output data line DL
nand DL
n+1.One stray capacitance 444 is between output data line DL
nand DL
n+1between.
Although sensing signal SAEN and output control signal SAOUT are depicted as only to control two sensing amplifiers, in an embodiment, one sensing signal and an output control signal can be controlled more sensing amplifiers, 32,64,128 sensing amplifiers in a storer row for example, and the sensing amplifier in multi-memory row more even.Similarly, although precharging signal PRESETB is depicted as only to control two pre-charge circuits, a precharging signal can be controlled more pre-charge circuits in an embodiment, 32,64,128 pre-charge circuits in a storer row for example, and the pre-charge circuit in multi-memory row more even.
Sensing amplifier 424 comprises a sensing circuit 541 and an output buffer circuit 547.Sensing circuit 541 sensing sense node V
cELLand reference voltage V
rEFbetween voltage difference, its representative is stored in the data value in a storage unit, for example binary one or 0.Sensing circuit 541 provides the input of sense data 545 to output buffer circuit 547.This output buffer circuit 547 then amplifies this sense data 545 to a logic level that is suitable for being for further processing in storage arrangement, and exports this sense data to this output data line DL
n.This output data line DL
nbe coupled to circuit component, for example data are exported many merits multiplexer 193 (Fig. 1).
Similarly, sensing amplifier 425 comprises a sensing circuit 551 and an output buffer circuit 557.Sensing circuit 551 sensing sense node V
cELLand reference voltage V
rEFbetween voltage difference, its representative is stored in the data value in a storage unit, for example binary one or 0.Sensing circuit 551 provides the input of sense data 555 to output buffer circuit 557.This output buffer circuit 557 then amplifies this sense data 555 to a logic level that is suitable for being for further processing in storage arrangement, and exports this sense data to this output data line DL
n+1.This output data line DL
n+1be coupled to circuit component, for example data are exported many merits multiplexer 193 (Fig. 1).
One output data line (DL for example
n) and an adjacent output data line (DL for example
n+1) between stray capacitance can be for example 0.5pF, an and output data line (DL for example
n) and two adjacent output data lines (DL for example
n-1, DL
n+1) between combination stray capacitance can be 1.0pF.The total load of one output online data can be for example 1.4pF, and it comprises data and exports the load of input of many merits multiplexer and the combination stray capacitance between output data line.Therefore,, compared to this total load, postpone the extra time that stray capacitance causes is important for data-switching.
Fig. 6 and Fig. 7 are the sequential charts of the embodiment of the pre-charge circuit described for Fig. 4 and Fig. 5.In the example shown in Fig. 6 and Fig. 7, output data line DL
n-1, DL
nand DL
n+1on data between the first voltage level VDD corresponding to logic high data and the second voltage level GND corresponding to logic-low data, switch.Fig. 6 illustrate in sensing signal SAEN at the very first time t1 conversion from logic low to logic high 610 and among output control signal SAOUT at very first time t1 the second time t2 subsequently the sensing interval P1 between the conversion 620 from logic low to logic high.Or the conversion in sensing signal SAEN can be from logic high to logic low, and the conversion in output control signal SAOUT can be from logic high to logic low.
Fig. 6 illustrates pre-charge interval P2 and is shorter than or equals sensing interval P1, and it starts from very first time t1 or starts after it, and ends at the second time t2 or finished before it.In the example shown in Fig. 6, in precharging signal PRESETB, this pre-charge interval P2 is between conversion 630 and the conversion from logic low to logic high 640 from logic high to logic low.Or this conversion 630 can be from logic low to logic high, and this conversion 640 can be from logic high to logic low.In other embodiments, if the output of sensing amplifier does not have driving data output line at the second time t2 of the previous read cycle for immediately and between for the very first time t1 of current read cycle, for the pre-charge interval P2 of a current read cycle can be before the very first time t1 for current read cycle and the second time t2 for previous read cycle immediately after start.
In the example shown in Fig. 6, during ending at an initial gap of very first time t1, output data line DL
n-1, DL
n, DL
n+1on data be to keep from previous sense operation.During the sensing interval P1 between very first time t1 and the second time t2, sensing amplifier is to be enabled in response sensing signal SAEN and the data of the data input of this sensing amplifier of sensing.During pre-charge interval P2, in response to precharging signal PRESETB, output data line DL
n-1, DL
n, DL
n+1on data from changing into pre-charge voltage 650 corresponding to the voltage level keeping from previous sense operation.In the example shown in Fig. 6, pre-charge voltage 650 is that it is corresponding to the data of logic high in about voltage level VDD.In another embodiment, pre-charge voltage can be that it is corresponding to the data of logic low in about voltage level GND.
Precharging signal PRESETB can start and is coupled to output data line (DL for example during pre-charge interval P2
n, pre-charge circuit Fig. 4) (for example 454, Fig. 4), and before pre-charge interval P2 and close afterwards this pre-charge circuit.When pre-charge circuit is activated, the output data line that is coupled to pre-charge circuit is precharged to a pre-charge voltage by the voltage level by keeping from previous sense operation.This pre-charge voltage can comprise VDD and GND.
For example, the first end of pre-charge circuit 454 is coupled to the pre-charge voltage 650 (Fig. 4) of VDD, correspondingly, and this output data line DL
n(Fig. 5) at the second time t2, be precharged to the pre-charge voltage 650 of VDD.Or, if the first end of pre-charge circuit 454 is coupled to the pre-charge voltage of GND, correspondingly, this output data line DL
nat the second time t2, be precharged to GND.
After the second time t2, this output data line is urged to an output-voltage levels by the pre-charge voltage 650 from VDD, and it is corresponding to the sense node V of the sensing amplifier of driver output data line
cELLthe data of place sensing.This output-voltage levels comprises VDD and GND.
In conjunction with the prior art being described in Fig. 3, for output data line DL
n, switching time, the worst case of aspect betided as output data line DL
n-1and DL
n+1have and DL
nvoltage change the voltage that direction (for example, from GND to VDD) is contrary and change direction (for example, from VDD to GND).With reference to figure 4, this stray capacitance 443 is between output data line DL
n-1and DL
nbetween, and stray capacitance 444 is between output data line DL
nand DL
n+1between.
In the example marking at Fig. 6, output data line DL
n-1and DL
n+1on the VDD of data from very first time t1 change to the GND after the second time t2, and the GND of DLn from very first time t1 changes to the VDD after the second time t2.During pre-charge interval P2, no matter the voltage level keeping from previous sense operation is why, output data line DL
n-1, DL
nand DL
n+1on data change to pre-charge voltage 650 (it is approximately the voltage level VDD corresponding to logic high data).Therefore,, after the second time t2, when output control signal, SAOUT establishes, output data line DL
non data dimension to be held in VDD constant, this reduce the indivedual stray capacitances of charging (for example 443 and 444, demand Fig. 4), and therefore reduce the time delay after the second time t2.
Description about sequential chart in Fig. 6 roughly can be applied to the sequential chart in Fig. 7.In the example marking at Fig. 7, output data line DL
n-1on the GND of data from very first time t1 change into the VDD after the second time t2, output data line DL
non data before very first time t1, start from ending at GND after GND and the second time t2, and output data line DL
n+1on data before very first time t1, start from ending at VDD after VDD and the second time t2.During pre-charge interval P2, output data line DL
n-1, DL
n, and DL
n+1on data change to pre-charge voltage 750, no matter it is approximately the voltage level VDD corresponding to logic high data, and the voltage level keeping from previous sense operation.Therefore,, after the second time t2, when output control signal, SAOUT establishes, output data line DL
n-1on data and output data line DL
n+1on data dimension to be held in VDD constant.
In the example shown in Fig. 6 and Fig. 7, voltage changes to GND only at output data line DL from VDD
n-1and DL
nbetween one end of stray capacitance 443, and only at output data line DL
nand DL
n+1between one end of stray capacitance 444, for the example shown in Fig. 6 and Fig. 7, this causes the charging of 2 * CC * VDD, is to have reduced for its situation worst of charging of 2 * 2 * CC * VDD describe in prior art to(for) Fig. 3.
Therefore with respect to prior art under identical worst case, be coupled in the present embodiment output data line DL
nsensing amplifier consume less charging and drive this output data line DL
nto a different voltage level.The charging consuming in situation worst can be reduced to 2 * CC * VDD by 2 * 2 * CC * VDD, and wherein CC is the electric capacity of stray capacitance, and the factor in 2 * CC * VDD 2 illustrates the situation that the stray capacitance at the two ends of output data lines is charged simultaneously.
In the example marking at Fig. 6, data-switching is corresponding to the worst case of the prior art that betides Fig. 3 associated description.In the example marking at Fig. 7, the situation beyond data-switching explanation situation worst.In above-mentioned two situations, the consumption of charging is about 2 * CC * VDD, or half of charge volume that worst case consumes in prior art.
Fig. 8 is the schematic diagram of illustrating the second embodiment of pre-charge circuit, and it is that the output online data being configured in storage arrangement according to the present invention applies pre-charge voltage.This storage arrangement comprises memory cell array.A plurality of output data lines of the output that this storage arrangement comprises a plurality of sensing amplifiers of coupling with memory cell array, receive corresponding sense amplifier in the plurality of sensing amplifier and be configured to apply pre-charge voltage at a plurality of pre-charge circuits of this output online data.This output data line is carried into data by sense data from the output of sensing amplifier and exports many merits multiplexer 893.Data are exported many merits multiplexer 893 and are selected the sense data of 128 output online data from a storer row, and from the subset of 128 output data lines, provide sense data to output driver 897 via data line 895.
In the example marking at Fig. 8, storage arrangement comprises a plurality of output data lines, comprises output data line DL
1, DL
2..., DL
n-1, DL
n, DL
n+1..., DL
127, and DL
128.In an embodiment, the number of output data line can be 64,128,256 etc., and it is corresponding to the line number in a memory array.Each output data line is coupled at least one output of a sensing amplifier.For example, output data line DL
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128be coupled to the output of sensing amplifier 821-827.Fig. 8 illustrates output data line DL
1, DL
2..., DL
n-1, DL
n, DL
n+1..., DL
127, and DL
128between stray capacitance 841-846.For example, stray capacitance 841 is between adjacent output data line DL
1and DL
2between, and stray capacitance 846 is between adjacent output data line DL
127and DL
128between.
In the example shown in Fig. 8, in this sensing amplifier 821-827, each has a sense node V
cELL, be coupled to a reference voltage V
rEFone second input and an output that drives an output data line.This sense node V
cELLbe coupled to the selected storage unit in memory array.One sensing signal SAEN and an output control signal SAOUT are coupled to each of this sensing amplifier 821-827.
In the present embodiment, pre-charge circuit (for example 851) has and is coupled to an output data line (DL for example
1) a first end, be coupled to (the DL for example of an adjacent output data line in the plurality of output data line
2) one second end and a gate terminal that is coupled to this precharging signal PRESETB.As described in Fig. 8, pre-charge circuit 851-856 is coupled to output data line DL
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128.
In the example shown in Fig. 8, this pre-charge circuit (for example 851) is a CMOS transistor, and it has, and to be coupled to the second gate of the complementary precharging signal PRESET that this controller provides extreme.This complementation precharging signal has the opposite polarity polarity with this precharging signal.Or this pre-charge circuit can be PMOS transistor or nmos pass transistor.
Fig. 9 and Figure 10 are the sequential charts of the embodiment of the pre-charge circuit described for Fig. 8.In the example shown in Fig. 9 and Figure 10, output data line DL
n-1, DL
n, and DL
n+1on data between the first voltage level VDD corresponding to logic high data and the second voltage level GND corresponding to logic-low data, switch.Fig. 9 illustrate in sensing signal SAEN at the very first time t1 conversion from logic low to logic high 610 and among output control signal SAOUT at very first time t1 the second time t2 subsequently the sensing interval P1 between the conversion 620 from logic low to logic high.Or the conversion in sensing signal SAEN can be from logic high to logic low, and the conversion in output control signal SAOUT can be from logic high to logic low.
Fig. 9 illustrates pre-charge interval P2 and is shorter than or equals sensing interval P1, and it starts from very first time t1 or starts after it, and ends at the second time t2 or finished before it.In the example shown in Fig. 9, in precharging signal PRESETB, this pre-charge interval P2 is between conversion 630 and the conversion from logic low to logic high 640 from logic high to logic low.Or this conversion 630 can be from logic low to logic high, and this conversion 640 can be from logic high to logic low.Fig. 9 also illustrates by this controller and produces and have a complementary precharging signal PRESET with the opposite polarity polarity of this precharging signal PRESETB.
In the example shown in Fig. 9, during ending at an initial gap of very first time t1, output data line DL
n-1, DL
n, DL
n+1on data be to keep from previous sense operation.During the sensing interval P1 between very first time t1 and the second time t2, sensing amplifier is to be enabled in response sensing signal SAEN and the data of the data input of this sensing amplifier of sensing.During pre-charge interval P2, in response to precharging signal PRESETB and this complementation precharging signal PRESET, output data line DL
n-1, DL
n, DL
n+1on the voltage level that kept by sense operation from previous of data change into pre-charge voltage 950.As shown in Figure 9, this pre-charge voltage 950 is in the first voltage level VDD between corresponding to logic high data and corresponding to the voltage level between the second voltage level GND of logic-low data, and this depends on this voltage level that this output online data keeps from previous sense operation.
This precharging signal PRESETB and this complementation precharging signal PRESET can start and be coupled to two adjacent output data lines (DL for example during pre-charge interval P2
nand DL
n+1, pre-charge circuit Fig. 8) (for example 854, Fig. 8), and before pre-charge interval P2 and close afterwards this pre-charge circuit.When pre-charge circuit is activated, output data line (DL for example
n-1, DL
n, and DL
n+1) by the voltage level by keeping from previous sense operation, be precharged to this pre-charge voltage 950.Because when pre-charge circuit is opened, this output data line (DL for example
1, DL
2, DL
n-1, DL
n, DL
n+1, DL
127, and DL
128) be for example, to connect via this pre-charge circuit (851-856), this pre-charge voltage 950 can be between the voltage level VDD corresponding to logic high data and the voltage level GND corresponding to logic-low data " impartial (equalized) " voltage level, this depends on that this output online data is from these indivedual voltage levels of previous sense operation maintenance.
After the P1 of sensing interval, this output data line is urged to an output-voltage levels from this pre-charge voltage 950, and it is corresponding to this sense node V that drives this sensing amplifier of this output data line
cELLthe data that place senses.This output-voltage levels comprises VDD and GND.
Description about sequential chart in Fig. 9 roughly can be applied to the sequential chart in Figure 10.In the example shown in Figure 10, during ending at the initial gap of very first time t1, output data line DL
n-1, DL
n, and DL
n+1on data be to keep from previous sense operation.During the sensing interval P1 between very first time t1 and the second time t2, sensing amplifier is to be enabled in response sensing signal SAEN and the data of the data input of this sensing amplifier of sensing.During pre-charge interval P2, in response to this precharging signal PRESETB and this complementation precharging signal PRESET, output data line DL
n-1, DL
n, DL
n+1on the voltage level that kept by sense operation from previous of data change into pre-charge voltage 1050.As shown in figure 10, this pre-charge voltage 1050 is in the first voltage level VDD corresponding to logic high data with corresponding to the voltage level between the second voltage level GND of logic-low data, and this depends on this voltage level that this output online data keeps from previous sense operation.
In the example shown in Fig. 9 and Figure 10, after the P1 of sensing interval, output data line DL
n-1, DL
n, and DL
n+1on data from " impartial " voltage level 950 between VDD and GND, change to the output-voltage levels corresponding to sense data, by this during data-switching, from the whole range of voltage swing between VDD and GND, reduce the amplitude of voltage swing, and therefore improve the reading rate in storage unit.
Therefore, with respect to prior art, under identical worst case, be coupled in the present embodiment an output data line (DL in Fig. 8 for example
n) a sensing amplifier (for example 824, Fig. 8) consume less charging and drive the different voltage level of this output data line to one.The charging consuming in situation worst can be reduced to 2 * CC * VDD by 2 * 2 * CC * VDD, and wherein CC is the electric capacity of stray capacitance.From 2 * 2 to 2 minimizing is because the maximum total voltage amplitude of oscillation between stray capacitance two ends is by being reduced to VDD for the described 2 * VDD of worst case shown in Fig. 3.
In the example marking at Fig. 9, data-switching is described in prior art situation worst corresponding to Fig. 3.In the example marking at Figure 10, data-switching is described the situation beyond worst case.In above-mentioned two situations, the consumption of charging is about 2 * CC * VDD, or half of charge volume that worst case consumes in prior art.
In described embodiment, precharge operation is to carry out in the output online data being shorter than or equal to drive at sensing amplifier during a pre-charge interval at a sensing interval herein, at this sensing this sensing amplifier of interim, carries out sense operation.Typically, sense operation than precharge operation more complicated and need longer time.For example, the sensing time can be 60ns, and can be 10ns precharge time.Owing to being presented on the repeatability of output data line on wiring diagram, (for example every row is 128, and Fig. 1), output data line may have diversified length, and therefore has diversified electric capacity.Because compared to precharge operation, the time that sense operation need to be longer, precharge operation may be shorter than even in the pre-charge interval at this sensing interval and complete in the output online data with diversified length.Therefore, this precharge operation can not affect the data transfer rate that uses this output data line reading cells.
Figure 11 is the simplification calcspar according to the storage arrangement of an embodiment.This integrated circuit 1100 comprises the memory array 1160 on an ic substrate.One column decoder 1140 is coupled to a plurality of word lines 1145 and is configured by a plurality of row in this memory array 1100.One line decoder 1170 is coupled to a plurality of bit lines 1165, and it is configured by a plurality of row in this memory array 1160, to read and to programme from the data of this storage unit in this memory array 1160.One row's code translator 1150 is coupled to a plurality of rows in this memory array 1160 in bus 1155.Address is in bus 1130, to be supplied to line decoder 1170, column decoder 1140 and row's code translator 1150.In this example, the sensing amplifier in square 1180 and data input structure are to be coupled to this line decoder 1170 via data bus 1175.Data are I/O ports from this integrated circuit 1100 or inner or other outside data sources are supplied to this data input structure square 1180 from this integrated circuit 1100 via Data In-Line 1105.
In the example marking at Figure 11, data are exported many merits multiplexer 1193 and are had the input that is coupled to this output data line 1185, and pre-charge circuit 1190 is coupled to output and the data of the sensing amplifier in this square 1180 and exports this output data line 1185 between many merits multiplexer 1193.Output driver 1197 has via data line 1195 and is coupled to the input that these data are exported the output of many merits multiplexer 1193.Data are exported many merits multiplexer 1193 one of them this output data line 1185 of this storer row from this memory array 1160 and are selected sense data.Output driver 1197 drives selected sense data to the destination of these integrated circuit 1100 outsides.
For example, a storage arrangement can have N row's storage unit, and each row can comprise 128 row that are coupled to 128 output data lines.These data are exported many merits multiplexer 1193 can select data from 128 output data lines of a storer row, and this output driver 1197 can be from the some of them output data of these 128 output data lines.
In the example shown in Figure 11, one controller 1110 is controlled this sensing amplifier and this pre-charge circuit 1190 in these squares 1180, its comprise cause this pre-charge circuit 1190 at this sensing amplifier driver output data-signal to this output data line 1185 of precharge before this output data line 1185.In the example shown in Figure 11, this controller 1110 provides control signal, and it can comprise a sensing signal 1111, an output signal 1112 and a precharging signal 1113.This precharging signal is at least function of one of them that is produced as this sensing signal 1111 and this output signal 1112.This controller 1110 enables sensing amplifier in the plurality of sensing amplifier via sensing signal 1111 and in the sensing interim that starts from the very first time, is sensed in the data of the data input of sensing amplifier.This controller 1110 enables the second time output sensing data of this sensing amplifier after the very first time to this output data line via output signal 1112.This controller enables this output data line 1185 of precharge during pre-charge circuit in this square 1190 pre-charge interval before the second time via precharging signal 1113.
These controller 1110 use one bias voltages arrange state machine that the application via the bias voltage arrangement that one or more Voltage Supply Device produced or the provided supply voltage in square 1120 is provided, for example, read and program voltage.Can implement this controller 1110 with special-purpose object logical circuit known in the art.In alternative embodiment, this controller comprises a general processor, and it can carry out on this identical integrated circuit, and this identical integrated circuit is carried out a computer program to control the operation of this device.In other embodiments, the combination of special-purpose object logical circuit and a general processor can be utilized the enforcement for this controller.
In the example shown in Figure 11, the pre-charge circuit in square 1190 is coupled to the output of this sensing amplifier in square 1180 via output data line 1185.This controller 1110 provides a precharging signal 1113 of this pre-charge circuit being coupled in square 1190.This precharging signal 1113 starts this pre-charge circuit in square 1190 during pre-charge interval, and before pre-charge interval and close afterwards this pre-charge circuit.
Generally speaking, be described in this and can be applied to data line that integrated circuit is placed closely together for other functions for improving the method for the reading rate on the output data line of sensing amplifier and device embodiment.
The present invention is by reference to preferred embodiment and example as described above and disclose, and understandable, these examples are intended in description and unrestricted object.Can make easily to those skilled in the art and revising and combination, this modification and combination are by the scope of the claim scope that drops on spirit of the present invention and enclose.
Claims (23)
1. a storage arrangement, comprising:
One memory cell array;
A plurality of sensing amplifiers that couple with this memory cell array;
A plurality of output data lines, it receives the output of corresponding sense amplifier in the plurality of sensing amplifier; And
A plurality of pre-charge circuits, are configured to apply a pre-charge voltage and export online data at this, wherein this pre-charge circuit at this sensing amplifier driver output data-signal to this output data line of first precharge before this output data line.
2. storage arrangement according to claim 1, more comprise a controller, it provides this sensing amplifier of controlling signal in the plurality of sensing amplifier and this pre-charge circuit in the plurality of pre-charge circuit, comprise cause this pre-charge circuit at this sensing amplifier driver output data-signal to this output data line of first precharge before this output data line.
3. storage arrangement according to claim 1, a plurality of rows that wherein the plurality of sensing amplifier comprises sensing amplifier, and each package is containing a sensing amplifier with an output of each output data line driving in the plurality of output data line.
4. storage arrangement according to claim 1, more comprise that data export many merits multiplexer, it has the input that is coupled to this output data line, and this pre-charge circuit is coupled to this sensing amplifier output and these data are exported this output data line between many merits multiplexer.
5. storage arrangement according to claim 2, wherein this controller enables this sensing amplifier and is sensed in the data of the data input of this sensing amplifier, one second time output sensing data after this very first time to this output data line and this output data line of precharge during enabling the pre-charge interval of this pre-charge circuit before this second time in the sensing interim that starts from a very first time.
6. storage arrangement according to claim 5, wherein this pre-charge interval is shorter than or equals this sensing interval.
7. storage arrangement according to claim 5, wherein this pre-charge interval starts from this very first time or starts after this very first time.
8. storage arrangement according to claim 5, wherein this pre-charge interval ends at this second time or finished before this second time.
9. storage arrangement according to claim 2, wherein the pre-charge circuit in the plurality of pre-charge circuit comprise be coupled to this pre-charge voltage a first end, be coupled to one second end of the output data line in the plurality of output data line and a gate terminal that is coupled to controller.
10. storage arrangement according to claim 2, wherein the pre-charge circuit in the plurality of pre-charge circuit comprise be coupled to the output data line in the plurality of output data line a first end, be coupled to one second end of the adjacent output data line in the plurality of output data line and a gate terminal that is coupled to this controller.
11. storage arrangements according to claim 1, wherein this pre-charge voltage comprises the voltage level corresponding to logic high data.
12. storage arrangements according to claim 1, wherein this pre-charge voltage comprises the voltage level corresponding to logic-low data.
13. storage arrangements according to claim 1, wherein this pre-charge voltage is in one first voltage level corresponding to logic high data and corresponding to the voltage level between a second voltage level of logic-low data.
14. 1 kinds of methods for the data of sensing one storage arrangement, a plurality of output data lines of a plurality of sensing amplifiers that this storage arrangement comprises a memory cell array, couple with this memory cell array, the output that receives corresponding sense amplifier in the plurality of sensing amplifier and be configured to apply a pre-charge voltage at a plurality of pre-charge circuits of this output online data, the method comprises:
Control this sensing amplifier and this pre-charge circuit in the plurality of sensing amplifier, comprise cause this pre-charge circuit at this sensing amplifier driver output data-signal to this output data line of first precharge before this output data line.
15. methods according to claim 14, wherein this control comprises:
Enable this sensing amplifier in the plurality of sensing amplifier and in the sensing interim that starts from a very first time, be sensed in the data of the data input of this sensing amplifier;
One second time output sensing data after this very first time are to this output data line; And
Enable this output data line of precharge during the pre-charge interval of this pre-charge circuit before this second time.
16. methods according to claim 15, wherein this pre-charge interval is shorter than or equals this sensing interval.
17. methods according to claim 15, wherein this pre-charge interval starts from this very first time or starts after this very first time.
18. methods according to claim 15, wherein this pre-charge interval ends at this second time or finished before this second time.
19. methods according to claim 15, wherein enable during this pre-charge circuit is included in this pre-charge interval to start the pre-charge circuit in the plurality of pre-charge circuit, and before this pre-charge interval and close afterwards this pre-charge circuit.
20. methods according to claim 15, more comprise the sense data of selecting this output online data, and export selected sense data.
21. methods according to claim 14, wherein this pre-charge voltage comprises the voltage level corresponding to logic high data.
22. methods according to claim 14, wherein this pre-charge voltage comprises the voltage level corresponding to logic-low data.
23. methods according to claim 14, wherein this pre-charge voltage is in one first voltage level corresponding to logic high data and corresponding to the voltage level between a second voltage level of logic-low data.
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| CN110891151A (en) * | 2018-09-07 | 2020-03-17 | 爱思开海力士有限公司 | High-speed data reading apparatus and CMOS image sensor using the same |
| CN112767988A (en) * | 2019-10-21 | 2021-05-07 | 铠侠股份有限公司 | Storage system and control method |
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