CN102110462A - Storage integrated circuit and method addressing storage integrated circuit - Google Patents
Storage integrated circuit and method addressing storage integrated circuit Download PDFInfo
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- CN102110462A CN102110462A CN2009102626451A CN200910262645A CN102110462A CN 102110462 A CN102110462 A CN 102110462A CN 2009102626451 A CN2009102626451 A CN 2009102626451A CN 200910262645 A CN200910262645 A CN 200910262645A CN 102110462 A CN102110462 A CN 102110462A
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Abstract
The invention discloses a storage integrated circuit, which comprises a control circuit for accessing a storage unit in the storage integrated circuit. The control circuit is a response instruction comprising a first command for indicating a higher part of an address bit and a second command for indicating a lower part of the address bit. The higher part and the lower part of the address bit form a complete access address of the storage integrated circuit, wherein the first command and the second command have different command codes.
Description
Technical field
The present invention for example is the technology of the storage of serial flash about addressing in the integrated circuit.
Background technology
The serial quickflashing is a kind of kenel of flash memory, and it has a sata standard interface for example is serial peripheral interface (SPI).What series data transmitted is according to serial interface standard.So serial line unit needs less external pins compared to the parallel device with similar memory capacity.For example, pass to about 16,000,000 memory locations of specifying 8 characters in one 128 megabits with one 24 memory address ditches, the serial flash that meets serial peripheral interface (SPI) transmits this 24 memory addresss by an output connecting pin serially, rather than abreast by 24 input pins.
Traditional serial quickflashing uses 24 bit address crossfires can reach the storage space of 128 megabits with the access maximum by the input pin.Because the numerical limitations of address bit addressable storage space, when each addressable point has stored 8 characters, this address limitation of 24 the storage area maximum only can reach 128 megabits, limited potential application.
Yet, do not encourage to revise a memory storage to expand the scope of addressable memory space, because modification compatibility that can to violate a memory storage and existing sata standard interface standard for example be serial peripheral interface (SPI) so, or with the employed instruction set of an existing product can't be compatible, can cause existing be familiar with common standard or the user's of existing instruction set burden.
Summary of the invention
A kind of integrated circuit storage is provided, serial quickflashing for example, new interface has the more access storage space of the 128 megabit storage spaces ability of more traditional serial quickflashing, and still keeps the ability compatible with the serial peripheral interface (SPI) of existing serial flash interface.
Embodiments of the invention have been used many different memory address interfaces and have been stored for high density, and for example serial flash uses.Keep and existing ability, and surpass the restriction that serial flash now uses the addressing capacity of single input pin simultaneously than low capacity storage unit standard interface compatibility.
A purpose of the present invention is for providing a kind of storage integrated circuit, and it has the storage unit in this storage integrated circuit of control circuit access.This control circuit is a response instruction, and this instruction comprises the higher part of one first order with the indication address bit.One second order with the indication address bit one than lower part.The higher part of this of this address bit and this constitute a complete access address of this storage integrated circuit than lower part, and wherein this first order and this second order have different command codes
Another object of the present invention comprises the following step for a kind of method of access one storage integrated circuit is provided:
Store one first order that a higher part of address bit was linked up and indicated to integrated circuit with this.
Link up and indicate one second order than lower part of address bit with this storage integrated circuit, the higher part of this of this address bit and this constitute a complete access address of this storage integrated circuit than lower part, and wherein this first order and this second order have different command codes.
Other different embodiment then is described below.
Description of drawings
The present invention is defined by claim.These and other objects, feature, and embodiment, graphic being described of can in the chapters and sections of following embodiment, arranging in pairs or groups, wherein:
Figure 1A shows a storage instruction, and it has the address of a memory access operational code and 3 bytes.
Figure 1B shows a storage instruction, and it has the address of a memory access operational code and 4 bytes.
Fig. 2 A shows a storage instruction, and it has a memory access operational code and specifies the address of single character access and 3 bytes to specify the address of this single character access, has eliminated and has linked up 3 potential address bits that must use in other cases.
Fig. 2 B shows a storage instruction, and it has a memory access operational code and specifies address of double word symbol access and 3 bytes to specify the address of this double word symbol access, has eliminated and has linked up 4 potential address bits that must use in other cases.
Fig. 2 C shows a storage instruction, and it has a memory access operational code and specifies the address of four character access and 3 bytes to specify the address of this four character access, has eliminated and has linked up 5 potential address bits that must use in other cases.
Fig. 3 A shows a storage instruction, and it has a memory access operational code to specify a higher storage address and a single byte address and two unessential bytes to specify this higher storage address part of a complete memory address.
Fig. 3 B shows a storage instruction, and it has a memory access operational code to specify low memory address and one or three byte addresses to specify this low memory address part of a complete memory address.
Fig. 4 shows the block schematic diagram of a storage chip, it has an address decoder and a storage chip outer encoder, so the storage chip outer encoder is encoded into short address with memory address and represents, and code translator address that this is short is represented to utilize in the common store chip operation to revert to long address again to represent in the storage chip.
Fig. 5 A shows the block schematic diagram of a storage chip, and it has multiple storage array storehouse, one group of pin with low memory address serial communication, and the pin of another group and the communication of higher storage address.
Fig. 5 B shows an example table, and it deciphers this group among Fig. 5 A and the pin of higher storage address communication, has many different higher storage address functions.
Fig. 6 shows the block schematic diagram of a storage chip, and it has multiple storage array storehouse, one group of pin with low memory address serial communication, and the pin of another group and the communication of higher storage address.
Fig. 7 comprises and has the concise and to the point block schematic diagram with integrated circuit of multiple thesaurus described herein for using the present invention, and it has the addressing mechanism of improvement.
[main element symbol description]
750 integrated circuit
700 storage arrays
701 character lines (row) code translator and novel word-line driver design for pseudo two-port
702 character lines
703 line decoders
704 bit lines
705,707 buses
706 induction amplifiers and data input structure
711 Data In-Lines
715 DOL Data Output Line
708 bias voltage adjustment supply voltage
709 programme, erase and read bias voltage adjusts state machine
Embodiment
Figure 1A shows a storage instruction, and it has the address of a memory access operational code and 3 bytes.Figure 1A shows a basic command and the address input sequence of the storage that for example is serial flash.After this operational code, this address bit is imported 2^24 the address that it represents a byte (2^3 character) data from A23 to A0 in regular turn, to represent the storage storage area of 16 megabits altogether.Therefore, to the storage of a memory capacity greater than 16 megabits, it is not enough that frequency is extracted in this address, and needs more address extraction frequency could handle higher address.
Figure 1B shows a storage instruction, and it has the address of a memory access operational code and 4 bytes.Figure 1B shows the another kind of basic command and the address input sequence of the storage that for example is serial flash.In Figure 1B, have an extra byte, its for address bit A31 to A24.Though the storage instruction among Figure 1B comprises more address bit, and can have bigger memory capacity than the storage instruction among Figure 1A.Yet this extra byte has changed the duration and the sequential of order among Figure 1B.If do not have to revise, the application program of instructing among use Figure 1A just can not be used the instruction among Figure 1B.
Fig. 2 A shows a storage instruction, and it has a memory access operational code and specifies single character access and 1 's address to specify the data (single character) of two bytes.Because a whole character is to carry out access according to this address, eliminate in the address since then 1 potential address, has reduced address incoming frequency and address extraction frequency.
Fig. 2 B shows a storage instruction, and it has the data (double word symbol) that a memory access operational code is specified double word symbol access and 2 address bits appointment nybble.Compared to the single character access of Fig. 2 A, eliminate in the address since then 1 potential address, has reduced address incoming frequency and address extraction frequency, and one extra the 2nd also is eliminated, because this is double word symbol access rather than single character access.
Fig. 2 C shows a storage instruction, and it has a memory access operational code and specifies four character access and 3 address bits to specify the address of this four character.Compared to Fig. 2 A, eliminate in the address since then 1 potential address, has reduced address incoming frequency and address extraction frequency, and extra the 2nd and the 3rd also is eliminated, because this is four character access rather than single character access.
Fig. 3 A shows a storage instruction, and it has a memory access operational code to specify a higher storage address and a single byte address and two unessential bytes to specify this higher storage address part of a complete memory address.
Opposite with Figure 1B, it has revised this memory access order to specify more address bit, and Fig. 3 A has an instruction that separates fully, and it has a diacritic higher storage accessing operation sign indicating number and a higher address, to surmount the normal address input space.Therefore, the user sends two complete input commands intactly to specify a memory address, reaches the access storage array.This higher address order with have different command codes than the low address order with indication higher address and than low address.Yet follow-up access can suppose that the higher address of previous higher address instruction still keeps effectively, to reduce future and have number to an input command of the memory access input command of identical higher address.
Fig. 3 B shows that a storage instruction has a memory access operational code to specify one than low memory address, reaches one 3 byte addresses to specify the low memory address part of a memory address.Though Fig. 3 B and Figure 1A are similar, the memory access instruction among Figure 1A does not rely on a diacritic higher storage address instruction.Different is the higher storage address instruction among the memory access instruction meeting dependency graph 3A among Fig. 3 B.
Fig. 4 shows the block schematic diagram of a storage chip, it has an address decoder and a storage chip outer encoder, so the storage chip outer encoder is encoded into short address with memory address and represents, and code translator address that this is short is represented to utilize in the common store chip operation to revert to long address again to represent in the storage chip.
Hardware among Fig. 4 is implemented in serial input the preceding of storage chip address information is encoded.This hardware coder is encoded into address information according to the specific compression algorithm of this scrambler has the X bit length.Because the X bit length of the address information of this scrambler coding needs less address extraction frequency less than the address before not encoding.Extract frequency in this address, the home address generator of storage chip is delivered in address buffer and the counter with this address decoding of encoding and with the address after this decoding and is manipulated for chip internal.
Fig. 5 A shows the block schematic diagram of a storage chip, and it has multiple storage array storehouse, one group of pin with low memory address serial communication, and the pin of another group and the communication of higher storage address.Fig. 5 B shows an example table, and it deciphers this group among Fig. 5 A and the pin of higher storage address communication, has many different higher storage address functions.
Fig. 5 A and Fig. 5 B utilize the more generally example of address technology, and it utilizes untapped input pin, output connecting pin or I/O (I/O) pin with the indication memory address.What CS0 and CS1 represented array storehouse 0 and array storehouse 1 chooses the input pin.These two array storehouses can be by access continuously, so after the FA final address that arrives array storehouse 0, this internal address counting device skips to first address in the array storehouse 1 of next reading frequency, and subsequently between array storehouse 0 and the array storehouse 1 or comprising between the whole array in array storehouse 0 and array storehouse 1 and circulate, according to the CS[1:0 among Fig. 5 B] setting of choosing the pin combination decides.
Fig. 6 shows that another kind of method comes the address bit of the many A23 of being higher than of addressing initially to be made as " 0 " and if only attempt first 128Mb zone (A24=0) in this row storehouse 0 of access the user.Afterwards, this chip can be counted next address (A24=1) in regular turn after first 128Mb array boundary arrives.
Fig. 7 comprises and has the concise and to the point block schematic diagram with integrated circuit of multiple thesaurus described herein for using the present invention, and it has the addressing mechanism of improvement.
Fig. 7 is the concise and to the point block schematic diagram that comprises the integrated circuit 750 of a storage array 700.One character line (or row) and block are chosen code translator 701 and are coupled to, and with it electrical communication are arranged, and many character lines 702 and character string selection wire are arranged along the column direction of storage array 700 therebetween.One bit line (OK) code translator and driver 703 are coupled to many bit lines of arranging along the row of storage array 700 704, and with it electrical communication are arranged, and with from reading of data, or write data extremely, in the storage unit of storage array 700.The address is to provide to wordline decoders and driver 701 and bit line decoder 703 by bus 705.Induction amplifier in the square 706 and data input structure comprise as reading, programme and the current source of the pattern of erasing, and are to be coupled to bit line decoder 703 by bus 707.Data are sent to the data input structure of square 706 by Data In-Line 711 by the input/output end port on the integrated circuit 750.Data by DOL Data Output Line 715, are sent to I/O end or other integrated circuit 750 interior or outer data destinations on the integrated circuit 750 by the induction amplifier in the square 706.State machine and improvement clock circuit are supplied voltage 708 with the adjustment of control bias voltage in circuit 709.
Storage addressing scheme described herein can be used by revising a serial (SPI) flash memory, and its representative device comprises MX25L12805D and MX25L12845E, and its standard is cited as reference data at this.
Though the present invention is described with reference to embodiment, right the present invention's creation is not subject to its detailed description.Substitute mode and revise pattern and in previous description, advise, and other substitute mode and the modification pattern will be thought by the personage who has the knack of this skill and.Particularly, all have be same as in fact member of the present invention in conjunction with and reach the identical result person in fact with the present invention, neither disengaging spiritual category of the present invention.Therefore, all these substitute modes and revise pattern and be intended to drop on the present invention among appended claims and category that equipollent defined thereof.
Claims (10)
1. a storage integrated circuit is characterized in that, comprises:
The control circuit access should be stored the storage unit in the integrated circuit, and this control circuit is a response instruction, and this instruction comprises:
One first order is with a higher part of indication address bit; And
One second order with the indication address bit one than lower part, the higher part of this address bit this and this constitute a complete access address of this storage integrated circuit than lower part, wherein this first is ordered and this second is ordered and have different command codes.
2. integrated circuit as claimed in claim 1 is characterized in that, this higher part of this address bit is divided many storage unit of one first in this storage integrated circuit of differentiation and one second many storage unit.
3. integrated circuit as claimed in claim 1, it is characterized in that, this storage integrated circuit comprises extra a plurality of storage unit and has extra a plurality of positions, and wherein this address bit should distinguish the specific memory position than the extra a plurality of memory locations of lower part in specific a plurality of storage unit additionally.
4. integrated circuit as claimed in claim 1, it is characterized in that, this storage integrated circuit comprises extra a plurality of storage unit and has extra a plurality of positions, wherein being somebody's turn to do than the extra a plurality of memory locations of lower part in specific a plurality of storage unit additionally of this address bit be distinguished the specific memory position, and
Wherein the higher part of this of this address bit is made differentiation among this more than first storage unit, this more than second storage unit and these extra a plurality of storage unit.
5. integrated circuit as claimed in claim 1, it is characterized in that the memory access instruction differentiation of this higher part of this address bit in this first order after to this first order is that many storage unit of one first in this storage integrated circuit or one second many storage unit are done access action.
6. integrated circuit as claimed in claim 1 is characterized in that, this storage integrated circuit is a serial flash integrated circuit.
7. the method for an access one storage integrated circuit is characterized in that this method comprises:
Store one first order that a higher part of address bit was linked up and indicated to integrated circuit with this;
Link up and indicate one second order than lower part of address bit with this storage integrated circuit, the higher part of this of this address bit and this constitute a complete access address of this storage integrated circuit than lower part, and wherein this first order and this second order have different command codes.
8. method as claimed in claim 7 is characterized in that, this higher part of this address bit is divided many storage unit of one first in this storage integrated circuit of differentiation and one second many storage unit.
9. method as claimed in claim 7, it is characterized in that, this storage integrated circuit comprises extra a plurality of storage unit and has extra a plurality of positions, and wherein this address bit should distinguish the specific memory position than the extra a plurality of memory locations of lower part in specific a plurality of storage unit additionally.
10. method as claimed in claim 7, it is characterized in that, this storage integrated circuit comprises extra a plurality of storage unit and has extra a plurality of positions, wherein being somebody's turn to do than the extra a plurality of memory locations of lower part in specific a plurality of storage unit additionally of this address bit be distinguished the specific memory position, and
Wherein the higher part of this of this address bit is made differentiation among this more than first storage unit, this more than second storage unit and these extra a plurality of storage unit.
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| Application Number | Priority Date | Filing Date | Title |
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| CN200910262645.1A CN102110462B (en) | 2009-12-25 | 2009-12-25 | Addressing one stores the method and apparatus of integrated circuit |
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| CN200910262645.1A CN102110462B (en) | 2009-12-25 | 2009-12-25 | Addressing one stores the method and apparatus of integrated circuit |
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| CN102110462A true CN102110462A (en) | 2011-06-29 |
| CN102110462B CN102110462B (en) | 2015-09-30 |
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Cited By (1)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996409A (en) * | 2013-02-16 | 2014-08-20 | 旺宏电子股份有限公司 | Memory apparatus and method for improving memory reading rate |
Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276873A (en) * | 1988-12-22 | 1994-01-04 | Hughes Aircraft Company | Apparatus and method for generating capture commands for data acquisition |
| CN1427350A (en) * | 2001-12-17 | 2003-07-02 | 群联电子股份有限公司 | Universal serial bus interface quick flash storage integrated circuit |
| CN1674151A (en) * | 2005-03-28 | 2005-09-28 | 北京中星微电子有限公司 | Synchronous dynamic random memory access method to image processing |
| CN1719421A (en) * | 2005-07-28 | 2006-01-11 | 上海大学 | Addressing space extending method of 16M syllable data storage based on MCS-51 structure |
| US20070091679A1 (en) * | 2005-10-20 | 2007-04-26 | Sony Corporation | Storage device, computer system, and data writing method |
| CN101206912A (en) * | 2006-12-22 | 2008-06-25 | 富士通株式会社 | Memory device, memory controller and memory system |
-
2009
- 2009-12-25 CN CN200910262645.1A patent/CN102110462B/en active Active
Patent Citations (6)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276873A (en) * | 1988-12-22 | 1994-01-04 | Hughes Aircraft Company | Apparatus and method for generating capture commands for data acquisition |
| CN1427350A (en) * | 2001-12-17 | 2003-07-02 | 群联电子股份有限公司 | Universal serial bus interface quick flash storage integrated circuit |
| CN1674151A (en) * | 2005-03-28 | 2005-09-28 | 北京中星微电子有限公司 | Synchronous dynamic random memory access method to image processing |
| CN1719421A (en) * | 2005-07-28 | 2006-01-11 | 上海大学 | Addressing space extending method of 16M syllable data storage based on MCS-51 structure |
| US20070091679A1 (en) * | 2005-10-20 | 2007-04-26 | Sony Corporation | Storage device, computer system, and data writing method |
| CN101206912A (en) * | 2006-12-22 | 2008-06-25 | 富士通株式会社 | Memory device, memory controller and memory system |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| CN103996409A (en) * | 2013-02-16 | 2014-08-20 | 旺宏电子股份有限公司 | Memory apparatus and method for improving memory reading rate |
| CN103996409B (en) * | 2013-02-16 | 2016-12-28 | 旺宏电子股份有限公司 | For improving storage arrangement and the method for memorizer reading rate |
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| CN102110462B (en) | 2015-09-30 |
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