CN102110462B - Addressing one stores the method and apparatus of integrated circuit - Google Patents
Addressing one stores the method and apparatus of integrated circuit Download PDFInfo
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- CN102110462B CN102110462B CN200910262645.1A CN200910262645A CN102110462B CN 102110462 B CN102110462 B CN 102110462B CN 200910262645 A CN200910262645 A CN 200910262645A CN 102110462 B CN102110462 B CN 102110462B
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Abstract
The present invention is open a kind of stores integrated circuit, and it has control circuit and accesses storage unit in this storage integrated circuit.This control circuit is response instruction, and this instruction comprises one first order to indicate a higher part of address bit to divide.One second order is to indicate a comparatively lower part of address bit.This higher part of this address bit is divided and should be formed a complete access address of this storage integrated circuit compared with lower part, and wherein this first order and this second order have different command codes.
Description
Technical field
The present invention is such as the technology of the storage of serial flash about addressing in integrated circuit.
Background technology
Serial flash is a kind of kenel of flash memory, and it has a sata standard interface is such as serial peripheral interface (SPI).The carrying out of series of data transfers is according to serial interface standard.Serial line unit so needs less external pins compared to a parallel device with similar memory capacity.For example, about 16,000,000 memory locations of 8 characters in appointment 1 megabit are passed to one 24 memory address ditches, the serial flash meeting serial peripheral interface (SPI) transmits this 24 memory addresss by an output connecting pin serially, instead of parallel through 24 input pins.
Traditional serial flash uses 24 bit address crossfires by input pin to access the maximum storage space reaching 128 megabits.Because the number of address bit limits addressable storage space, when each addressable point stores 8 characters, this address of 24 limits that storage area is maximum only can reach 128 megabits, limits potential application.
But, do not encourage amendment one memory storage to expand the scope of addressable memory space, because so amendment can violate the compatibility that a memory storage and existing sata standard interface standard are such as serial peripheral interface (SPI), or the instruction set to use with an existing product cannot be compatible, can cause and existingly be familiar with common standard or the burden of the user of existing instructions collection.
Summary of the invention
A kind of integrated circuit is provided to store, such as serial flash, new interface, the 128 megabit storage spaces with more traditional serial flash more access storage space ability, and still maintain the ability compatible with the serial peripheral interface (SPI) of existing serial flash interface.
Embodiments of the invention apply many different memory address interfaces for high-density city, and such as serial flash uses.Maintain and the existing ability compared with low capacity storage unit standard interface compatibility, and exceed the restriction that serial flash now uses the addressing capacity of single input pin simultaneously.
An object of the present invention stores integrated circuit for providing a kind of, and it has control circuit and accesses storage unit in this storage integrated circuit.This control circuit is response instruction, and this instruction comprises one first order to indicate a higher part of address bit to divide.One second order is to indicate a comparatively lower part of address bit.This higher part of this address bit is divided and should be formed a complete access address of this storage integrated circuit compared with lower part, and wherein this first order and this second order have different command codes
Another object of the present invention stores the method for integrated circuit for providing a kind of access one, comprises the following step:
Link up with this storage integrated circuit and indicate a higher part of address bit to divide one first to order.
Link up with this storage integrated circuit and indicate one of address bit to order compared with one second of lower part, this higher part of this address bit is divided and should be formed a complete access address of this storage integrated circuit compared with lower part, and wherein this first order and this second order have different command codes.
Other different embodiment is then described below.
Accompanying drawing explanation
The present invention defined by claim.These and other objects, feature, and embodiment, graphic being described of arranging in pairs or groups in the chapters and sections of following embodiments, wherein:
Figure 1A shows a storage instruction, and it has the address of a memory access operational code and 3 bytes.
Figure 1B shows a storage instruction, and it has the address of a memory access operational code and 4 bytes.
Fig. 2 A shows one and stores instruction it has a memory access operational code and specifies single character access, and the address of this single character access is specified in the address of 3 bytes, eliminates and links up the potential address bit of 3 of must use in other cases.
Fig. 2 B shows one and stores instruction it has a memory access operational code and specifies two character access, and the address of this pair of character access is specified in the address of 3 bytes, eliminates and links up the potential address bit of 4 of must use in other cases.
Fig. 2 C shows one and stores instruction it has a memory access operational code and specifies four character access, and the address of this four character access is specified in the address of 3 bytes, eliminates and links up the potential address bit of 5 of must use in other cases.
Fig. 3 A shows one and stores instruction it has a memory access operational code to specify a higher storage address, and a single byte address and two unessential bytes are to specify this higher storage address part of a full storage address.
Fig. 3 B shows a storage instruction, and it has a memory access operational code to specify a lower memory address, and one or three byte addresses are to specify this lower memory address part of a full storage address.
Fig. 4 shows the block schematic diagram of a storage chip, it has an address decoder and a storage chip outer encoder, memory address is encoded into a shorter address and represents by storage chip outer encoder like this, and in storage chip, this shorter address represents to utilize in common store chip to operate and again reverts to longer address and represent by code translator.
Fig. 5 A shows the block schematic diagram of a storage chip, and it has Multiple storage array storehouse, one group with the pin of lower memory address serial communication, and the pin of another group and the communication of higher storage address.
Fig. 5 B shows an example table, and this in Fig. 5 A is organized the pin decoding with the communication of higher storage address by it, has many different higher storage address functions.
Fig. 6 shows the block schematic diagram of a storage chip, and it has Multiple storage array storehouse, one group with the pin of lower memory address serial communication, and the pin of another group and the communication of higher storage address.
Fig. 7 can apply the present invention to comprise and have the concise and to the point block schematic diagram with the integrated circuit in Multiple storage storehouse described herein, and it has the addressing mechanism of improvement.
[main element symbol description]
750 integrated circuit
700 storage arrays
701 character lines (row) code translator and novel word-line driver design for pseudo two-port
702 character lines
703 line decoders
704 bit lines
705,707 buses
706 induction amplifiers and data input structure
711 Data In-Lines
715 DOL Data Output Line
708 bias voltage adjustment supply voltages
709 programme, erase and read bias voltage adjustment state machine
Embodiment
Figure 1A shows a storage instruction, and it has the address of a memory access operational code and 3 bytes.Figure 1A indication example is a basic command of the storage of serial flash and address input sequence in this way.After this operational code, this address bit sequentially inputs 2^24 the address that it represents a byte (2^3 character) data, to represent the storage storage area of 16 megabits altogether from A23 to A0.Therefore, a memory capacity is greater than to the storage of 16 megabits, this address extraction frequency is inadequate, and needs more address extraction frequency could process higher address.
Figure 1B shows a storage instruction, and it has the address of a memory access operational code and 4 bytes.Figure 1B indication example is the another kind of basic command of the storage of serial flash and address input sequence in this way.Have an extra byte in fig. ib, it is address bit A31 to A24.Although the storage instruction in Figure 1B comprises more address bit, and larger memory capacity can be had compared with the storage instruction in Figure 1A.But this extra byte changes duration and the sequential of order in Figure 1B.If do not have amendment, in use Figure 1A, the application program of instruction just can not use the instruction in Figure 1B.
Fig. 2 A shows one and stores instruction it has a memory access operational code and specifies single character access, and the data of two bytes (single character) are specified in the address of 1.Because a whole character accesses according to this address, 1 potential address is eliminated in address since then, decreases address incoming frequency and address extraction frequency.
Fig. 2 B shows a storage instruction, and it has the two character access of a memory access operational code appointment, and 2 address bits specify the data (double word symbol) of nybble.Compared to the single character access of Fig. 2 A, 1 potential address is eliminated in address since then, decreases address incoming frequency and address extraction frequency, and one extra 2nd is also eliminated, because being two character access instead of single character access for this reason.
Fig. 2 C shows one and stores instruction it has a memory access operational code and specifies four character access, and 3 address bits specify the address of this four character.Compared to Fig. 2 A, 1 potential address is eliminated in address since then, and decrease address incoming frequency and address extraction frequency, extra the 2nd and the 3rd is also eliminated, because being four character access instead of single character access for this reason.
Fig. 3 A shows one and stores instruction it has a memory access operational code to specify a higher storage address, and a single byte address and two unessential bytes are to specify this higher storage address part of a full storage address.
Contrary with Figure 1B, it have modified this memory access order to specify more address bit, and Fig. 3 A has an instruction be separated completely, and it has diacritic higher storage accessing operation code and a higher address, to surmount the normal address input space.Therefore, user sends two complete input commands intactly to specify a memory address, and access storage array.This higher address order and lower location order have different command codes to indicate higher address and location lower.But follow-up access can suppose that the higher address of previous higher address instruction still remains effective, there is to reduce future number to input command of the memory access input command of identical higher address.
Fig. 3 B shows a storage instruction and has a memory access operational code to specify a lower memory address, and one 3 byte addresses are to specify the lower memory address part of a memory address.Although Fig. 3 B and Figure 1A is similar, the memory access instruction in Figure 1A does not rely on a diacritic higher storage address instruction.Unlike, the higher storage address instruction in the memory access instruction meeting dependency graph 3A in Fig. 3 B.
Fig. 4 shows the block schematic diagram of a storage chip, it has an address decoder and a storage chip outer encoder, memory address is encoded into a shorter address and represents by storage chip outer encoder like this, and in storage chip, this shorter address represents to utilize in common store chip to operate and again reverts to longer address and represent by code translator.
Address information is encoded by the hardware implementation in Fig. 4 before serial input storage chip.Address information to be encoded into according to the specific compression algorithm of this scrambler by this hardware coder has X bit length.Because of the X bit length of the address information coding of scrambler be for this reason less than uncoded before address, need less address extraction frequency.In this address extraction frequency, the home address generator of storage chip is delivered to by this encoded address decoding and by the address after this decoding in address buffer and counter and is used for chip internal operation.
Fig. 5 A shows the block schematic diagram of a storage chip, and it has Multiple storage array storehouse, one group with the pin of lower memory address serial communication, and the pin of another group and the communication of higher storage address.Fig. 5 B shows an example table, and this in Fig. 5 A is organized the pin decoding with the communication of higher storage address by it, has many different higher storage address functions.
Fig. 5 A and Fig. 5 B is an example utilizing more generally address technology, and it utilizes untapped input pin, output connecting pin or I/O (I/O) pin to indicate memory address.What CS0 and CS1 represented array storehouse 0 and array storehouse 1 chooses input pin.These two array storehouses can be accessed continuously, so after the FA final address arriving array storehouse 0, this internal address counter skips to first address in the array storehouse 1 of next reading frequency, and circulate between array storehouse 0 and array storehouse 1 or comprising between array storehouse 0 and the whole array in array storehouse 1 subsequently, choose the setting of pin combination according to the CS [1:0] in Fig. 5 B and determine.
Fig. 6 shows another kind of method to be carried out the many address bits higher than A23 of addressing and can be initially set to " 0 " and if only attempt user first the 128Mb region (A24=0) accessing this row storehouse 0.Afterwards, this chip can sequentially count next address (A24=1) after first 128Mb array boundary arrives.
Fig. 7 can apply the present invention to comprise and have the concise and to the point block schematic diagram with the integrated circuit in Multiple storage storehouse described herein, and it has the addressing mechanism of improvement.
Fig. 7 is the concise and to the point block schematic diagram of the integrated circuit 750 comprising a storage array 700.One character line (or row) and block are chosen code translator 701 and are coupled to, and have electrical communication with it, and many character lines 702 and character string select line, and the column direction therebetween along storage array 700 arranges.One bit line (OK) code translator and driver 703 are coupled to many bit lines 704 along the row arrangement of storage array 700, and have electrical communication with it, and certainly to read data, or write data extremely, in the storage unit of storage array 700.Address is provided to wordline decoders and driver 701 and bit line decoder 703 by bus 705.Induction amplifier in square 706 and data input structure, comprising the current source as reading, pattern of programming and erase, is be coupled to bit line decoder 703 by bus 707.Data are sent to the data input structure of square 706 by Data In-Line 711 by the input/output end port on integrated circuit 750.Data, by the induction amplifier in square 706, by DOL Data Output Line 715, are sent to the input/output terminal on integrated circuit 750 or the data destination in or beyond other integrated circuit 750.State machine and improvement clock circuit adjust supply voltage 708 to control bias voltage in circuit 709.
Storage addressing scheme described herein can be applied by amendment one serial (SPI) flash memory, and its representative device comprises MX25L12805D and MX25L12845E, and its standard is cited as reference data at this.
Although the present invention is described with reference to embodiment, right the present invention's creation is not limited to its detailed description.Substitute mode and amendment pattern advised in previously describing, and other substitute mode and revise pattern the personage by haveing the knack of this skill is thought and.Particularly, all have be same as in fact component of the present invention combine and reach and the present invention identical result person in fact, neither depart from scope of the present invention.Therefore, these substitute modes all and amendment pattern are intended to drop among the category that the present invention defines in appended claims and equipollent thereof.
Claims (8)
1. store an integrated circuit, it is characterized in that, comprise:
Control circuit accesses the storage unit in this storage integrated circuit, and this control circuit is response instruction, and this instruction comprises:
One first order indicate a higher part of address bit to divide, wherein this higher part of this address bit divide differentiation this storage integrated circuit in one first many storage unit and one second many storage unit; And
One second order is indicate a comparatively lower part of address bit, and this higher part of this address bit is divided and should be formed a complete access address of this storage integrated circuit compared with lower part, wherein this first order and this second order there is different command codes.
2. store integrated circuit as claimed in claim 1, it is characterized in that, this storage integrated circuit comprises extra multiple storage unit, each storage unit has an extra memory location, wherein this address bit should compared with lower part in multiple storage unit that this is extra, from multiple extra memory location, distinguish a specific memory location.
3. store integrated circuit as claimed in claim 1, it is characterized in that, this storage integrated circuit comprises extra multiple storage unit, each storage unit has an extra memory location, wherein this address bit should compared with lower part in multiple storage unit that this is extra, a specific memory location is distinguished from multiple extra memory location, and
Wherein this higher part of this address bit is divided is make differentiation among this more than first storage unit, this more than second storage unit and this extra multiple storage unit.
4. store integrated circuit as claimed in claim 1, it is characterized in that, it is do access action to one first many storage unit in this storage integrated circuit or one second many storage unit that this higher part of this address bit in this first order is divided the memory access instruction differentiation after this first order.
5. store integrated circuit as claimed in claim 1, it is characterized in that, this storage integrated circuit is a serial flash integrated circuit.
6. access the method that stores integrated circuit, it is characterized in that, the method comprises:
One first order is linked up and indicates a higher part of address bit to divide with this storage integrated circuit, and wherein this higher part of this address bit divides one first many storage unit in this storage integrated circuit of differentiation and one second many storage unit;
One second order is linked up with this storage integrated circuit and is indicated a comparatively lower part of address bit, this higher part of this address bit is divided and should be formed a complete access address of this storage integrated circuit compared with lower part, and wherein this first order and this second order have different command codes.
7. method as claimed in claim 6, it is characterized in that, this storage integrated circuit comprises extra multiple storage unit, each storage unit has an extra memory location, wherein this address bit should compared with lower part in multiple storage unit that this is extra, from multiple extra memory location, distinguish a specific memory location.
8. method as claimed in claim 6, it is characterized in that, this storage integrated circuit comprises extra multiple storage unit, each storage unit has an extra memory location, wherein this address bit should compared with lower part in multiple storage unit that this is extra, a specific memory location is distinguished from multiple extra memory location, and
Wherein this higher part of this address bit is divided is make differentiation among this more than first storage unit, this more than second storage unit and this extra multiple storage unit.
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| CN200910262645.1A CN102110462B (en) | 2009-12-25 | 2009-12-25 | Addressing one stores the method and apparatus of integrated circuit |
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| CN200910262645.1A CN102110462B (en) | 2009-12-25 | 2009-12-25 | Addressing one stores the method and apparatus of integrated circuit |
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Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276873A (en) * | 1988-12-22 | 1994-01-04 | Hughes Aircraft Company | Apparatus and method for generating capture commands for data acquisition |
| CN1427350A (en) * | 2001-12-17 | 2003-07-02 | 群联电子股份有限公司 | Universal serial bus interface quick flash storage integrated circuit |
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| CN1674151A (en) * | 2005-03-28 | 2005-09-28 | 北京中星微电子有限公司 | Synchronous dynamic random memory access method to image processing |
| CN100359491C (en) * | 2005-07-28 | 2008-01-02 | 上海大学 | Addressing space extending method of 16M syllable data storage based on MCS-51 structure |
| JP4910360B2 (en) * | 2005-10-20 | 2012-04-04 | ソニー株式会社 | Storage device, computer system, and data writing method |
| JP5018074B2 (en) * | 2006-12-22 | 2012-09-05 | 富士通セミコンダクター株式会社 | Memory device, memory controller and memory system |
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Patent Citations (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US5276873A (en) * | 1988-12-22 | 1994-01-04 | Hughes Aircraft Company | Apparatus and method for generating capture commands for data acquisition |
| CN1427350A (en) * | 2001-12-17 | 2003-07-02 | 群联电子股份有限公司 | Universal serial bus interface quick flash storage integrated circuit |
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