KR20130053791A - Sensing circuitry and sensing method for semiconductor memory - Google Patents

Sensing circuitry and sensing method for semiconductor memory Download PDF

Info

Publication number
KR20130053791A
KR20130053791A KR1020110119437A KR20110119437A KR20130053791A KR 20130053791 A KR20130053791 A KR 20130053791A KR 1020110119437 A KR1020110119437 A KR 1020110119437A KR 20110119437 A KR20110119437 A KR 20110119437A KR 20130053791 A KR20130053791 A KR 20130053791A
Authority
KR
South Korea
Prior art keywords
sense amplifier
global
data line
global sense
decoding
Prior art date
Application number
KR1020110119437A
Other languages
Korean (ko)
Inventor
김성호
권기창
Original Assignee
에스케이하이닉스 주식회사
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by 에스케이하이닉스 주식회사 filed Critical 에스케이하이닉스 주식회사
Priority to KR1020110119437A priority Critical patent/KR20130053791A/en
Publication of KR20130053791A publication Critical patent/KR20130053791A/en

Links

Images

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuits 
    • G11C11/4091—Sense or sense/refresh amplifiers, or associated sense circuitry, e.g. for coupled bit-line precharging, equalising or isolating
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/06—Sense amplifiers; Associated circuits, e.g. timing or triggering circuits
    • G11C7/08—Control thereof
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C2207/00—Indexing scheme relating to arrangements for writing information into, or reading information out from, a digital store
    • G11C2207/22—Control and timing of internal memory operations
    • G11C2207/2227—Standby or low power modes

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Dram (AREA)

Abstract

The present invention relates to a sensing circuit for efficiently detecting binary information stored in a memory cell and a sensing method using the circuit in a semiconductor memory device. The present invention discloses a sensing circuit and a sensing method for compensating for a difference in transfer time for each matrix when data read from a memory cell is first transmitted through a bit line sense amplifier and secondly to a global sense amplifier.

Description

Sensing Circuitry and Sensing Method for Semiconductor Memory

The present invention relates to a sensing circuit for efficiently detecting binary information stored in a memory cell and a sensing method using the circuit in a semiconductor memory device.

With the rapid development of semiconductor technology over the last few decades, the degree of integration of semiconductor memory devices has also increased significantly. Starting with the 1 Kb random access memory (RAM) in the early 1970s, it has recently been mass-produced up to 4 GB Dynamic Random Access Memory (DRAM), resulting in millions of times the number of devices integrated into an integrated circuit. . The increased number of devices inevitably involves an increase in power consumption. However, due to the characteristics of the semiconductor substrate material and the semiconductor package material, such an increase in power cannot be easily accommodated, so that the circuit designer may lower the power supply voltage supplied to the integrated circuit from the outside or the internal power supply voltage lower than the external power supply voltage inside the integrated circuit. I have responded by making a separate. The low internal supply voltage causes the circuit to swing low, greatly reducing dynamic current consumption, which is particularly effective for circuits that drive long data lines. The dynamic current consumption I L of the wiring is proportional to the product of the rate of change of the voltage applied to the wiring (dV / dt) and the capacitive load C L of the wiring, as in Equation (1).

Figure pat00001
--- (One)

Even if the integration degree of the semiconductor memory device is increased, parasitic components such as parasitic resistance or capacitive load due to the increase in the length of the wiring made of metal or polysilicon cannot be reduced. In particular, this problem is exacerbated as the degree of integration of semiconductor memory devices increases. For example, as the integration from 1Gb DRAM to 4Gb DRAM increases, the length of the wiring also increases by four times, so the parasitic component also increases four times in theory. Of course, considering the miniaturization tendency of semiconductor manufacturing technology, parasitic components do not increase by the theoretical multiples. Nevertheless, as the line width becomes smaller, the parasitic capacitance per unit length decreases, but the parasitic resistance per unit length increases. Therefore, the response time of a signal that depends on the time constant that is the product of R and C increases.

If the length of a data line reaches 4000 mu m (microns) in a semiconductor memory device, assuming that the capacitance per unit mu m is 0.001 mW (picofarad), the total capacitance of the data line reaches 4 mW. If the voltage change of the data line reaches 1.2V while 4mA (nanosecond) is one cycle, the dynamic current consumption is 1.2mA (milliampere) by Equation (1). If the data is 32 bits, then the total number of pairs of data lines will be 64, resulting in a total dynamic current consumption of only 32 bits of data line pairs in one cycle at 76.8 ㎃, 64 times 1.2 ㎃. Is reached.

This problem causes other problems. One of them concerns the starting point of the global sense amplifier. Before describing this problem. First, it is necessary to understand the layout and matrix structure of each circuit in the semiconductor memory device. Here, the 'matrix' refers to a memory cell array of a certain size, a word line driver circuit directly connected to the memory cell array and arranged at a pitch of the memory cell array, and a bit line sense amplifier connected to a bit line of the memory cell array. And a column select circuit for selecting the bit line sense amplifier. Some circuit designers may refer to this as 'core' or 'core circuit', but the term 'matrix' is used here for a uniform description.

The global sense amplifier is a circuit that amplifies the data signal once amplified by the sense amplifier connected to the bit line of the memory cell. To distinguish this from the bit line sense amplifier connected to the memory cell array, the bit line sense amplifier may be classified into a primary sense amplifier and a global sense amplifier as a secondary sense amplifier.

Due to the arrangement characteristics of the semiconductor memory device, the global sense amplifiers are usually arranged at the end of the repeated matrix rather than adjacent to each matrix. If the semiconductor memory device 110 is a 4Gb DRAM, when the bank is divided into four banks 111 to 114 as shown in FIG. 1A, the size of each bank becomes 1Gb, so that each bank is divided into 32 separate matrices. If designed, the size of the individual matrix is 32 Mb. If the semiconductor memory device 160 is divided into two banks 161 and 162 as shown in FIG. 1B, the size of each bank is 2Gb and the size of the individual matrix is 64Mb. In either case, the global sense amplifiers 115, 165 are naturally placed at the end of the bank where the repetition of the individual matrix ends, resulting in a circuit layout.

At this time, the data signal starting from the matrix closer to the global sense amplifier arrives at the global sense amplifier 230 earlier than the data signal starting from the far matrix. As a global sense amplifier, even if the data signals originate from the farthest matrix, the voltages of the global data line pairs (LIO and LIOB) must be sufficiently different from each other, so that they can be enabled after having sufficient voltage margin. . Without this margin, sensing errors can be difficult to prevent. Therefore, with a fixed enable point, the data of the nearest matrix has too much time to spare, so the voltages of the global data line pairs (LIO, LIOB) also become excessively different from each other. It consumes unnecessary current for time.

Excessively different voltages on global data line pairs create another problem. The larger the difference voltage, the longer the global data line is precharged. This problem becomes more serious as the operation speed of the semiconductor memory device increases. For example, if the data column clock is 250 MHz, one cycle has a period of 4 ns and the time allowed for precharging is around 2 ns. During this time, the voltages of the global data line pairs must be completely equal to each other during the precharge period. There is no problem in operation. If the voltages in the global data line pairs are so different that they are not completely equal to each other during the precharge period, a data read error may occur in the next cycle. There is a problem that the possibility of such an error is gradually increased due to the operation characteristics of the semiconductor memory device which is gradually accelerated.

Accordingly, an object of the present invention is to provide a method and a circuit for minimizing dynamic current consumed in input / output data lines in a semiconductor memory device.

Another object to be solved by the present invention is to provide a circuit and a method of controlling the circuit in which the operating time of the sense amplifier is interlocked according to the degree of the voltage difference between the input / output data line pairs in the semiconductor memory device.

Another problem to be solved by the present invention is to improve the reliability of the read operation of the semiconductor memory device by controlling the operation time of the sense amplifier.

Another problem to be solved by the present invention is to enable a subject who makes a completed electronic device to be provided with a more reliable semiconductor memory device of the present invention.

According to an aspect of the present invention, there is provided a method of detecting a semiconductor memory device, the method comprising: decoding an address and selectively transferring binary information read from a memory cell to a local data line; Selectively connecting groups belonging to a unit matrix among the local data lines to a global data line, enabling an enabling time of the global sense amplifier according to a physical distance between a global sense amplifier and the unit matrices. Otherwise controlling.

According to another aspect of the present invention, there is provided a sensing circuit of a semiconductor memory device including unit matrixes (MAT) including a memory cell array for storing binary information, and selecting each column of the unit matrix to a local data line. Column select switches 220 for connecting to the data line switches 210 for selectively connecting the local data line and the global data line, a global sense amplifier 230 electrically connected to the global data line, and the global And a control circuit 240 for controlling an enabling point of the global sense amplifier according to the physical distance between the sense amplifier and the unit matrices.

In the case of applying the sensing method and the sensing circuit of the semiconductor memory device proposed by the present invention, there is an advantage of minimizing the dynamic current consumption, and the operation of the sense amplifier is more stabilized, thereby reducing read errors and enabling fast operation. There is also.

Fig. 1A is a block diagram showing the arrangement of a bank structure and a global sense amplifier of a conventional semiconductor memory device.
FIG. 1B is another embodiment of a block diagram showing the arrangement of a bank structure and a global sense amplifier of a conventional semiconductor memory device.
2 illustrates various circuits involved in the data transfer path in the present invention.
3 is an example of a data line precharge circuit of the present invention.
4 is an example of the global sense amplifier of the present invention.
5 shows a data line, a global sense amplifier and a control circuit of the present invention.
6 is a voltage waveform diagram of a global data line when the present invention is applied.
7 is a voltage waveform diagram of a global data line when the present invention is not applied.
8 is a detailed embodiment of a control circuit.
9 is a timing diagram of the control circuit shown in FIG. 8.

In describing the contents of the present invention throughout the specification, the meanings of the terms 'electrically connected', 'connected' and 'connected' between the individual components are not limited to direct connection but also to a certain degree. It includes all the connections made through the intermediate media while maintaining them. The terms "transfer" and "derived" for individual signals include not only direct meanings, but also indirect meanings through intermediate mediators with some degree of signal properties. Other terms such as 'apply', 'apply' and 'input' are also used throughout this specification to mean voltage or signal.

Also, a plurality of representations for each component may be omitted. For example, even a configuration consisting of a plurality of switches or a plurality of signal lines may be expressed as 'switches' or 'signal lines', or may be expressed in the singular as 'switches' or 'signal lines'. This is because the switches may operate complementarily with each other, and sometimes may operate alone, and this may be the case when the signal line is also bundled with several signal lines having the same property, for example, address signals or data signals. This is because there is no need to distinguish between singular and plural. In this respect, this description is valid. Accordingly, similar expressions should be construed in the same sense throughout the specification.

In order to fully understand the operational advantages of the present invention and the objects achieved by the practice of the present invention, reference should be made to the following description of exemplary embodiments of the present invention and the contents described in the accompanying drawings.

Hereinafter, exemplary embodiments of the present invention will be described with reference to the accompanying drawings. First, the various circuits and their connection state of the present invention will be described in brief. Next, the technical ideas applied in the present invention will be described with a specific timing diagram and a truth table.

Schematic description of the invention

FIG. 1A is a block diagram schematically illustrating locations of banks and global sense amplifiers existing in one semiconductor memory chip to illustrate the invention. This block diagram assumes that there are four banks 111, 112, 113, and 114 in one semiconductor memory chip 100. If the chip is a 4Gb (Gigabit) DRAM, each bank contains 1Gb of memory cells. Even in the same 4Gb DRAM, two banks 161 and 162 may be configured as shown in FIG. 1B according to a designer's intention. In this case, each bank is 2 Gb in size. In addition, the bank can be arranged in various forms by changing the position and size of the bank.

FIG. 2 shows one bank 112 in FIG. 1A in detail. The bank 112 is composed of 32 matrices including an array of memory cells. If the size of each bank is 1 Gb, the size of each matrix is 32 Mb. In this figure, not only the memory cell array but also the bit line sense amplifier BLSA, the column switch 220, and the local data lines SIO and SIOB are shown. In FIG. 2, the memory cell array is not shown for convenience of description and the data lines.

In the present invention, the local data lines SIO and SIOB mean a signal line connected to a section between the column switch 220 and the data line switch 210 selecting the bit line, and are generally parallel to the word line of the memory cell. Is placed. In addition, in the present invention, the global data lines LIO and LIOB mean data signal lines between the data line switch 210 and the global sense amplifier 230. For convenience of design, the global data lines LIO and LIOB are generally perpendicular to the local data lines SIO and SIOB. Is placed.

The bit line sense amplifier BLSA is connected to the local data line pairs SIO and SIOB through the column switch 220. The on and off operation of the column switch 220 is controlled by the decoded column address Yi, and as many bit line sense amplifiers as the number of local data lines are selected in one cycle. The decoded column address Yi actually means a signal in which several column addresses are decoded and logically combined. Column addresses retain their original attributes even when decoded. Therefore, there is no difficulty in understanding the features of the present invention even if described as a representative symbol 'Yi' regardless of decoding for convenience of explanation. During one column cycle, only a portion of the column switches 220 are selected according to the decoded and logically combined column address Yi. The number selected is equal to the number of local data line pairs. The local data lines in pairs (SIO, SIOB) means the difference signal a signal is moving in complementary to each other and the total number of these because it is usually having a multiplier of 2 for each matrix was shown in addition to the '2 n' .

The data line switch 210 interconnects the local data lines SIO and SIOB and the global data lines LIO and LIOB. To prevent data collisions, only local data lines belonging to one matrix are connected to global data lines during one cycle. Naturally, the number of global data lines is 2 n , which is equal to the number of local data lines in each matrix. In FIG. 2, only one global data line LIO and LIOB and one global sense amplifier 230 are representatively illustrated to describe the technical idea of the present invention.

Controlling the on and off of the data line switches 210 also involves an address. At this time, the row address is responsible for the job. If the 32 matrices are to be distinguished individually, five row addresses are required.

In the case of SRAM, the local data lines are paired, but in the case of nonvolatile memory such as flash memory, the local data lines may exist in pairs and sometimes alone, depending on the design technique. The same is true for global data lines. The technical idea of the present invention can be applied to any type of memory, and will be described later.

The charge shared data from the memory cell is amplified by the bit line sense amplifier and then selectively connected to the local data lines SIO and SIOB through the column select switches 220. The column selection may be performed sequentially, randomly, or in a plurality of batches according to the use environment of the semiconductor memory device. If multiple bitline sense amplifiers are connected per local data line (usually this), this column selection should be done in one batch per cycle.

The data transferred to the local data lines SIO and SIOB are transferred to the global data lines LIO and LIOB again by selection of the data line switches 210. This selection is also made by address, in which case the row address for selecting each matrix is involved. As shown in FIG. 2, five row addresses are required to individually distinguish each of the 32 matrices. Since how many banks are divided in one semiconductor memory or how many banks are divided into matrices can be changed entirely according to the design of the circuit or the layout of the circuits, It is not relevant to the essential part of the invention.

The data loaded on the global data lines LIO and LIOB are amplified again by the global sense amplifier 230. Before the data line switch 210 is turned on, the global data line is precharged. The precharge is an operation for preforming a global data line with a predetermined voltage, which is performed by the precharge circuit 300 as shown in FIG. 3. The global data line is precharged to the internal power supply voltage VDDi while the first to third switches 310, 320, and 330 are 'turned on' by the precharge signal PRE. Among these, the third switch 330 functions to make the voltages of the global data line pairs LIO and LIOB equal to each other. In the present invention, this function is also included in the precharge operation.

The precharged first and second switches 310 and 320 may be omitted in the circuit designer's choice. In this case, the precharge is performed by the third switch 330 alone which performs the same function. At this time, the pre-autonomous operation is completed because the voltages of the pair of global data lines LIO and LIOB that have moved complementarily to each other in the previous cycle are equal to each other. In some cases, the third switch 330 may be omitted. In either case, it is only necessary that the voltages of the global data line pairs eventually become equal during the precharge period, and the specific configuration of the circuit does not matter.

The precharge operation described above must be completed before the global sense amplifier 230 starts operation, and must also be completed before the data line switches 210 are 'turned on'. If these switches are made of N-channel MOSFETs, the voltage precharged with the internal supply voltage may be a voltage that is reduced by the threshold voltage of the N-channel MOSFET than the internal supply voltage. The switches 310, 320 and 330 related to precharge may use a P-channel MOSFET, or may be implemented in a CMOS form, depending on the circuit designer's choice.

When the data line switch 210 is 'turned on' and a signal GSAEN for enabling the global sense amplifier is transmitted from the control circuit 240, sensing is started. The global sense amplifier 230 may be configured with various types of differential amplifier circuits, an example of which is illustrated in FIG. 4. The input of the global sense amplifier 230 is the global data lines LIO and LIOB connected to the gates of the driving transistors 231 and 232, and the output Vo is connected to the load terminal 234. In this embodiment, the load stage 234 is a CMOS latch, but may be in various forms. For example, a load stage in the form of a current mirror or a diode-connected transistor may be used. The enable signal GSAEN is connected to the gate of the current source transistor 233. In general, since the saturation drain current of the MOS transistor is determined by the ratio of the width and the length of the transistor, circuit designers eventually adjust the size and turn-on time of the current source transistor 233 to determine the operation time and the operation speed of the global sense amplifier. You can control it.

Detailed Description of the Invention

Hereinafter, the technical idea of the present invention will be described in more detail with reference to the circuit diagram of FIG. 5 and the timing diagram of FIG. 6. In the case of the matrix MAT_0 located farthest from the global sense amplifier 230, data is transmitted to the global sense amplifier 230 only after starting from point B and passing through a long transmission line. In contrast, in the case of MAT_31, since the data voltage starts from point A, it is transmitted directly to the global sense amplifier without having to pass through a long transmission line. FIG. 6 compares the case where the matrix MAT_31 closest to the global sense amplifier is selected (indicated by a solid line) and when the matrix MAT_0 in the farthest position is selected (indicated by a dashed line). The matrix has been omitted for convenience of explanation. The technical spirit of the present invention will be easily understood and revealed in more detail by the following additional description.

(When MAT_31 is selected: solid line)

Before t A0 : Global data lines (LIO, LIOB) are precharged with a constant voltage.

t A0 : The column switch 220 belonging to the matrix closest to the global sense amplifier, for example MAT_31 in FIG. 2, is turned on. As soon as it is turned on, the voltages of the global data line pairs (LIO, LIOB) begin to differ from each other by the bitline sense amplifier.

t A1 : The global sense amplifier is enabled after the voltages of the global data line pairs (LIO and LIOB) are somewhat different from each other. The enable point is designed to be the earliest of the 32 matrices.

t A2 : Global sense amplifier completes sensing operation. The sensing operation takes place during t A2 -t A1 . Global data line a sensing operation at the same time and finish (LIO, LIOB) is the pre-charging is started again.

The end of the sensing operation starts at the same time as the enable signal of the global sense amplifier changes to inactive, no matter which matrix is selected. If the global sense amplifier of the type shown in FIG. 4 is used, the enable signal is inactivated to a 'low' state. Although the sensing operation is completed, the voltage sensed by the global sense amplifier using the latch type load stage is maintained while being output as shown in FIG. 4.

t A3 : Completes precharge before the next global data signal voltage is received.

(When MAT_0 is selected: dashed line)

Before t A0 : Global data lines (LIO, LIOB) are precharged with a constant voltage.

t B0 : The column switch 220 belonging to the matrix furthest from the global sense amplifier, eg MAT_0 of FIG. 2, is turned on. Immediately after turn-on, the voltages on the global data line pairs (LIO, LIOB) near MAT_0 begin to differ from each other by the bitline sense amplifiers, but they pass the distance of the 32 matrices and then reach the global sense amplifiers. This pass time is the maximum value and is denoted as t d_MAX .

t B1 : The global sense amplifier is enabled after the voltages of the global data lines LIO and LIOB differ from each other to some extent. The enable time is designed to be the latest of the 32 matrices.

t B2 : The global sense amplifier completes the sensing operation. The sensing operation takes place during t B2 -t B1 . Global data line a sensing operation at the same time and finish (LIO, LIOB) is the pre-charging is started again.

t B3 : Completes precharge before the next sequence of global data signal voltages.

As described above, when the maximum time difference of the delay time at which the global data line voltage reaches the global sense amplifier for each matrix is t d_MAX , the theoretical delay time corresponding to one matrix is t d_MAX / 32. Since the column address Yi also extends from the matrix MAT_31 at one end in the bank to the matrix MAT_0 at the other end, the maximum time difference at the time of selection of the column address Yi according to the position of each matrix also becomes t d_MAX .

Accordingly, the maximum time difference at which the global sense amplifier is enabled is also t d_MAX . Therefore, (t B2 -t B1 ) is equal to (t A2 -t A1 ), and mathematically, it is the area of the inverted triangle of the global data line (LIO, LIOB) having t A1 , t A2 as two vertices in FIG. 6. Is equal to the area of the inverted triangle of the global data lines (LIO, LIOB) with t vertices t B1 and t B2 .

As a result, in the present invention, since the time point at which the voltages of the global data line pairs LIO and LIOB differ from each other is variable according to the position of the matrix, the enable time point and the disable time point of the global sense amplifier are also variable accordingly. . As the global sense amplifiers are disabled, the global data lines begin to be precharged, so the current consumption of the global data lines remains constant for each matrix.

In order to compensate for the delay time of the different data for each matrix, the feature of the present invention is that the enable time of the global sense amplifier 230 is different for each matrix. It is necessary to interlock at least a part of each other.

If the present invention is not applied, the enable timing of the global sense amplifier according to the position of each matrix is fixed. As shown in the timing diagram of FIG. 7 when there is a fixed enable time, the voltage of the global data line pair is earlier than when MAT_0 31 is selected (time t A0 ) or when MAT_0 is selected (time t B0 ). Because of the difference, the differential voltage across the global data line pair is as large as ΔV while the global sense amplifier is enabled. In other words, they are excessively spaced apart by ΔV. This difference means more current consumption.

This phenomenon can also be explained mathematically. In FIG. 7, when MAT_31 is selected , the area of the inverted triangle figure formed by the waveform of the differential voltage of the global data line pair is larger than when MAT_0 having t A0 and t A3 as two vertices is selected. This area difference means the difference in actual current consumption.

If we want to group the 32 matrices in groups of four, we need two row addresses. 8 shows an embodiment of a control circuit 240 having a circuit for decoding two row addresses and a delay circuit. The inputs of the two-to-four decoder 241 are two row addresses A X1 and A X0 , and the four outputs are connected to delay elements 243, 245, 247 and 249, respectively. According to the combination of row addresses, only one of the four outputs of the decoder 241 is active and becomes 'high'. The first output is A X1 A X0 = 00, the second output is A X1 A X0 = 01, and the third output is A X1 A X0 = 10, the fourth output is activated when A X1 A X0 = 11 respectively.

The delay element 243 includes switch transistors M1 and M2 and an inverter I1 (Fig. 8) for connecting delay capacitors C UP and C DOWN to the delay node DLY according to the output signal of the decoder. Each of the delay elements 243, 245, 247, and 249 has delay capacitors C UP and C DOWN of different sizes. The delay capacitor C UP of the delay element 243 corresponding to the first group MAT_0 to MAT7 among 32 matrices divided into four groups (MAT_0 to MAT_7, MAT_8 to MAT15, MAT_16 to MAT23, and MAT_24 to MAT31). The value of C DOWN is the largest and the values of the delay capacitors C UP and C DOWN of the delay elements 249 corresponding to the fourth groups MAT_24 to MAT31 are the smallest.

That is, the capacitance load connected to the delay node DLY varies according to the position of the matrix, and the time taken to charge or discharge the delay node DLY also varies. As a result, the signal delay from the precharge signal PRE to the buffers 242 and 244 until the enable signal GSAEN of the global sense amplifier is activated is different. Which of the four delay elements 243, 245, 247, and 249 is connected to the delay node DLY is determined before the enable point of the global sense amplifier. When the group delay time adjusted by the logical combination of decoding is divided into t d1 to t d4 , the results are summarized as shown in Table 1.

Figure pat00002

These four groups have different enable delay times t d1 to t d4 as shown in FIG. 9. There is no difference in enable latency within one group of eight matrices. The finer separation of latency for each matrix is entirely up to the designer.

The inventors have found that the difference in delay time for each matrix of data line voltage can vary from company to company, but can reach up to 200 ps (picoseconds). If the column cycle time is 4ns (nanoseconds), this delay accounts for about 5% of the cycle time. In this case, dividing the matrix groups into four groups can provide about 1.25% latency for each group, which is appropriate.

This delay, for example, time differences such as t d1 to t d4 can be made in several ways. The RC time constant may be increased by inserting parasitic resistance or parasitic capacitance into the decoder circuit to be included in the control circuit artificially, or the current driving capability may be different by using transistors of different sizes for each decoder. If the technical spirit of the present invention is understood, any method or circuit designer can easily implement it.

As described above, it is a feature of the present invention that the enable timing of the global sense amplifier is variable. Therefore, this technical idea can be applied regardless of the type of memory device.

In the case of DRAM, data is transferred in the order of memory cell-bit line sense amplifier-column switch-local data line, but in case of SRAM, memory cell-column switch-bit line sense amplifier-local data line It only changes. Therefore, the present invention regarding the global sense amplifier and its control can be applied to SRAM without any problem. Such structural differences between DRAM and SRAM are well known to engineers working in this field, and thus detailed descriptions thereof will be omitted.

Even in the case of a nonvolatile memory device such as a flash memory, the core technical idea of the present invention is applied as it is. In the case of a flash memory device, only the structure of the memory cell storing and storing binary information is different, and there is only a difference in the process of selecting a memory cell array, and the rest of the architecture, that is, memory cell-column. The output path of the data from the switch-bitline sense amplifier-local data line is essentially the same as for SRAM. These differences are also well-known facts recognized by engineers working in this field, so further explanations are omitted here.

As described above, the core technical idea of the present invention is to enable or change the global sense amplifier enable time, so that the present invention can be applied to any type of memory device such as MRAM, PRAM, and RRAM. In the case of a semiconductor memory device, the corresponding memory cell array is inevitably divided into multiple matrices, and as the degree of integration increases, the bit line sense amplifier alone is insufficient to drive long data lines, and thus a global sense amplifier is necessary. When reading data from a memory cell, the technical idea of the present invention is always applicable if both a bit line sense amplifier and a global sense amplifier are used.

Although a preferred embodiment of the present invention has been described in detail above, the scope of the present invention is not limited thereto. Based on the basic concept of the invention defined in the following claims can be implemented in more various embodiments, these embodiments also belong to the scope of the invention.

110, 160: semiconductor memory device
111-114, 161, 162: banks 115, 165: global sense amplifiers
210: data line switch 220: column switch
230: global sense amplifier 240: control circuit
300: precharge circuit
t d_MAX : Maximum delay time of global data
t d1 ~ t d4 : Delay time of global data MAT_i: i-th matrix
VDDi: Internal power supply voltage VDD: External power supply voltage
SIO, SIOB: Local data signal pair LIO, LIOB: Global data signal pair
GSAEN: Enable signal of global sense amplifier
Yi: Signal whose column address is decoded PRE: Precharge signal

Claims (17)

In the sensing method of a semiconductor memory device,
Decoding the address;
Selectively transferring binary information read from the memory cell to a local data line;
Selectively connecting groups belonging to a unit matrix among the local data lines to a global data line; And
Controlling an enabling point of the global sense amplifier according to a physical distance between a global sense amplifier and the unit matrices; And a sensing method of a semiconductor memory device. The method of claim 1,
And wherein said step of decoding an address is a step of decoding a row address associated with selection of said unit matrix. The method of claim 1,
Wherein the step of differently controlling the enabling time of the global sense amplifier according to the physical distance between the global sense amplifier and the unit matrices is linked to the result of the step of decoding the address. How to detect the storage device. The method of claim 1,
The controlling of the enabling time of the global sense amplifier according to the physical distance between the global sense amplifier and the unit matrices may be performed by selecting the unit matrix farther from the global sense amplifier as a result of the decoding. A sensing method of a semiconductor memory device, characterized in that the timing of the enable is delayed. The method of claim 1,
And precharging the global data line to a predetermined voltage in advance of the enable time. The method of claim 1,
And wherein the enable time point is coincident with or after the step of selectively connecting groups belonging to a unit matrix among local data lines to a global data line. The method of claim 1,
The enable memory signal GSAEN output in the step of controlling the enabling time of the global sense amplifier differently according to the physical distance between the global sense amplifier and the unit matrix is a pulse signal. Detection method. Unit matrices (MAT) including a memory cell array for storing binary information;
Column select switches for selectively connecting each column of the unit matrix to a local data line;
Data line switches for selectively connecting the local data line and a global data line;
A global sense amplifier electrically connected to the global data line;
A control circuit for controlling an enabling time of the global sense amplifier according to a physical distance between the global sense amplifier and the unit matrices;
A sensing circuit of a semiconductor memory device comprising a. The method of claim 8,
And the control circuit adjusts the enable timing according to the result of decoding the row address. The method of claim 9,
And the result of the decoding results in a later delay of the enable time as the unit matrix farther from the global sense amplifier is selected. The method of claim 8,
And a precharge circuit for precharging the global data line to a predetermined voltage before the enable time. 12. The method of claim 11,
The precharge circuit includes at least one of a first switch and a second switch for charging the global data line to a predetermined voltage, and at least one of a third switch for equalizing the global data line with each other. Sensing circuit of the device. The method of claim 8,
And the output signal of the control circuit is a pulse signal.
The method of claim 8,
And said global sense amplifier has a differential input. The method of claim 8,
And said global sense amplifier comprises a cross-coupled latch. The method of claim 9,
And the control circuit adjusts the enable timing by selectively connecting capacitors having different values to the control circuit according to the decoding result. The method of claim 9,
And the control circuit adjusts the charging and discharging time of any one node in the control circuit according to the decoding result.
KR1020110119437A 2011-11-16 2011-11-16 Sensing circuitry and sensing method for semiconductor memory KR20130053791A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
KR1020110119437A KR20130053791A (en) 2011-11-16 2011-11-16 Sensing circuitry and sensing method for semiconductor memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
KR1020110119437A KR20130053791A (en) 2011-11-16 2011-11-16 Sensing circuitry and sensing method for semiconductor memory

Publications (1)

Publication Number Publication Date
KR20130053791A true KR20130053791A (en) 2013-05-24

Family

ID=48662940

Family Applications (1)

Application Number Title Priority Date Filing Date
KR1020110119437A KR20130053791A (en) 2011-11-16 2011-11-16 Sensing circuitry and sensing method for semiconductor memory

Country Status (1)

Country Link
KR (1) KR20130053791A (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230125437A (en) * 2022-02-21 2023-08-29 (주)피델릭스 Semiconductor memory device for reducing data read time difference among memory banks
CN117809708A (en) * 2024-02-29 2024-04-02 浙江力积存储科技有限公司 Memory array and method for improving data reading accuracy of memory array

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
KR20230125437A (en) * 2022-02-21 2023-08-29 (주)피델릭스 Semiconductor memory device for reducing data read time difference among memory banks
CN117809708A (en) * 2024-02-29 2024-04-02 浙江力积存储科技有限公司 Memory array and method for improving data reading accuracy of memory array
CN117809708B (en) * 2024-02-29 2024-05-07 浙江力积存储科技有限公司 Memory array and method for improving data reading accuracy of memory array

Similar Documents

Publication Publication Date Title
US7633791B2 (en) Read-write circuit for short bit line DRAM
KR100673903B1 (en) Semiconductor memory device having bit line over driving scheme and method for driving bit line sense amplifier thereof
US8547779B2 (en) Memory circuits, systems, and method of interleavng accesses thereof
US5241506A (en) Semiconductor memory circuit apparatus
US8116149B2 (en) Circuit and method for small swing memory signals
US9064556B2 (en) High frequency pseudo dual port memory
CN101937706A (en) Assisting write operations to data storage cells
KR102160562B1 (en) Memory with local-/global bit line architecture and additional capacitance for global bit line discharge in reading
US8779800B2 (en) Control signal generation circuit and sense amplifier circuit using the same
JP2009528635A (en) Apparatus and method for adjusting operating parameters of an integrated circuit
US8358551B2 (en) Reducing peak currents required for precharging data lines in memory devices
US10153007B2 (en) Apparatuses including a memory array with separate global read and write lines and/or sense amplifier region column select line and related methods
US9202538B2 (en) Wordline activation
US20100054066A1 (en) Memory device, semiconductor memory device and control method thereof
US9384790B2 (en) Memory device with separately controlled sense amplifiers
US8854901B2 (en) Read self timing circuitry for self-timed memory
US9589608B2 (en) Semiconductor memory device
IT202100024365A1 (en) PROCEDURE FOR ACCESSING MEMORY CELLS, CORRESPONDING CIRCUIT AND DATA STORAGE DEVICE
US9691499B1 (en) Semiconductor memory device
KR20080043498A (en) Controller and control method of global input/output line
US8854902B2 (en) Write self timing circuitry for self-timed memory
US8432757B2 (en) Semiconductor system and method for operating the same
KR20130053791A (en) Sensing circuitry and sensing method for semiconductor memory
US6166977A (en) Address controlled sense amplifier overdrive timing for semiconductor memory device
US9076501B2 (en) Apparatuses and methods for reducing current leakage in a memory

Legal Events

Date Code Title Description
A201 Request for examination
E902 Notification of reason for refusal
E601 Decision to refuse application