KR100634330B1 - Method for reading a structural phase-change memory - Google Patents

Abstract

The cells of the structural phase change memory are programmed by raising the cell voltage and the cell current to the programming threshold level and lowering them to the stop level below their programming level. Then, a precharge pulse is applied which raises the bit line voltage of the selected cell and does not raise the cell voltage and cell current to their programming level. The cell current is then raised to a read level below the programming threshold level, and the bit line voltage is compared with the reference voltage while the cell current is at the read level.

Description

METHOD FOR READING A STRUCTURAL PHASE-CHANGE MEMORY}             

The present invention relates to a read operation applied to reading a solid state memory device of a phase change material.

Solid state memory devices using structural phase change materials as data storage mechanisms (hereafter simply phase change memories) offer significant advantages in terms of cost and performance over conventional charge storage based memories. The phase change memory consists of a cell array, each cell having several structural phase change materials to store cell data. Such materials may be, for example, chalcogen alloys that exhibit a reversible structural phase change from amorphous to crystalline. A small volume of chalcogenide alloy is integrated in the circuit that allows the cell to act as a fast switching programmable resistor. This programmable resistance represents at least 40 times the dynamic range of the resistivity between a relatively crystalline phase (low resistivity) and a relatively amorphous phase (high resistivity). Data stored in a cell is read by measuring the resistance of the cell. Chalcogen alloy cells are also nonvolatile.

Phase-change memory cells can be written and read by programming, i.e., applying current pulses that have the appropriate size and duration and generate the required voltages and currents throughout the volume of phase change material in the cell. The selected cell in the structural phase change memory can be programmed to one selected state by raising the cell voltage and cell current for the selected cell to a programming threshold level characteristic of the phase change material in the cell. The voltage and current can then drop down to a stop level (eg, substantially zero voltage and current) below their programming threshold level. This process can be performed, for example, by the application of a reset pulse and a set pulse that can program the cell to two different logic states. In both of these pulses, the cell voltage and cell current are raised by at least the specific threshold voltage and current levels needed to program the cell. Next, to read the programming cell, a read pulse can be applied to measure the relative change in cell material. Thus, typically, read pulses provide a significantly smaller amount of cell current and cell voltage than reset pulses or set pulses.

The invention is illustrated by way of example and not by way of limitation in the figures of the accompanying drawings in which like reference characters indicate similar elements. It is to be understood that the "one" embodiment herein is not necessarily the same embodiment and means at least one.

1 is a block diagram of a portion of an integrated circuit featuring a coupled controlled phase change memory array in accordance with one embodiment of the present invention;

2 illustrates current voltage characteristics of an exemplary phase change memory cell;

3 is an exemplary timing diagram for various signals associated with a cell being programmed and read in accordance with one embodiment of the present invention;

4 is a schematic circuit diagram of one embodiment of a pulse generation and drive circuit coupled to a bit line of a phase change memory array;

5 is a flow diagram of one embodiment of a method of operating a structural phase change memory cell, in accordance with one embodiment of the present invention;

6 is a block diagram of a portable electronic device implementing a phase change memory IC capable of performing a read operation in accordance with one embodiment of the present invention.

In a relatively large phase change memory array, the present inventors have noted that the above-described read operation, before raising the cell current to the read level, does not raise the cell voltage and the cell current to their programming threshold level without raising the bit line voltage of the selected cell. It has been found that by applying a precharge pulse that raises the voltage, it can be done at a higher speed. The bit line voltage used to obtain a measurement of the cell voltage (and the relative resistance of the material in the cell) becomes available faster in time when using precharge pulses. This is because, depending on how large the memory cell is, a bit line that can exhibit a significantly larger capacity than the read current can be charged to a sufficiently high voltage level by a precharge pulse of relatively short duration, where With a sufficiently high voltage level, the bit line voltage can deploy the measurement of the cell voltage very quickly, despite the relatively small read current.

Another advantage of using precharge pulses is seen in certain embodiments where the cell current is controlled independently of the precharge pulse. This allows the read operation to successfully see changes in the structural and electrical behavior of the cells in the array by selecting the appropriate error margin of the read current level.

With reference to FIG. 1, shown is a block diagram illustrating a portion of an integrated circuit (IC) featuring a phase change memory array 104 coupled to be controlled by timing logic, pulse generation, and drive circuit 130. . Circuit 130 may perform programming and reading operations on array 104 in accordance with various embodiments described above. Starting with the array 104 first, a plurality of vertically oriented conductive lines 112_1, 112_2,... (Referred to as bit lines) and a plurality of horizontally oriented conductive lines 108_1, 108_2,. (Called a word line) can be built on the semiconductor IC die in a matrix structure of intersections, as shown. Each intersection of the bit line-word line pairs is associated with an individual memory cell 114. In order to achieve a large volume at a low manufacturing cost, all the memory cells 114 of the array 104 can be designed to have the same structure.

Each memory cell 114 has one volume of structural phase change material 118 coupled between the bit line 112 and individual bit line-word line pairs of the word line 108. The volume of phase change material 118 functions to store information about the cell in accordance with the programmed resistivity. Access to each cell 114 in the embodiment of FIG. 1 is made through a corresponding bit line-word line pair, and is isolated from other circuits in each cell, namely the parasitic PNP bipolar transistor 124. It is possible through the device. The word line of the selected cell, in this case word line 108_2, is connected to the base of transistor 124, and bit line 112_2 of cell 114 is connected to the other side of the volume of phase change material 118. do. In this embodiment, the volume of the phase change material 118 is in series with the emitter of the transistor 124, and the collector of the transistor 124 is not only the timing logic of the IC, the pulse generation and driving circuit 130, It is connected to a power return node that may be common to all memory cells of the array 104. Connected transistor 124 as shown in Figure 1 acts as a solid state switch under the control of the word line signal received at the base. Other configurations are also possible that selectively block the cell current through the phase change material 118, such as using discrete switching field effect transistors. Resistor 120 may also be provided for heating and / or current limiting purposes in series with the volume of phase change material 118.

The cell current may be defined as the current passing through the volume of phase change material 118, which in this embodiment is the bit line current. The cell current in this embodiment is equal to the emitter current of transistor 124. On the one hand, the cell voltage may be defined very loosely as any voltage for the cell 114 that includes the voltage across the volume of the phase change material 118.                 

Referring also to FIG. 1, the timing logic, pulse generation and driving circuit 130 includes a number of input and output ports, each coupled to a respective bit line 112 and word line 108 of the array 104. Equipped. These ports are driven to appropriate signal levels and timings so that one or more selected cells can be programmed and read as shown below. Conventional drive circuits, such as switching transistors, can be used with pulse generation circuits to achieve desired waveforms on signals driven by bit lines and word lines. Timing logic can also be implemented using conventional components, including, for example, counters that apply the necessary timing with greater accuracy and speed in programming and reading operations. Timing logic may respond to input requests received via address line 134 and data line 138. This requirement should, for example, be able to write a single bit or multiple bits of data values in one or more cells in the array 104. Thus, the circuit 130 converts the address and data information received on the address and data line into a bit line-word line pair of the array 104 that must be driven in response to the requested data and address. It is understood to include the necessary decoding logic of. Circuit 130 may be formed on the same IC die as array 104.

Although described with reference to a single selected or target memory cell being programmed and read, it should be appreciated that the concept of programming and simultaneously reading multiple memory cells is applicable. For example, depending on the write request received by the circuit 130, multiple memory cells in the same row of the array and coupled to the same word line 108 (each memory cell to a different bit line 112). Coupled) can be programmed or read simultaneously.

When cell 114 is selected to be programmed or read, an appropriate pulse is applied to the word line-bit line pair of that selected cell. Thus, when the cell 114 shown in FIG. 1 is selected to be programmed or read, the potential on the bit line 112_2 rises above the potential of the power return node, and the potential on the word line 108_2 causes the base drive to drive the transistor ( 124) (eg, to the potential of the power return node). It can also increase the emitter current to a level that is allowed by the pulses. The voltage and current level that may be applied to the selected cell for programming and reading may vary depending on the cell's current-voltage (ie, I-V) characteristics.

2 illustrates an exemplary set of memory cell I-V characteristics. The figures are annotated to show the various voltage and current levels that may be required during the programming and reading of phase change memory cells. The change in cell current is represented as a function of cell voltage for different memory cell states. For example, one should know the difference between trace 204 and trace 210. Trace 204 corresponds to the I-V characteristic of the cell in the set state. In this state, the phase change material of the cell is quite crystalline and therefore exhibits low resistance versus current. In contrast, when the cell is in the reset state, the phase change material is quite amorphous and thus exhibits relatively high resistance to current. Operation of the cell in the reset state is given by trace 210. In one embodiment, the cell may be placed in an intermediate state, such as a state in which the phase change material corresponds to a trace 206 having a structure that is highly crystalline or highly amorphous.

When the cell current rises above the threshold I _th , the material in the cell will be affected by the phase change. The threshold currents and voltage ranges shown and illustrated in FIG. 2 are examples referred to herein as programming threshold levels. However, in order to actually program the cell to any given state, it should be noted that the cell current must be further increased to the level shown in the figure with the trace 208 being essentially vertical. Trace 208 represents the dynamic operation of a cell whose state can be programmed to a set state, a reset state or an intermediate state, depending on the level of cell current reached and the shape and duration of the cell current pulse.

According to one embodiment, the read current range is between 0 and I _th . Since it is desirable to read the cell without changing its state, the read level should not be taken above I _th .

Referring to FIG. 3, an exemplary set of timing diagrams illustrating various waveforms associated with programming and reading phase change memory cells is shown. Six sets of waveforms are shown, where they represent phase change material temperature, cell voltage, cell current, word line voltage, bit line voltage, and precharge (ie, PC) control signals. The precharge control signal increases the bit line voltage of one selected cell (raises the cell voltage and cell current to the programming threshold level) before raising the cell current to its read level, in accordance with various embodiments described herein. Can be used to apply a precharge pulse.

3 may be depicted as including three columns, where the first column represents a reset operation that can be executed on a cell, the second column represents a set operation, and the third column is an embodiment of a read operation. Indicates. Reset and set operations may be generic and will be briefly described herein. Between programming or other operations, any unselected word line is raised to a relatively high voltage, eg, V _cc , in this embodiment, and the unselected bit line is a relatively low voltage, eg, 0 or ground state. It should be noted that Thus, referring again to FIG. 1, this means that in an unselected word line at V _cc and an unselected bit line in ground state, transistor 124 can cause the cell current to be minimal in the cutoff mode. have.

In order to reset the cell, the temperature of the phase change material must reach a certain level and maintain that level for any period of time. Thus, in the embodiment shown in FIG. 3, the cell is applied by applying a voltage pulse between the bit line and the word line of the cell such that the cell current rises to any given level and stays at that level at any time interval T _reset . It is reset. The two waveforms shown and marked, SET and RESET, refer to the operation of current or voltage (when present) if the cell was in the set or reset state, respectively. Thus, referring to the first column (write zero or reset operation), if the cell being written is already in the reset state, current and voltage operate as indicated by the RESET terminology. On the other hand, if the cell being programmed is currently in the set state, the operation of the voltage and current is given by the waveform indicated by SET. To end programming the cell in the reset state, the temperature of the phase change material in the cell is drastically lowered as defined by the extinction time shown in the figure. This decay time can be obtained by drastically reducing the cell current within the interval T _{reset fall} as shown. Thereafter, the cell voltage and current fall to the stop level, which is zero volts and zero current in this embodiment. The zero voltage and zero current at the stop level help to maintain the programmed state of the cell and also reduce power consumption.

With reference to FIG. 3, the second column shows the waveform generated during an exemplary write operation in which the cell is programmed to a set state. If the cell is currently in a reset state and a set operation has been performed, the waveform marked RESET in the second column is the waveform that can be represented by the memory cell. In order to set the cell, the temperature of the phase change material is maintained during the crystal growth interval satisfied by the time interval T _set of the set pulses. Again, after the cell is programmed, the cell is not selected by raising its word line voltage to V _cc and grounding the bit line voltage.

Referring to the third column of FIG. 3, an embodiment of a read operation including a precharge pulse is shown. The application of the precharge pulse is demonstrated by an active low pulse of the precharge control signal indicated by the waveform at the bottom of FIG. 3. In the illustrated embodiment, precharge pulses are initiated and the bit line-word line pairs are not at their stop level, i.e. Specific circuit implementations for executing precharge pulses will be illustrated and described in conjunction with FIG. 4. It should now be fully understood that the precharge pulses do not raise the cell voltage and cell current to their programming threshold level, but rather raise the bit line voltage of the selected cell shown in the bit line voltage waveform of FIG.

In the embodiment shown in Fig. 3, the change in cell voltage and cell current during the precharge pulse is considered to be considerably small with respect to the increase in the bit line voltage. This is due to the precharge voltage dropping significantly across the isolation device, particularly across the emitter base terminal of transistor 124 (see FIG. 1).

According to one embodiment, the end of the precharge pulse may be loosely defined at the time point after the bit line voltage reaches a predefined level below the stop level. Various levels of precharge voltage may be used as long as they help to reduce the time period needed to subsequently obtain a bit line voltage representing a measurement of the cell data state for read purposes. For example, the peak level of the precharge pulse voltage on the bit line may be in the range of 0.5 volts to 1.5 volts for a memory cell with a typical phase change material such as Ge ₂ Sb ₂ Te ₅ .

The precharge pulse is immediately followed, raising the cell current to a read level below the programming threshold level, and also comparing the bit line voltage obtained while the current is at the read level to the reference voltage. Depending on the state of the memory cell being read, the cell voltage may be different, and if the cell is in a reset state where the phase change material has a relatively high resistance, the bit line voltage obtained while the current is at the read level is determined by the cell. Larger than when it was in the set state. This can be seen from the waveform of the V _bitline in FIG. In addition, due to the different resistance provided by the phase change material in the set state and in the reset state, the read level of the cell current may be different as shown in the figure, unless the read current is supplied by the constant current source. Alternatively, a constant current source can be used to provide a fixed read current level for both set and reset conditions.

Exemplary magnitudes of current pulses for setting up a memory cell can be between 50 microamps and 650 microamps for a memory cell with a typical phase change material such as Ge ₂ Sb ₂ Te ₅ . In contrast, the magnitude of the reset current pulse described above for the same cell may range from 100 microamps to 3 milliamps. Appropriate read levels for the current of a typical memory cell can be between 5 microamps and 100 microamps. These levels may be applicable to phase change materials that provide low resistance in the range of 1 kiloohm to 10 kiloohms and high resistance in the range of more than 100 kiloohms. The time interval required to maintain cell current at the read level can be relatively short, such as in the range of 5 to 30 nanoseconds. The precharge pulse may be shorter in duration. The read time interval also depends on the time required to develop a sufficiently large voltage difference between the reference voltage and the bit line voltage, which can be compared by, for example, a sense amplifier. An example circuit implementation of the sense amplifier will be given below in conjunction with FIG. 4. These trend values are technology and device dependent and may also vary depending on the particular manufacturing process.

Referring to FIG. 4, a schematic circuit of one embodiment of a pulse generation and drive circuit coupled to bit lines 112_1 and 112_2 of a phase change memory array is shown. This circuit implementation uses metal oxide semiconductor field effect transistors entirely, although other types of transistors may alternatively be used, depending on the fabrication process. The description below focuses on transistors 410-422 coupled through bit line 112_2 and word line 108_2 to program and read selected cells 114. For other bit lines in the array, the same circuit implementation can be repeated. Although the timing logic used to control the transistors of the pulse generation and drive circuits and the control signals or word lines are not shown, the design of such circuits, in conjunction with the exemplary timing diagram of FIG. It can be easily accomplished by those skilled in the art.

It can be seen that cell 114 is partially controlled by a signal applied to word line 108_2. Assuming cell 114 has been selected to be programmed or read, the potential on word line 108_2 is lowered to a level low enough to allow a PNP transistor inside the selected cell 114 to conduct cell current. In this embodiment, the cell current is equal to the bit line current provided by one of the transistors 419-422. Transistor 419 via the digital SET control signal is used to generate one set programming current pulse. In the same way, transistor 420 is used to generate a reset programming current pulse in response to the digital RESET control signal. Similarly, precharge pulses are generated using transistor 421 under the control of a digital PRECHARGE control signal. Finally, the cell current is raised to the read level using transistor 422 under the control of the digital READ control signal. In the illustrated embodiment, the set, reset, and read current pulses provided to the selected cells 114 have a constant magnitude (ie, rectangular). Alternatively, the pulse may not be rectangular in shape if it achieves the desired programming or reading result.

Sensing the resistance of the phase change material, which is the purpose of the read operation, can be accomplished in the embodiment shown in FIG. 4, using a sense amplifier comprised of transistors 410-418. The sense amplifier provides a measure of resistance by comparing the voltage on bit line 112_2 with an external reference voltage. Input to the sense amplifier is controlled by the isolation transistor 416 with respect to the bit line voltage and by isolation transistor 415 with respect to the reference voltage. In this embodiment of the sense amplifier, the output of the sense amplifier is the single terminal voltage V _out gated by transistor 417. Transistors 410 and 413 form cross-coupled p-channel pairs, and n-channel transistors 412 and 414 also form cross-coupled pairs. As shown, the coupled cross-coupled transistor pair quickly indicates that the input voltage is greater than the common power supply return voltage (in this case, ground), thereby providing two input signals (here the bit line voltage and the reference voltage). Form a regeneration circuit that can determine the difference between To help conserve power, a switching pull-up transistor 418 under the control of the digital ACTIVE PULL UP control signal is provided to effectively shut down the sense amplifier when the voltage on the bit line 112_2 is not read.

One embodiment of a read process using the pulse generation and drive circuit shown in FIG. 4 is described. The read operation begins by selecting one or more cells to read. In one embodiment, the selected cells may be in the same row. In that case, the voltage on the word line corresponding to all deselected rows of memory cells rises to V _cc , and the word line for the selected row is grounded. In FIG. 4, the selected row includes the selected cell 114 connected to the word line 108_2. The bit line 112 from which the selected column is read is precharged with the voltage V _pc . In the embodiment of FIG. 4, this is accomplished by turning on transistor 421. During the precharge pulse, i.e., while the transistor 421 is turned on, the isolation transistors 415 and 416 of the sense amplifier can be turned on. Note that the sense amplifier itself is not yet active at that time (ie, transistor 418 remains cutoff). Transistor 421 is then turned off, thereby terminating the precharge pulse, and then transistor 422 is turned on to provide a read current to bit line 112_2. After a delay sufficient to develop the minimum difference between the bit line voltage provided to the sense amplifier and the external reference voltage (where the minimum difference depends on the sensitivity of the sense amplifier), the isolation transistors 415 and 416 are turned off. , The sense amplifier is activated (ie, by turning on transistor 418). After sufficient amplification by the sense amplifier, a digital value V _out is provided that represents one of two states (eg, set and reset) in the selected cell by turning on the gate transistor 417. When the isolation transistors 415 and 416 are turned off, the bit line 112_2 can fall back to ground voltage to prepare for the next read or programming cycle.

Thus, by combining the precharge operation with a current mode readout, it is not necessary to wait for the bitline to be charged from the stop level (here, ground) with the relatively small readout current provided by the transistor 422, which leads to faster performance. Read operation is possible. It should be noted that this read current should be considerably smaller, preferably less than the threshold current I _th , in order to obtain proper reading results and to avoid changing the phase of the structural phase change material in the selected cell 114. Nevertheless, the read current can be adjusted, for example based on the position of the selected cell being read. This allows for an adjustable margin for reading cells that may indicate a change in their electrical operation.

Although the above-described reading process is based on the schematic circuit of FIG. 4 showing the selected cell 114 with the isolation device coupled between the phase change material and the power return node (in this case ground), the memory cell. A similar process can be applied to the phase change memory array in which the isolation transistors within are coupled to the power supply node rather than the power return node. In this embodiment, the cell current flowing in the volume of phase change material can be supplied from a power supply node and enter the power return node (ground, etc.) by a number of pulse generating transistors. This embodiment can be viewed as a donated version of the embodiment of FIG. 4. In addition, although the cell voltage of the embodiment shown in FIGS. 1 and 4 is single terminal with respect to the power return node voltage (here, 0 volts), the cell voltage is measured between the corresponding bit line-word line pairs of the cell. Other embodiments may include circuitry that may be enabled. In this other embodiment, the cell voltage may take into account the differential voltage measured between the corresponding bit line-word line pair of the selected cell.

In the embodiment of FIG. 4 showing a sense amplifier having a first input receiving bit line voltage and a second input receiving external reference voltage, it should be noted that the cell is expected to store a single bit. However, for cells capable of storing multiple bits of information, for example by enabling one or more intermediate states between the set and reset states (see FIG. 2), a comparator circuit having multiple reference levels is a multi-bit cell. It may be necessary to determine the state of the system.

5, a flow diagram of one embodiment of a method of operating a structural phase change memory cell is shown. Operation begins programming the selected cell in the selected state in operation 504 by raising the cell voltage and cell current of the cell to the programming threshold level (operation 504). The voltage and current are then lowered to a stop level below their programming threshold level. The level may be as described above in conjunction with FIG. 2, which illustrates exemplary memory cell I-V characteristics. Operation then proceeds with the application of a precharge pulse (operation 508). This pulse raises the bit line voltage of the selected cell but does not raise the cell voltage and cell current to their programming threshold level. Thus, the precharge pulse is a relatively short current pulse that can be seen to serve to charge the selected bit line to a level that is expected to occur when the read current subsequently passes through the bit line.

After application of the precharge pulse, the cell current is immediately raised to the read level, and the read level is below the programming threshold level so as not to change the state of the selected cell (operation 512). Next, to determine the state of the selected cell, the bit line voltage is compared with the reference voltage and the cell current is at the read level (operation 516). Using precharge pulses before raising the cell current to the read level may also be applicable to multibit cell embodiments.

Referring to FIG. 6, shown is a block diagram of a portable electronic device 604 that implements a phase change memory storage subsystem 608 with the ability to perform the above-described read operations. Storage system 608 may be operated in accordance with embodiments of the readout process described above. Storage system 608 may include one or more integrated circuit die with memory arrays in which each die is programmed and read in accordance with the embodiments described above in FIGS. 1-5. These IC dies may be separate standalone memory devices that are aligned within modules, such as conventional dynamic random access memory (DRAM) modules, which may be integrated with other on-chip functions such as an I / O processor or part of a microcontroller. have.

Application 604 may be, for example, a portable notebook computer, a digital still and / or video camera, a personal digital assistant, or a mobile (cellular) portable telephone device. In both of these applications, a processor 610 and a storage system 608 that is used as a program memory to store code and data for execution by the processor are operatively installed on the board. The portable application 604 communicates with another device, such as a personal computer or computer network, via the I / O interface 614. This I / O interface 614 may provide access to a computer peripheral bus, a high speed digital communication transmission line, or an antenna for unguided transmission. Communication between the processor and storage system 608 and communication between the processor and I / O interface 614 may be accomplished using conventional computer bus architectures.

The above-described components of the portable application 604 are powered by the battery 618 via the power supply bus 616. Because application 604 is a general battery powered, its functional components, including storage system 608, must be designed to provide the desired performance at low power consumption levels. In addition, due to the limited size of the portable application, the components shown in FIG. 6 may provide relatively high density of functionality. Of course, there are non-portable applications of storage system 608 that are not shown. These include large network servers or other computing devices that may benefit from nonvolatile memory devices, such as, for example, phase change memory.

In summary, several embodiments of methods and apparatus for reading structural phase change memory have been described. In the foregoing specification, the invention has been described with reference to specific examples. However, as described in the appended claims, it will be apparent that various modifications and changes may be made thereto without departing from the broader spirit and scope of the invention. Accordingly, the specification and drawings are to be regarded in an illustrative rather than a restrictive sense.

Claims (16)

A method of operating a structural phase change memory cell, For a selected cell in a structural phase change memory, the selected cell is raised by raising the cell voltage and cell current of the selected cell to a programming threshold level, and then lowering the voltage and current to a stop level below their programming threshold level. Programming the cell into one selected state, Applying a precharge pulse that raises the bit line voltage of the selected cell but does not raise the cell voltage and cell current to its programming threshold level; Raising the cell current to a read level below the programming threshold level and comparing the bit line voltage to a reference voltage while the current is at the read level. Method of operating a structural phase change memory cell comprising a. The method of claim 1, And said stop level is essentially at zero volts. The method of claim 1, While applying the precharge pulse, further comprising isolating an input of a sense amplifier from the bit line voltage for a predetermined time interval and placing the input under the influence of the bit line voltage, wherein the bit line voltage and the The comparison of reference voltages is a method of operating a structural phase change memory cell in which an output bit value is performed by a sense amplifier in which said comparison result is obtained. The method of claim 1, And wherein said cell voltage is a single terminal with respect to a power return node voltage. A plurality of bit lines and a plurality of word lines, Each memory cell having a volume of structural phase change material coupled between the plurality of bit lines and individual bit line-word line pairs of the plurality of word lines to store information about the cell; The pair is selected when reading the cell; and, Coupled to the plurality of bit lines and the plurality of word lines to raise one selected cell to raise the cell voltage and cell current of the selected cell to a programming threshold level and to stop the voltage and current below their programming threshold level. Dropping to a level, applying a precharge pulse to raise the bit line voltage of the selected cell and not raising the cell voltage and cell current to their programming threshold level, and bringing the cell current to a reading level below the programming threshold level. Timing logic, pulse generation, and drive circuitry to program one selected state by raising and comparing the bit line voltage obtained while the current is at the read level with a reference voltage Integrated circuit comprising a. The method of claim 5, wherein The stop level is essentially at zero volts. The method of claim 5, And a sense amplifier having an input coupled to a bit line of the selected cell. The method of claim 5, The cell voltage is a single terminal with respect to a power return node voltage. A portable electronic device having a printed circuit board operatively installed with a processor and a storage subsystem, and a battery for powering the printed circuit board, wherein the storage subsystem includes a plurality of bit lines and a plurality of word lines. And each memory cell has a volume of structural phase change material coupled between the plurality of bit lines and individual bit line-word line pairs of the plurality of word lines to store information about the cell. A memory cell, wherein the pair is selected when reading the cell, and coupled to the plurality of bit lines and the plurality of word lines to select one selected cell for programming the cell voltage and cell current of the selected cell to a threshold level. Up to the voltage and current down to a stop level below their programming threshold level and a precharge pulse To increase the bit line voltage of the selected cell and not raise the cell voltage and cell current to their programming threshold level, raise the cell current to a read level below the programming threshold level and allow the current to be at the read level. And an integrated circuit having timing logic, pulse generation, and driving circuitry to program one selected state by comparing the bit line voltage obtained during the comparison with a reference voltage. The method of claim 9, The stop level is essentially at zero volts. The method of claim 9, The integrated circuit further comprising a sense amplifier having an input coupled to a bit line of the selected cell. The method of claim 9, The cell voltage is a single terminal relative to a power return node voltage. delete delete delete delete

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