EP3507831A4 - Memory cells and memory arrays - Google Patents

Memory cells and memory arrays Download PDF

Info

Publication number
EP3507831A4
EP3507831A4 EP17847158.7A EP17847158A EP3507831A4 EP 3507831 A4 EP3507831 A4 EP 3507831A4 EP 17847158 A EP17847158 A EP 17847158A EP 3507831 A4 EP3507831 A4 EP 3507831A4
Authority
EP
European Patent Office
Prior art keywords
memory
arrays
cells
memory cells
memory arrays
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP17847158.7A
Other languages
German (de)
French (fr)
Other versions
EP3507831B1 (en
EP3507831A1 (en
Inventor
Gloria YANG
Suraj J. Mathew
Raghunath Singanamalla
Vinay Nair
Scott J. Derner
Michael Amiel SHORE
Brent Keeth
Fatma Arzum Simsek-Ege
Diem Thy N. TRAN
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Micron Technology Inc
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Priority to EP21153826.9A priority Critical patent/EP3840046A1/en
Publication of EP3507831A1 publication Critical patent/EP3507831A1/en
Publication of EP3507831A4 publication Critical patent/EP3507831A4/en
Application granted granted Critical
Publication of EP3507831B1 publication Critical patent/EP3507831B1/en
Active legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Classifications

    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/30—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells
    • H10B12/37—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate
    • H10B12/377—DRAM devices comprising one-transistor - one-capacitor [1T-1C] memory cells the capacitor being at least partially in a trench in the substrate having a storage electrode extension located over the transistor
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L28/00—Passive two-terminal components without a potential-jump or surface barrier for integrated circuits; Details thereof; Multistep manufacturing processes therefor
    • H01L28/40—Capacitors
    • H01L28/60—Electrodes
    • H01L28/82—Electrodes with an enlarged surface, e.g. formed by texturisation
    • H01L28/90—Electrodes with an enlarged surface, e.g. formed by texturisation having vertical extensions
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/40—Electrodes ; Multistep manufacturing processes therefor
    • H01L29/41—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions
    • H01L29/423—Electrodes ; Multistep manufacturing processes therefor characterised by their shape, relative sizes or dispositions not carrying the current to be rectified, amplified or switched
    • H01L29/42312—Gate electrodes for field effect devices
    • H01L29/42316—Gate electrodes for field effect devices for field-effect transistors
    • H01L29/4232—Gate electrodes for field effect devices for field-effect transistors with insulated gate
    • H01L29/42372—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out
    • H01L29/42376—Gate electrodes for field effect devices for field-effect transistors with insulated gate characterised by the conducting layer, e.g. the length, the sectional shape or the lay-out characterised by the length or the sectional shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
    • H01L29/68—Types of semiconductor device ; Multistep manufacturing processes therefor controllable by only the electric current supplied, or only the electric potential applied, to an electrode which does not carry the current to be rectified, amplified or switched
    • H01L29/76—Unipolar devices, e.g. field effect transistors
    • H01L29/772—Field effect transistors
    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/7827—Vertical transistors
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/03—Making the capacitor or connections thereto
    • H10B12/033—Making the capacitor or connections thereto the capacitor extending over the transistor
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B12/00—Dynamic random access memory [DRAM] devices
    • H10B12/01—Manufacture or treatment
    • H10B12/02—Manufacture or treatment for one transistor one-capacitor [1T-1C] memory cells
    • H10B12/05—Making the transistor
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/403—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh
    • G11C11/405—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells with charge regeneration common to a multiplicity of memory cells, i.e. external refresh with three charge-transfer gates, e.g. MOS transistors, per cell
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C11/00—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor
    • G11C11/21—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements
    • G11C11/34—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices
    • G11C11/40—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors
    • G11C11/401—Digital stores characterised by the use of particular electric or magnetic storage elements; Storage elements therefor using electric elements using semiconductor devices using transistors forming cells needing refreshing or charge regeneration, i.e. dynamic cells
    • G11C11/4063—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing
    • G11C11/407—Auxiliary circuits, e.g. for addressing, decoding, driving, writing, sensing or timing for memory cells of the field-effect type
    • G11C11/409—Read-write [R-W] circuitsĀ 
    • G11C11/4097—Bit-line organisation, e.g. bit-line layout, folded bit lines
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/528—Geometry or layout of the interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/04—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body
    • H01L27/06—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers the substrate being a semiconductor body including a plurality of individual components in a non-repetitive configuration
    • H01L27/0688—Integrated circuits having a three-dimensional layout
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/08—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/0843—Source or drain regions of field-effect devices
    • H01L29/0847—Source or drain regions of field-effect devices of field-effect transistors with insulated gate
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L29/00—Semiconductor devices specially adapted for rectifying, amplifying, oscillating or switching and having potential barriers; Capacitors or resistors having potential barriers, e.g. a PN-junction depletion layer or carrier concentration layer; Details of semiconductor bodies or of electrodes thereof ; Multistep manufacturing processes therefor
    • H01L29/02—Semiconductor bodies ; Multistep manufacturing processes therefor
    • H01L29/06—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions
    • H01L29/10—Semiconductor bodies ; Multistep manufacturing processes therefor characterised by their shape; characterised by the shapes, relative sizes, or dispositions of the semiconductor regions ; characterised by the concentration or distribution of impurities within semiconductor regions with semiconductor regions connected to an electrode not carrying current to be rectified, amplified or switched and such electrode being part of a semiconductor device which comprises three or more electrodes
    • H01L29/1025—Channel region of field-effect devices
    • H01L29/1029—Channel region of field-effect devices of field-effect transistors
    • H01L29/1033—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure
    • H01L29/1037—Channel region of field-effect devices of field-effect transistors with insulated gate, e.g. characterised by the length, the width, the geometric contour or the doping structure and non-planar channel

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Semiconductor Memories (AREA)
EP17847158.7A 2016-08-31 2017-07-31 Memory arrays Active EP3507831B1 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
EP21153826.9A EP3840046A1 (en) 2016-08-31 2017-07-31 Memory cells and memory arrays

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201662381720P 2016-08-31 2016-08-31
PCT/US2017/044638 WO2018044456A1 (en) 2016-08-31 2017-07-31 Memory cells and memory arrays

Related Child Applications (2)

Application Number Title Priority Date Filing Date
EP21153826.9A Division-Into EP3840046A1 (en) 2016-08-31 2017-07-31 Memory cells and memory arrays
EP21153826.9A Division EP3840046A1 (en) 2016-08-31 2017-07-31 Memory cells and memory arrays

Publications (3)

Publication Number Publication Date
EP3507831A1 EP3507831A1 (en) 2019-07-10
EP3507831A4 true EP3507831A4 (en) 2020-06-17
EP3507831B1 EP3507831B1 (en) 2021-03-03

Family

ID=61243451

Family Applications (2)

Application Number Title Priority Date Filing Date
EP17847158.7A Active EP3507831B1 (en) 2016-08-31 2017-07-31 Memory arrays
EP21153826.9A Pending EP3840046A1 (en) 2016-08-31 2017-07-31 Memory cells and memory arrays

Family Applications After (1)

Application Number Title Priority Date Filing Date
EP21153826.9A Pending EP3840046A1 (en) 2016-08-31 2017-07-31 Memory cells and memory arrays

Country Status (5)

Country Link
US (2) US10157926B2 (en)
EP (2) EP3507831B1 (en)
KR (2) KR20180130581A (en)
CN (1) CN109219883B (en)
WO (1) WO2018044456A1 (en)

Families Citing this family (38)

* Cited by examiner, ā€  Cited by third party
Publication number Priority date Publication date Assignee Title
KR102134532B1 (en) 2016-08-31 2020-07-20 ė§ˆģ“ķ¬ė”  ķ…Œķ¬ė†€ė”œģ§€, ģøķ¬ Memory cells and memory arrays
US10079235B2 (en) 2016-08-31 2018-09-18 Micron Technology, Inc. Memory cells and memory arrays
EP3507808A4 (en) 2016-08-31 2020-05-27 Micron Technology, Inc. Memory arrays
US10355002B2 (en) * 2016-08-31 2019-07-16 Micron Technology, Inc. Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
WO2018044479A1 (en) 2016-08-31 2018-03-08 Micron Technology, Inc. Sense amplifier constructions
EP3507829B1 (en) 2016-08-31 2022-04-06 Micron Technology, Inc. Memory cells and memory arrays
EP3507831B1 (en) 2016-08-31 2021-03-03 Micron Technology, Inc. Memory arrays
CN110192280A (en) 2017-01-12 2019-08-30 ē¾Žå…‰ē§‘ęŠ€å…¬åø Memory cell, pair transistor single capacitor memory cell array, the method for forming pair transistor single capacitor memory cell array and the method for manufacturing integrated circuit
US10177159B2 (en) 2017-04-21 2019-01-08 Micron Technology, Inc. Memory cells and memory arrays
US10347635B2 (en) 2017-06-30 2019-07-09 Micron Technology, Inc. Apparatuses comprising memory cells, and apparatuses comprising memory arrays
WO2019045882A1 (en) 2017-08-29 2019-03-07 Micron Technology, Inc. Memory circuitry
CN110785843A (en) * 2017-08-31 2020-02-11 ē¾Žå…‰ē§‘ęŠ€å…¬åø Apparatus having a memory cell with two transistors and one capacitor and having a body region of the transistors coupled to a reference voltage
US10297290B1 (en) 2017-12-29 2019-05-21 Micron Technology, Inc. Semiconductor devices, and related control logic assemblies, control logic devices, electronic systems, and methods
US10366983B2 (en) 2017-12-29 2019-07-30 Micron Technology, Inc. Semiconductor devices including control logic structures, electronic systems, and related methods
US10340267B1 (en) 2017-12-29 2019-07-02 Micron Technology, Inc. Semiconductor devices including control logic levels, and related memory devices, control logic assemblies, electronic systems, and methods
US10229874B1 (en) 2018-03-22 2019-03-12 Micron Technology, Inc. Arrays of memory cells individually comprising a capacitor and a transistor and methods of forming such arrays
US10748931B2 (en) 2018-05-08 2020-08-18 Micron Technology, Inc. Integrated assemblies having ferroelectric transistors with body regions coupled to carrier reservoirs
WO2020181049A1 (en) 2019-03-06 2020-09-10 Micron Technology, Inc. Integrated assemblies having transistor body regions coupled to carrier-sink-structures; and methods of forming integrated assemblies
US11031374B2 (en) * 2019-03-06 2021-06-08 Micron Technology, Inc. Methods of compensating for misalignment of bonded semiconductor wafers
US11038027B2 (en) * 2019-03-06 2021-06-15 Micron Technology, Inc. Integrated assemblies having polycrystalline first semiconductor material adjacent conductively-doped second semiconductor material
US11062763B2 (en) 2019-04-09 2021-07-13 Micron Technology, Inc. Memory array with multiplexed digit lines
US10854617B2 (en) 2019-04-09 2020-12-01 Micron Technology, Inc. Integrated components which have both horizontally-oriented transistors and vertically-oriented transistors
US11049864B2 (en) * 2019-05-17 2021-06-29 Micron Technology, Inc. Apparatuses including capacitor structures, and related memory devices, electronic systems, and methods
KR20210052660A (en) 2019-10-29 2021-05-11 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Three-dimensional Semiconductor memory device
US11094699B1 (en) 2020-05-28 2021-08-17 Micron Technology, Inc. Apparatuses including stacked horizontal capacitor structures and related methods, memory devices, and electronic systems
TW202145506A (en) * 2020-05-29 2021-12-01 台ē£ē©é«”é›»č·Æč£½é€ č‚”ä»½ęœ‰é™å…¬åø Memory cell
US11569244B2 (en) * 2020-05-29 2023-01-31 Taiwan Semiconductor Manufacturing Company Limited Vertical heterostructure semiconductor memory cell and methods for making the same
KR20220007393A (en) 2020-07-10 2022-01-18 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Semiconductor memory device
US11903221B2 (en) * 2020-08-17 2024-02-13 Taiwan Semiconductor Manufacturing Co., Ltd. Three dimensional semiconductor device with memory stack
US11495600B2 (en) * 2020-11-10 2022-11-08 Micron Technology, Inc. Vertical three-dimensional memory with vertical channel
US12120865B2 (en) * 2020-12-23 2024-10-15 Intel Corporation Arrays of double-sided dram cells including capacitors on the frontside and backside of a stacked transistor structure
US11770923B2 (en) * 2021-03-03 2023-09-26 Micron Technology, Inc. Thin film transistor random access memory
JP2022146576A (en) * 2021-03-22 2022-10-05 悭ć‚Ŗć‚Æć‚·ć‚¢ę Ŗ式会ē¤¾ Semiconductor device and semiconductor storage device
WO2023028821A1 (en) * 2021-08-31 2023-03-09 Yangtze Memory Technologies Co., Ltd. Memory devices having vertical transistors and methods for forming thereof
WO2023028829A1 (en) 2021-08-31 2023-03-09 Yangtze Memory Technologies Co., Ltd. Memory devices having vertical transistors and methods for forming the same
WO2023028890A1 (en) 2021-08-31 2023-03-09 Yangtze Memory Technologies Co., Ltd. Memory devices having vertical transistors and methods for forming the same
CN116097915A (en) * 2021-08-31 2023-05-09 é•æę±Ÿå­˜å‚Øē§‘ęŠ€ęœ‰é™č“£ä»»å…¬åø Memory device with vertical transistor and method of forming the same
US12114480B2 (en) * 2021-12-21 2024-10-08 Tokyo Electron Limited Method of making of plurality of 3D vertical logic elements integrated with 3D memory

Citations (3)

* Cited by examiner, ā€  Cited by third party
Publication number Priority date Publication date Assignee Title
US20040151020A1 (en) * 2002-11-27 2004-08-05 Peter Beer Dynamic memory cell
US20040232497A1 (en) * 2001-12-14 2004-11-25 Satoru Akiyama Semiconductor device and method for manufacturing the same
US7164595B1 (en) * 2005-08-25 2007-01-16 Micron Technology, Inc. Device and method for using dynamic cell plate sensing in a DRAM memory cell

Family Cites Families (111)

* Cited by examiner, ā€  Cited by third party
Publication number Priority date Publication date Assignee Title
US4103342A (en) 1976-06-17 1978-07-25 International Business Machines Corporation Two-device memory cell with single floating capacitor
US4554570A (en) 1982-06-24 1985-11-19 Rca Corporation Vertically integrated IGFET device
US5066607A (en) 1987-11-30 1991-11-19 Texas Instruments Incorporated Method of making a trench DRAM cell with dynamic gain
US5146300A (en) 1989-11-27 1992-09-08 Mitsubishi Denki Kabushiki Kaisha Semiconductor integrated circuit device having improved stacked capacitor and manufacturing method therefor
JPH03205867A (en) 1990-01-08 1991-09-09 Nec Corp Semiconductor memory
JP2678094B2 (en) * 1991-03-01 1997-11-17 ć‚·ćƒ£ćƒ¼ćƒ—ę Ŗ式会ē¤¾ Dynamic random access memory
US5398200A (en) 1992-03-02 1995-03-14 Motorola, Inc. Vertically formed semiconductor random access memory device
US5389810A (en) * 1992-03-27 1995-02-14 Matsushita Electric Industrial Co., Ltd. Semiconductor device having at least one symmetrical pair of MOSFETs
US5363327A (en) * 1993-01-19 1994-11-08 International Business Machines Corporation Buried-sidewall-strap two transistor one capacitor trench cell
TW378323B (en) 1994-09-22 2000-01-01 Matsushita Electric Ind Co Ltd Ferroelectric memory device
JP3226433B2 (en) 1994-09-22 2001-11-05 ę¾äø‹é›»å™Øē”£ę„­ę Ŗ式会ē¤¾ Ferroelectric memory device
JP3135795B2 (en) 1994-09-22 2001-02-19 ę±čŠćƒžć‚¤ć‚Æ惭ć‚Ø惬ć‚Æ惈惭惋ć‚Æć‚¹ę Ŗ式会ē¤¾ Dynamic memory
JP3549602B2 (en) 1995-01-12 2004-08-04 ę Ŗ式会ē¤¾ćƒ«ćƒć‚µć‚¹ćƒ†ć‚Æ惎惭ć‚ø Semiconductor storage device
JPH08264764A (en) 1995-03-22 1996-10-11 Toshiba Corp Semiconductor device
US5830791A (en) * 1995-09-06 1998-11-03 Lg Semicon Co., Ltd. Manufacturing process for a DRAM with a buried region
US8018058B2 (en) 2004-06-21 2011-09-13 Besang Inc. Semiconductor memory device
JP3495905B2 (en) 1998-02-19 2004-02-09 ć‚·ćƒ£ćƒ¼ćƒ—ę Ŗ式会ē¤¾ Semiconductor storage device
US6043527A (en) 1998-04-14 2000-03-28 Micron Technology, Inc. Circuits and methods for a memory cell with a trench plate trench capacitor and a vertical bipolar read device
US6028806A (en) 1998-05-22 2000-02-22 Micron Technology, Inc. Semiconductor memory with local phase generation from global phase signals and local isolation signals
US6141286A (en) 1998-08-21 2000-10-31 Micron Technology, Inc. Embedded DRAM architecture with local data drivers and programmable number of data read and data write lines
US6365453B1 (en) 1999-06-16 2002-04-02 Micron Technology, Inc. Method and structure for reducing contact aspect ratios
US6159818A (en) 1999-09-02 2000-12-12 Micron Technology, Inc. Method of forming a container capacitor structure
JP4047531B2 (en) 2000-10-17 2008-02-13 ę Ŗ式会ē¤¾ę±čŠ Ferroelectric memory device
JP2002216473A (en) 2001-01-16 2002-08-02 Matsushita Electric Ind Co Ltd Semiconductor memory
US6518610B2 (en) * 2001-02-20 2003-02-11 Micron Technology, Inc. Rhodium-rich oxygen barriers
CA2342496A1 (en) 2001-03-30 2002-09-30 Atmos Corporation Twisted wordline straps
US6528896B2 (en) 2001-06-21 2003-03-04 Samsung Electronics Co., Ltd. Scalable two transistor memory device
US6794238B2 (en) * 2001-11-07 2004-09-21 Micron Technology, Inc. Process for forming metallized contacts to periphery transistors
JP2003263886A (en) 2002-03-08 2003-09-19 Fujitsu Ltd Ferroelectric memory in which bit line capacity can be optimized
JP2003273245A (en) 2002-03-15 2003-09-26 Hitachi Ltd Semiconductor memory device
US6587367B1 (en) 2002-03-19 2003-07-01 Texas Instruments Incorporated Dummy cell structure for 1T1C FeRAM cell array
JP3650077B2 (en) 2002-03-29 2005-05-18 ę²–é›»ę°—å·„ę„­ę Ŗ式会ē¤¾ Semiconductor memory device
JP4290921B2 (en) 2002-04-08 2009-07-08 ć‚Øćƒ«ćƒ”ćƒ¼ćƒ€ćƒ”ćƒ¢ćƒŖę Ŗ式会ē¤¾ Semiconductor integrated circuit device
ITMI20020793A1 (en) 2002-04-15 2003-10-15 St Microelectronics Srl SEMICONDUCTOR MEMORY FERAM
EP1512150B1 (en) * 2002-05-28 2010-09-01 Nxp B.V. Memory array having 2t memory cells
US6563727B1 (en) 2002-07-31 2003-05-13 Alan Roth Method and structure for reducing noise effects in content addressable memories
KR100456598B1 (en) 2002-09-09 2004-11-09 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Memory device arranged memory cells having complementary data
US6744087B2 (en) 2002-09-27 2004-06-01 International Business Machines Corporation Non-volatile memory using ferroelectric gate field-effect transistors
JP4005468B2 (en) * 2002-09-30 2007-11-07 åƌ士通ę Ŗ式会ē¤¾ Memory cell arrangement method and semiconductor memory device
JP3597185B2 (en) 2002-11-12 2004-12-02 ę²–é›»ę°—å·„ę„­ę Ŗ式会ē¤¾ Ferroelectric memory
US6804142B2 (en) 2002-11-12 2004-10-12 Micron Technology, Inc. 6F2 3-transistor DRAM gain cell
US6960796B2 (en) 2002-11-26 2005-11-01 Micron Technology, Inc. CMOS imager pixel designs with storage capacitor
US6845033B2 (en) 2003-03-05 2005-01-18 International Business Machines Corporation Structure and system-on-chip integration of a two-transistor and two-capacitor memory cell for trench technology
US6822891B1 (en) 2003-06-16 2004-11-23 Kabushiki Kaisha Toshiba Ferroelectric memory device
US7867822B2 (en) 2003-06-24 2011-01-11 Sang-Yun Lee Semiconductor memory device
JP3961994B2 (en) 2003-07-28 2007-08-22 ę Ŗ式会ē¤¾ę±čŠ Semiconductor memory device
DE10344604B4 (en) 2003-09-25 2011-08-11 Infineon Technologies AG, 81669 Storage unit with collecting electrodes
US7262089B2 (en) * 2004-03-11 2007-08-28 Micron Technology, Inc. Methods of forming semiconductor structures
US7378702B2 (en) 2004-06-21 2008-05-27 Sang-Yun Lee Vertical memory device structures
US7122425B2 (en) 2004-08-24 2006-10-17 Micron Technology, Inc. Methods of forming semiconductor constructions
US7241655B2 (en) * 2004-08-30 2007-07-10 Micron Technology, Inc. Method of fabricating a vertical wrap-around-gate field-effect-transistor for high density, low voltage logic and memory array
US7199419B2 (en) * 2004-12-13 2007-04-03 Micron Technology, Inc. Memory structure for reduced floating body effect
KR100585169B1 (en) 2004-12-23 2006-06-02 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Layout of semiconductor memory device and method of controlling capacitance of dummy cell
KR100681039B1 (en) * 2005-07-04 2007-02-09 ģ—˜ģ§€ģ „ģž ģ£¼ģ‹ķšŒģ‚¬ Oled
US7488664B2 (en) 2005-08-10 2009-02-10 Micron Technology, Inc. Capacitor structure for two-transistor DRAM memory cell and method of forming same
US7330388B1 (en) 2005-09-23 2008-02-12 Cypress Semiconductor Corporation Sense amplifier circuit and method of operation
US7358133B2 (en) 2005-12-28 2008-04-15 Nanya Technology Corporation Semiconductor device and method for making the same
KR100729360B1 (en) 2006-04-05 2007-06-15 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Capacitor structures of semiconductor device and methods of fabricating the same
KR100739532B1 (en) 2006-06-09 2007-07-13 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Method of forming a buried bit line
US7772632B2 (en) 2006-08-21 2010-08-10 Micron Technology, Inc. Memory arrays and methods of fabricating memory arrays
KR100791339B1 (en) 2006-08-25 2008-01-03 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ An embeded semiconductor device including planarization resistant patterns and method for fabricating the same
JP5057739B2 (en) 2006-10-03 2012-10-24 ę Ŗ式会ē¤¾ę±čŠ Semiconductor memory device
JP4901459B2 (en) 2006-12-26 2012-03-21 ę Ŗ式会ē¤¾ę±čŠ Semiconductor memory device
US7558097B2 (en) 2006-12-28 2009-07-07 Intel Corporation Memory having bit line with resistor(s) between memory cells
TWI349334B (en) 2007-07-02 2011-09-21 Nanya Technology Corp Dram structure and method of making the same
US7679405B2 (en) 2007-10-24 2010-03-16 Agere Systems Inc. Latch-based sense amplifier
US7920404B2 (en) 2007-12-31 2011-04-05 Texas Instruments Incorporated Ferroelectric memory devices with partitioned platelines
US7742324B2 (en) 2008-02-19 2010-06-22 Micron Technology, Inc. Systems and devices including local data lines and methods of using, making, and operating the same
US7700469B2 (en) 2008-02-26 2010-04-20 Micron Technology, Inc. Methods of forming semiconductor constructions
US7821039B2 (en) * 2008-06-23 2010-10-26 Taiwan Semiconductor Manufacturing Company, Ltd. Layout architecture for improving circuit performance
US8009459B2 (en) 2008-12-30 2011-08-30 Taiwan Semiconductor Manufacturing Company, Ltd. Circuit for high speed dynamic memory
JP4487221B1 (en) 2009-04-17 2010-06-23 ę—„ęœ¬ćƒ¦ćƒ‹ć‚µćƒ³ćƒ†ć‚£ć‚¹ć‚Ø惬ć‚Æ惈惭惋ć‚Æć‚¹ę Ŗ式会ē¤¾ Semiconductor device
JP5588123B2 (en) 2009-05-22 2014-09-10 ćƒ”ćƒ¼ć‚Øć‚¹ćƒ•ć‚©ćƒ¼ 惫ć‚Æć‚¹ć‚³ ć‚Øć‚¹ć‚Øć‚¤ć‚¢ćƒ¼ćƒ«ć‚Ø惫 Semiconductor device and manufacturing method thereof
JP5524547B2 (en) 2009-09-14 2014-06-18 ćƒ¦ćƒ‹ć‚µćƒ³ćƒ†ć‚£ć‚¹ ć‚Ø惬ć‚Æ惈惭惋ć‚Æć‚¹ ć‚·ćƒ³ć‚¬ćƒćƒ¼ćƒ« ćƒ—ćƒ©ć‚¤ćƒ™ćƒ¼ćƒˆ ćƒŖ惟惆惃惉 Semiconductor memory device
JP2011142256A (en) 2010-01-08 2011-07-21 Elpida Memory Inc Semiconductor device and method of manufacturing the same
KR20180043383A (en) * 2010-01-22 2018-04-27 ź°€ė¶€ģ‹œķ‚¤ź°€ģ“ģƒ¤ ķ•œė„ģ˜¤ė”°ģ“ ģ—ė„¤ė£Øźø° ģ¼„ķģ‡¼ Method for manufacturing semiconductor device
KR101669244B1 (en) 2010-06-08 2016-10-25 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Sram devices and methods for fabricating the same
US9454997B2 (en) 2010-12-02 2016-09-27 Micron Technology, Inc. Array of nonvolatile memory cells having at least five memory cells per unit cell, having a plurality of the unit cells which individually comprise three elevational regions of programmable material, and/or having a continuous volume having a combination of a plurality of vertically oriented memory cells and a plurality of horizontally oriented memory cells; array of vertically stacked tiers of nonvolatile memory cells
TWI415247B (en) 2010-12-15 2013-11-11 Powerchip Technology Corp Dynamic random access memory cell and array having vertical channel transistor
EP2555241A1 (en) 2011-08-02 2013-02-06 Nxp B.V. IC die, semiconductor package, printed circuit board and IC die manufacturing method
KR20130042779A (en) * 2011-10-19 2013-04-29 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Semiconductor devices including a vertical channel transistor and methods of fabricating the same
US8704221B2 (en) 2011-12-23 2014-04-22 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US8872258B2 (en) 2012-01-26 2014-10-28 Ps4 Luxco S.A.R.L. Semiconductor memory device
US20130193400A1 (en) * 2012-01-27 2013-08-01 Micron Technology, Inc. Memory Cell Structures and Memory Arrays
JP2013168569A (en) 2012-02-16 2013-08-29 Elpida Memory Inc Semiconductor device and manufacturing method of the same
US9312257B2 (en) * 2012-02-29 2016-04-12 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device
US9036391B2 (en) 2012-03-06 2015-05-19 Micron Technology, Inc. Arrays of vertically-oriented transistors, memory arrays including vertically-oriented transistors, and memory cells
JP2013187223A (en) 2012-03-06 2013-09-19 Elpida Memory Inc Semiconductor device
US8693253B2 (en) * 2012-04-30 2014-04-08 Design Express Limited Vertically stackable NAND flash memory
KR20140017272A (en) 2012-07-31 2014-02-11 ģ—ģŠ¤ģ¼€ģ“ķ•˜ģ“ė‹‰ģŠ¤ ģ£¼ģ‹ķšŒģ‚¬ Semiconductor device and method of fabricating the same
US9478550B2 (en) 2012-08-27 2016-10-25 Micron Technology, Inc. Arrays of vertically-oriented transistors, and memory arrays including vertically-oriented transistors
KR102061694B1 (en) 2013-10-14 2020-01-02 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Semiconductor memory device having three-dimensional cross point array
KR102191215B1 (en) 2013-12-20 2020-12-16 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Static random access memory (sram) cell and method of manufacturing the same
US9343507B2 (en) 2014-03-12 2016-05-17 Sandisk 3D Llc Dual channel vertical field effect transistor including an embedded electrode
US10128327B2 (en) 2014-04-30 2018-11-13 Stmicroelectronics, Inc. DRAM interconnect structure having ferroelectric capacitors exhibiting negative capacitance
KR102184355B1 (en) 2014-09-16 2020-11-30 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Semiconductor device
US9245893B1 (en) 2014-11-19 2016-01-26 Micron Technology, Inc. Semiconductor constructions having grooves dividing active regions
US9419003B1 (en) 2015-05-15 2016-08-16 Taiwan Semiconductor Manufacturing Company, Ltd. Semiconductor devices and methods of manufacture thereof
US9378780B1 (en) 2015-06-16 2016-06-28 National Tsing Hua University Sense amplifier
US10424671B2 (en) 2015-07-29 2019-09-24 Semiconductor Energy Laboratory Co., Ltd. Semiconductor device, circuit board, and electronic device
KR102420150B1 (en) 2015-08-19 2022-07-13 ģ‚¼ģ„±ģ „ģžģ£¼ģ‹ķšŒģ‚¬ Method of fabricating semiconductor device
US20170186782A1 (en) 2015-12-24 2017-06-29 Innolux Corporation Pixel circuit of active-matrix light-emitting diode and display panel having the same
JP6538598B2 (en) 2016-03-16 2019-07-03 ę Ŗ式会ē¤¾ę±čŠ Transistor and semiconductor memory device
US10355002B2 (en) 2016-08-31 2019-07-16 Micron Technology, Inc. Memory cells, methods of forming an array of two transistor-one capacitor memory cells, and methods used in fabricating integrated circuitry
EP3507831B1 (en) 2016-08-31 2021-03-03 Micron Technology, Inc. Memory arrays
EP3507829B1 (en) 2016-08-31 2022-04-06 Micron Technology, Inc. Memory cells and memory arrays
US10079235B2 (en) 2016-08-31 2018-09-18 Micron Technology, Inc. Memory cells and memory arrays
CN110192280A (en) 2017-01-12 2019-08-30 ē¾Žå…‰ē§‘ęŠ€å…¬åø Memory cell, pair transistor single capacitor memory cell array, the method for forming pair transistor single capacitor memory cell array and the method for manufacturing integrated circuit
CN110603640B (en) 2017-07-17 2023-06-27 ē¾Žå…‰ē§‘ęŠ€å…¬åø Memory circuit system
US10020311B1 (en) 2017-08-02 2018-07-10 Ap Memory Technology Corporation Semiconductor memory device provided with DRAM cell including two transistors and common capacitor
CN110785843A (en) 2017-08-31 2020-02-11 ē¾Žå…‰ē§‘ęŠ€å…¬åø Apparatus having a memory cell with two transistors and one capacitor and having a body region of the transistors coupled to a reference voltage

Patent Citations (3)

* Cited by examiner, ā€  Cited by third party
Publication number Priority date Publication date Assignee Title
US20040232497A1 (en) * 2001-12-14 2004-11-25 Satoru Akiyama Semiconductor device and method for manufacturing the same
US20040151020A1 (en) * 2002-11-27 2004-08-05 Peter Beer Dynamic memory cell
US7164595B1 (en) * 2005-08-25 2007-01-16 Micron Technology, Inc. Device and method for using dynamic cell plate sensing in a DRAM memory cell

Non-Patent Citations (2)

* Cited by examiner, ā€  Cited by third party
Title
CHAO-GANG WEI ET AL: "A NEW HIGH-RELIABLE 2T/1C FeRAM CELL", INTEGRATED FERROELECTRICS, vol. 81, no. 1, 17 August 2006 (2006-08-17), US, pages 149 - 155, XP055694118, ISSN: 1058-4587, DOI: 10.1080/10584580600660264 *
See also references of WO2018044456A1 *

Also Published As

Publication number Publication date
CN109219883B (en) 2023-03-21
KR20200113006A (en) 2020-10-05
US11094697B2 (en) 2021-08-17
EP3507831B1 (en) 2021-03-03
EP3507831A1 (en) 2019-07-10
WO2018044456A1 (en) 2018-03-08
US20180061835A1 (en) 2018-03-01
US20190088652A1 (en) 2019-03-21
EP3840046A1 (en) 2021-06-23
US10157926B2 (en) 2018-12-18
CN109219883A (en) 2019-01-15
KR102223551B1 (en) 2021-03-08
KR20180130581A (en) 2018-12-07

Similar Documents

Publication Publication Date Title
EP3507831A4 (en) Memory cells and memory arrays
EP3507830A4 (en) Memory cells and memory arrays
EP3507832A4 (en) Memory cells and memory arrays
EP3507829A4 (en) Memory cells and memory arrays
EP3571720A4 (en) Memory cells, integrated structures and memory arrays
EP3635782A4 (en) Memory arrays
EP3635783A4 (en) Memory arrays
EP3711093A4 (en) Memory cells, memory arrays, and methods of forming memory arrays
EP3507804A4 (en) Ferroelectric memory cells
EP3729437A4 (en) Auto-referenced memory cell read techniques
EP3729429A4 (en) Auto-referenced memory cell read techniques
EP3718110A4 (en) Operations on memory cells
EP3259757A4 (en) Memory cells
EP3577690A4 (en) Nand memory arrays, and methods of forming nand memory arrays
EP3155620A4 (en) Memory cell and an array of memory cells
EP3888127A4 (en) Memory arrays
EP3577688A4 (en) Memory arrays, and methods of forming memory arrays
EP3281225A4 (en) Constructions comprising stacked memory arrays
EP3616240A4 (en) Arrays of elevationally-extending strings of memory cells and methods of forming memory arrays
EP3380117A4 (en) Genetically modified cells and uses thereof
EP3430626A4 (en) Ferroelectric memory cell sensing
EP3440673A4 (en) Supply-switched dual cell memory bitcell
EP3612568B8 (en) Cell
EP3459079A4 (en) Improved flash memory cell associated decoders
EP3180430A4 (en) Genomically-encoded memory in live cells

Legal Events

Date Code Title Description
STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE INTERNATIONAL PUBLICATION HAS BEEN MADE

PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: REQUEST FOR EXAMINATION WAS MADE

17P Request for examination filed

Effective date: 20181107

AK Designated contracting states

Kind code of ref document: A1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

AX Request for extension of the european patent

Extension state: BA ME

DAV Request for validation of the european patent (deleted)
DAX Request for extension of the european patent (deleted)
RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 27/108 20060101AFI20200220BHEP

A4 Supplementary search report drawn up and despatched

Effective date: 20200520

RIC1 Information provided on ipc code assigned before grant

Ipc: H01L 27/108 20060101AFI20200514BHEP

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

INTG Intention to grant announced

Effective date: 20200928

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: GRANT OF PATENT IS INTENDED

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: THE PATENT HAS BEEN GRANTED

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): AL AT BE BG CH CY CZ DE DK EE ES FI FR GB GR HR HU IE IS IT LI LT LU LV MC MK MT NL NO PL PT RO RS SE SI SK SM TR

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: AT

Ref legal event code: REF

Ref document number: 1368150

Country of ref document: AT

Kind code of ref document: T

Effective date: 20210315

Ref country code: CH

Ref legal event code: EP

REG Reference to a national code

Ref country code: DE

Ref legal event code: R096

Ref document number: 602017034058

Country of ref document: DE

REG Reference to a national code

Ref country code: IE

Ref legal event code: FG4D

REG Reference to a national code

Ref country code: LT

Ref legal event code: MG9D

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: BG

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210603

Ref country code: NO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210603

Ref country code: HR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: FI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: GR

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210604

REG Reference to a national code

Ref country code: NL

Ref legal event code: MP

Effective date: 20210303

REG Reference to a national code

Ref country code: AT

Ref legal event code: MK05

Ref document number: 1368150

Country of ref document: AT

Kind code of ref document: T

Effective date: 20210303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LV

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: RS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: PL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: SE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: NL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: EE

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: CZ

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: AT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: SM

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: PT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210705

Ref country code: RO

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: SK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210703

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602017034058

Country of ref document: DE

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: DK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: AL

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: ES

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

26N No opposition filed

Effective date: 20211206

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: SI

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

REG Reference to a national code

Ref country code: CH

Ref legal event code: PL

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MC

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

REG Reference to a national code

Ref country code: BE

Ref legal event code: MM

Effective date: 20210731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: LI

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210731

Ref country code: IT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

Ref country code: CH

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IS

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210703

Ref country code: LU

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: IE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210731

Ref country code: BE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20210731

REG Reference to a national code

Ref country code: DE

Ref legal event code: R079

Ref document number: 602017034058

Country of ref document: DE

Free format text: PREVIOUS MAIN CLASS: H01L0027108000

Ipc: H10B0012000000

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: CY

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: HU

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT; INVALID AB INITIO

Effective date: 20170731

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MK

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: MT

Free format text: LAPSE BECAUSE OF FAILURE TO SUBMIT A TRANSLATION OF THE DESCRIPTION OR TO PAY THE FEE WITHIN THE PRESCRIBED TIME-LIMIT

Effective date: 20210303

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20240730

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: GB

Payment date: 20240724

Year of fee payment: 8

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20240725

Year of fee payment: 8