FR2839156B1 - Circuit et procede utilisant de multiples chaines d'acces serie pour le test de cirucuits integres - Google Patents
Circuit et procede utilisant de multiples chaines d'acces serie pour le test de cirucuits integresInfo
- Publication number
- FR2839156B1 FR2839156B1 FR0209758A FR0209758A FR2839156B1 FR 2839156 B1 FR2839156 B1 FR 2839156B1 FR 0209758 A FR0209758 A FR 0209758A FR 0209758 A FR0209758 A FR 0209758A FR 2839156 B1 FR2839156 B1 FR 2839156B1
- Authority
- FR
- France
- Prior art keywords
- circuit
- integrated circuits
- access channels
- multiple series
- testing integrated
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3177—Testing of logic operation, e.g. by logic analysers
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/2851—Testing of integrated circuits [IC]
- G01R31/2886—Features relating to contacting the IC under test, e.g. probe heads; chucks
- G01R31/2891—Features relating to contacting the IC under test, e.g. probe heads; chucks related to sensing or controlling of force, position, temperature
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318536—Scan chain arrangements, e.g. connections, test bus, analog signals
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318541—Scan latches or cell details
-
- G—PHYSICS
- G01—MEASURING; TESTING
- G01R—MEASURING ELECTRIC VARIABLES; MEASURING MAGNETIC VARIABLES
- G01R31/00—Arrangements for testing electric properties; Arrangements for locating electric faults; Arrangements for electrical testing characterised by what is being tested not provided for elsewhere
- G01R31/28—Testing of electronic circuits, e.g. by signal tracer
- G01R31/317—Testing of digital circuits
- G01R31/3181—Functional testing
- G01R31/3185—Reconfiguring for testing, e.g. LSSD, partitioning
- G01R31/318533—Reconfiguring for testing, e.g. LSSD, partitioning using scanning techniques, e.g. LSSD, Boundary Scan, JTAG
- G01R31/318552—Clock circuits details
Landscapes
- Engineering & Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- Physics & Mathematics (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Tests Of Electronic Circuits (AREA)
- Semiconductor Integrated Circuits (AREA)
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US10/136,670 US7249298B2 (en) | 2002-04-30 | 2002-04-30 | Multiple scan chains with pin sharing |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2839156A1 FR2839156A1 (fr) | 2003-10-31 |
FR2839156B1 true FR2839156B1 (fr) | 2006-07-07 |
Family
ID=22473846
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0209758A Expired - Lifetime FR2839156B1 (fr) | 2002-04-30 | 2002-07-31 | Circuit et procede utilisant de multiples chaines d'acces serie pour le test de cirucuits integres |
Country Status (7)
Country | Link |
---|---|
US (1) | US7249298B2 (fr) |
JP (1) | JP4202165B2 (fr) |
KR (1) | KR100486275B1 (fr) |
FR (1) | FR2839156B1 (fr) |
GB (1) | GB2388199B (fr) |
NL (1) | NL1021104C2 (fr) |
TW (1) | TWI231372B (fr) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7082560B2 (en) * | 2002-05-24 | 2006-07-25 | Sun Microsystems, Inc. | Scan capable dual edge-triggered state element for application of combinational and sequential scan test patterns |
JP4274806B2 (ja) * | 2003-01-28 | 2009-06-10 | 株式会社リコー | 半導体集積回路およびスキャンテスト法 |
US7975197B2 (en) * | 2003-03-31 | 2011-07-05 | Lsi Corporation | On-chip scan clock generator for ASIC testing |
US7584392B2 (en) * | 2003-05-23 | 2009-09-01 | Cadence Design Systems, Inc. | Test compaction using linear-matrix driven scan chains |
US7657809B1 (en) * | 2003-11-19 | 2010-02-02 | Cadence Design Systems, Inc. | Dual scan chain design method and apparatus |
US7055118B1 (en) | 2004-03-01 | 2006-05-30 | Sun Microsystems, Inc. | Scan chain verification using symbolic simulation |
US7263642B1 (en) | 2005-09-15 | 2007-08-28 | Azul Systems, Inc | Testing replicated sub-systems in a yield-enhancing chip-test environment using on-chip compare to expected results for parallel scan chains testing critical and repairable sections of each sub-system |
US7529294B2 (en) | 2006-02-28 | 2009-05-05 | International Business Machines Corporation | Testing of multiple asynchronous logic domains |
US7441171B2 (en) * | 2006-03-24 | 2008-10-21 | International Business Machines Corporation | Efficient scan chain insertion using broadcast scan for reduced bit collisions |
US7831877B2 (en) * | 2007-03-08 | 2010-11-09 | Silicon Image, Inc. | Circuitry to prevent peak power problems during scan shift |
US7975307B2 (en) * | 2007-09-07 | 2011-07-05 | Freescale Semiconductor, Inc. | Securing proprietary functions from scan access |
US7962819B2 (en) * | 2008-01-24 | 2011-06-14 | Sandisk Corporation | Test mode soft reset circuitry and methods |
US7908534B2 (en) * | 2008-02-25 | 2011-03-15 | International Business Machines Corporation | Diagnosable general purpose test registers scan chain design |
US8555123B2 (en) | 2008-07-23 | 2013-10-08 | Industrial Technology Research Institute | Test device and method for the SoC test architecture |
US7937634B2 (en) * | 2009-02-17 | 2011-05-03 | Almukhaizim Sobeeh A | Circuit and method providing dynamic scan chain partitioning |
TWI405969B (zh) * | 2009-05-08 | 2013-08-21 | Accton Wireless Broadband Corp | 管線式元件測試系統及其方法 |
JP2011149775A (ja) * | 2010-01-20 | 2011-08-04 | Renesas Electronics Corp | 半導体集積回路及びコアテスト回路 |
US8793546B2 (en) * | 2011-06-20 | 2014-07-29 | Lsi Corporation | Integrated circuit comprising scan test circuitry with parallel reordered scan chains |
US9377510B2 (en) | 2012-12-28 | 2016-06-28 | Nvidia Corporation | System for reducing peak power during scan shift at the global level for scan based tests |
US9222981B2 (en) | 2012-12-28 | 2015-12-29 | Nvidia Corporation | Global low power capture scheme for cores |
US9395414B2 (en) | 2012-12-28 | 2016-07-19 | Nvidia Corporation | System for reducing peak power during scan shift at the local level for scan based tests |
US10379161B2 (en) * | 2013-06-17 | 2019-08-13 | Mentor Graphics Corporation | Scan chain stitching for test-per-clock |
US10310015B2 (en) * | 2013-07-19 | 2019-06-04 | Advanced Micro Devices, Inc. | Method and apparatus for providing clock signals for a scan chain |
TWI507989B (zh) * | 2013-08-08 | 2015-11-11 | Nat Univ Tsing Hua | 資源導向之嵌入式系統功率消耗分析方法 |
CN105572573B (zh) * | 2014-10-30 | 2018-08-24 | 国际商业机器公司 | 用于存储器时序测试的扫描链、扫描链构建方法和相应装置 |
US9347991B1 (en) * | 2014-11-12 | 2016-05-24 | Texas Instruments Incorporated | Scan throughput enhancement in scan testing of a device-under-test |
CN106680688B (zh) | 2015-11-11 | 2020-09-25 | 恩智浦美国有限公司 | 利用并行扫描测试数据输入和输出测试多核集成电路 |
TWI625534B (zh) * | 2015-12-21 | 2018-06-01 | 瑞昱半導體股份有限公司 | 透過掃描測試的掃描鏈所執行的除錯方法及相關電路系統 |
US10613142B2 (en) * | 2017-02-22 | 2020-04-07 | International Business Machines Corporation | Non-destructive recirculation test support for integrated circuits |
CN113454471A (zh) * | 2019-03-13 | 2021-09-28 | 美商新思科技有限公司 | 用于多个链缺陷的单次通过诊断 |
US11073557B2 (en) * | 2019-05-08 | 2021-07-27 | Texas Instruments Incorporated | Phase controlled codec block scan of a partitioned circuit device |
US11366162B2 (en) | 2020-04-16 | 2022-06-21 | Mediatek Inc. | Scan output flip-flop with power saving feature |
Family Cites Families (22)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
GB2121997B (en) * | 1982-06-11 | 1985-10-09 | Int Computers Ltd | Testing modular data processing systems |
GB8518859D0 (en) | 1985-07-25 | 1985-08-29 | Int Computers Ltd | Digital integrated circuits |
US4701921A (en) | 1985-10-23 | 1987-10-20 | Texas Instruments Incorporated | Modularized scan path for serially tested logic circuit |
US4701621A (en) * | 1986-02-10 | 1987-10-20 | General Electric Company | Monitor for airborne radioactive particles |
US4947357A (en) * | 1988-02-24 | 1990-08-07 | Stellar Computer, Inc. | Scan testing a digital system using scan chains in integrated circuits |
JPH01270683A (ja) * | 1988-04-22 | 1989-10-27 | Mitsubishi Electric Corp | 半導体集積回路 |
US4989209A (en) * | 1989-03-24 | 1991-01-29 | Motorola, Inc. | Method and apparatus for testing high pin count integrated circuits |
US5412260A (en) | 1991-05-03 | 1995-05-02 | Lattice Semiconductor Corporation | Multiplexed control pins for in-system programming and boundary scan state machines in a high density programmable logic device |
US5592493A (en) | 1994-09-13 | 1997-01-07 | Motorola Inc. | Serial scan chain architecture for a data processing system and method of operation |
US5909451A (en) * | 1996-11-21 | 1999-06-01 | Sun Microsystems, Inc. | System and method for providing scan chain for digital electronic device having multiple clock domains |
JPH1138100A (ja) * | 1997-07-18 | 1999-02-12 | Advantest Corp | 半導体試験装置 |
US6049901A (en) * | 1997-09-16 | 2000-04-11 | Stock; Mary C. | Test system for integrated circuits using a single memory for both the parallel and scan modes of testing |
US6070260A (en) | 1998-09-17 | 2000-05-30 | Xilinx, Inc. | Test methodology based on multiple skewed scan clocks |
US6418545B1 (en) * | 1999-06-04 | 2002-07-09 | Koninklijke Philips Electronics N.V. | System and method to reduce scan test pins on an integrated circuit |
TW484016B (en) * | 1999-07-28 | 2002-04-21 | Hitachi Ltd | Semiconductor integrated circuit and recording medium |
KR100697264B1 (ko) * | 1999-12-02 | 2007-03-21 | 삼성전자주식회사 | 딜레이 체인 회로를 이용한 반도체 장치의 테스트 회로 및그의 테스트 방법 |
US6516432B1 (en) * | 1999-12-22 | 2003-02-04 | International Business Machines Corporation | AC scan diagnostic method |
KR100448903B1 (ko) | 2000-01-28 | 2004-09-16 | 삼성전자주식회사 | 스캔신호 변환회로를 구비한 반도체 집적회로 장치 |
US6766487B2 (en) * | 2000-03-09 | 2004-07-20 | Texas Instruments Incorporated | Divided scan path with decode logic receiving select control signals |
US6591388B1 (en) * | 2000-04-18 | 2003-07-08 | International Business Machines Corporation | High speed sink/source register to reduce level sensitive scan design test time |
US6691268B1 (en) * | 2000-06-30 | 2004-02-10 | Oak Technology, Inc. | Method and apparatus for swapping state data with scan cells |
US6877119B2 (en) * | 2001-09-14 | 2005-04-05 | Stmicroelectronics Limited | Circuit scan output arrangement |
-
2002
- 2002-04-30 US US10/136,670 patent/US7249298B2/en not_active Expired - Lifetime
- 2002-07-17 GB GB0216628A patent/GB2388199B/en not_active Expired - Lifetime
- 2002-07-18 NL NL1021104A patent/NL1021104C2/nl not_active IP Right Cessation
- 2002-07-31 FR FR0209758A patent/FR2839156B1/fr not_active Expired - Lifetime
- 2002-07-31 TW TW091117123A patent/TWI231372B/zh not_active IP Right Cessation
- 2002-10-28 KR KR10-2002-0065939A patent/KR100486275B1/ko active IP Right Grant
-
2003
- 2003-03-25 JP JP2003083625A patent/JP4202165B2/ja not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
GB2388199B (en) | 2004-09-01 |
GB2388199A (en) | 2003-11-05 |
NL1021104C2 (nl) | 2005-09-07 |
US20030204802A1 (en) | 2003-10-30 |
JP4202165B2 (ja) | 2008-12-24 |
JP2003329742A (ja) | 2003-11-19 |
US7249298B2 (en) | 2007-07-24 |
FR2839156A1 (fr) | 2003-10-31 |
TWI231372B (en) | 2005-04-21 |
GB0216628D0 (en) | 2002-08-28 |
KR100486275B1 (ko) | 2005-04-29 |
KR20030085459A (ko) | 2003-11-05 |
NL1021104A1 (nl) | 2003-10-31 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 15 |
|
PLFP | Fee payment |
Year of fee payment: 16 |
|
PLFP | Fee payment |
Year of fee payment: 17 |
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PLFP | Fee payment |
Year of fee payment: 19 |
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PLFP | Fee payment |
Year of fee payment: 20 |