FR2834125B1 - Dispositif a semi-conducteurs comportant un isolant en tranchee et procede pour la fabrication de ce dispositif - Google Patents
Dispositif a semi-conducteurs comportant un isolant en tranchee et procede pour la fabrication de ce dispositifInfo
- Publication number
- FR2834125B1 FR2834125B1 FR0211175A FR0211175A FR2834125B1 FR 2834125 B1 FR2834125 B1 FR 2834125B1 FR 0211175 A FR0211175 A FR 0211175A FR 0211175 A FR0211175 A FR 0211175A FR 2834125 B1 FR2834125 B1 FR 2834125B1
- Authority
- FR
- France
- Prior art keywords
- manufacturing
- semiconductor device
- same
- trench insulation
- trench
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Fee Related
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having at least one potential-jump barrier or surface barrier, e.g. PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic System or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/26—Bombardment with radiation
- H01L21/263—Bombardment with radiation with high-energy radiation
- H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
- H01L21/26506—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors
- H01L21/26513—Bombardment with radiation with high-energy radiation producing ion implantation in group IV semiconductors of electrically active species
- H01L21/2652—Through-implantation
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76283—Lateral isolation by refilling of trenches with dielectric material
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
- H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
- H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
- H01L21/84—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being other than a semiconductor body, e.g. being an insulating body
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
- H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
- H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
- H01L27/1203—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body the substrate comprising an insulating body on a semiconductor body, e.g. SOI
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP2001387522A JP4139105B2 (ja) | 2001-12-20 | 2001-12-20 | 半導体装置の製造方法 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2834125A1 FR2834125A1 (fr) | 2003-06-27 |
FR2834125B1 true FR2834125B1 (fr) | 2005-06-17 |
Family
ID=19188076
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR0211175A Expired - Fee Related FR2834125B1 (fr) | 2001-12-20 | 2002-09-10 | Dispositif a semi-conducteurs comportant un isolant en tranchee et procede pour la fabrication de ce dispositif |
Country Status (5)
Country | Link |
---|---|
US (3) | US6875663B2 (fr) |
JP (1) | JP4139105B2 (fr) |
KR (1) | KR100487045B1 (fr) |
FR (1) | FR2834125B1 (fr) |
TW (1) | TW552715B (fr) |
Families Citing this family (31)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JP4139105B2 (ja) * | 2001-12-20 | 2008-08-27 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US7432136B2 (en) * | 2002-05-06 | 2008-10-07 | Advanced Micro Devices, Inc. | Transistors with controllable threshold voltages, and various methods of making and operating same |
US7129142B2 (en) * | 2002-06-11 | 2006-10-31 | Advanced Micro Devices, Inc. | Method of forming doped regions in the bulk substrate of an SOI substrate to control the operational characteristics of transistors formed thereabove, and an integrated circuit device comprising same |
KR100525797B1 (ko) * | 2003-06-18 | 2005-11-02 | 동부아남반도체 주식회사 | 소자분리막 구조 및 제조 방법 |
KR100602085B1 (ko) * | 2003-12-31 | 2006-07-14 | 동부일렉트로닉스 주식회사 | 반도체 소자 및 그의 제조 방법 |
JP4291197B2 (ja) * | 2004-04-06 | 2009-07-08 | エルピーダメモリ株式会社 | 半導体装置及びその製造方法 |
JP4974474B2 (ja) * | 2004-06-22 | 2012-07-11 | ルネサスエレクトロニクス株式会社 | 半導体装置およびその製造方法 |
US7491614B2 (en) * | 2005-01-13 | 2009-02-17 | International Business Machines Corporation | Methods for forming channel stop for deep trench isolation prior to deep trench etch |
JP4783050B2 (ja) * | 2005-04-13 | 2011-09-28 | パナソニック株式会社 | 半導体装置及びその製造方法 |
JP2006319164A (ja) * | 2005-05-13 | 2006-11-24 | Renesas Technology Corp | 半導体装置の製造方法 |
KR100677998B1 (ko) * | 2005-09-30 | 2007-02-02 | 동부일렉트로닉스 주식회사 | 반도체 소자의 셸로우 트렌치 소자분리막 제조 방법 |
US7986029B2 (en) * | 2005-11-08 | 2011-07-26 | Taiwan Semiconductor Manufacturing Company, Ltd. | Dual SOI structure |
US20070161150A1 (en) * | 2005-12-28 | 2007-07-12 | Intel Corporation | Forming ultra dense 3-D interconnect structures |
US7648869B2 (en) * | 2006-01-12 | 2010-01-19 | International Business Machines Corporation | Method of fabricating semiconductor structures for latch-up suppression |
US20070158779A1 (en) * | 2006-01-12 | 2007-07-12 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a buried damage layer |
US7276768B2 (en) * | 2006-01-26 | 2007-10-02 | International Business Machines Corporation | Semiconductor structures for latch-up suppression and methods of forming such semiconductor structures |
US7491618B2 (en) * | 2006-01-26 | 2009-02-17 | International Business Machines Corporation | Methods and semiconductor structures for latch-up suppression using a conductive region |
US20070194403A1 (en) * | 2006-02-23 | 2007-08-23 | International Business Machines Corporation | Methods for fabricating semiconductor device structures with reduced susceptibility to latch-up and semiconductor device structures formed by the methods |
US7754513B2 (en) * | 2007-02-28 | 2010-07-13 | International Business Machines Corporation | Latch-up resistant semiconductor structures on hybrid substrates and methods for forming such semiconductor structures |
US7818702B2 (en) * | 2007-02-28 | 2010-10-19 | International Business Machines Corporation | Structure incorporating latch-up resistant semiconductor device structures on hybrid substrates |
US20090065841A1 (en) * | 2007-09-06 | 2009-03-12 | Assaf Shappir | SILICON OXY-NITRIDE (SiON) LINER, SUCH AS OPTIONALLY FOR NON-VOLATILE MEMORY CELLS |
TWI346375B (en) * | 2007-09-12 | 2011-08-01 | Nanya Technology Corp | Method of fabricating a semiconductor device |
US8115254B2 (en) * | 2007-09-25 | 2012-02-14 | International Business Machines Corporation | Semiconductor-on-insulator structures including a trench containing an insulator stressor plug and method of fabricating same |
US8492846B2 (en) | 2007-11-15 | 2013-07-23 | International Business Machines Corporation | Stress-generating shallow trench isolation structure having dual composition |
US7824948B2 (en) * | 2009-01-21 | 2010-11-02 | Taiwan Semiconductor Manufacturing Company, Ltd. | Method and structure for reducing cross-talk in image sensor devices |
JP5465907B2 (ja) * | 2009-03-27 | 2014-04-09 | ラピスセミコンダクタ株式会社 | 半導体装置 |
JP5558243B2 (ja) * | 2010-07-21 | 2014-07-23 | パナソニック株式会社 | 半導体装置 |
KR102274182B1 (ko) * | 2014-08-01 | 2021-07-06 | 삼성전자주식회사 | 반도체 장치와 이를 위한 제조 방법 |
JP6316725B2 (ja) * | 2014-10-03 | 2018-04-25 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
JP6783703B2 (ja) * | 2017-05-29 | 2020-11-11 | ルネサスエレクトロニクス株式会社 | 半導体装置の製造方法 |
EP3654861A4 (fr) | 2017-07-21 | 2021-07-21 | National Taiwan University Hospital | Système auxiliaire comportant un dispositif d'échappement pour chirurgie |
Family Cites Families (43)
Publication number | Priority date | Publication date | Assignee | Title |
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CH332422A (de) | 1954-04-21 | 1958-09-15 | Weger Karl | Reinigungsgerät |
US4571819A (en) | 1984-11-01 | 1986-02-25 | Ncr Corporation | Method for forming trench isolation structures |
JPH01194436A (ja) * | 1988-01-29 | 1989-08-04 | Nec Yamaguchi Ltd | 半導体装置 |
US5240874A (en) * | 1992-10-20 | 1993-08-31 | Micron Semiconductor, Inc. | Semiconductor wafer processing method of forming channel stops and method of forming SRAM circuitry |
JP3311044B2 (ja) * | 1992-10-27 | 2002-08-05 | 株式会社東芝 | 半導体装置の製造方法 |
JPH0773128B2 (ja) * | 1992-11-19 | 1995-08-02 | 日本電気株式会社 | 半導体装置の製造方法 |
JP2978345B2 (ja) * | 1992-11-26 | 1999-11-15 | 三菱電機株式会社 | 半導体装置の製造方法 |
US5433794A (en) * | 1992-12-10 | 1995-07-18 | Micron Technology, Inc. | Spacers used to form isolation trenches with improved corners |
JP3157357B2 (ja) * | 1993-06-14 | 2001-04-16 | 株式会社東芝 | 半導体装置 |
JP3247801B2 (ja) | 1993-07-27 | 2002-01-21 | 三菱電機株式会社 | Soi構造を有する半導体装置およびその製造方法 |
US5571819A (en) * | 1994-11-22 | 1996-11-05 | Sabb; Annmarie L. | Imidazopyridines as muscarinic agents |
US5494851A (en) * | 1995-01-18 | 1996-02-27 | Micron Technology, Inc. | Semiconductor processing method of providing dopant impurity into a semiconductor substrate |
JP2679683B2 (ja) * | 1995-04-28 | 1997-11-19 | 日本電気株式会社 | 半導体装置の製造方法 |
KR0149942B1 (ko) * | 1995-06-24 | 1999-04-15 | 양승택 | Cmos 소자의 제조방법 |
US5899712A (en) | 1995-08-21 | 1999-05-04 | Hyundai Electronics Industries Co., Ltd. | Method for fabricating silicon-on-insulator device |
KR100197656B1 (ko) | 1995-12-29 | 1999-07-01 | 김영환 | 반도체 에스.오.아이.소자의 제조방법 |
US5679602A (en) * | 1996-01-29 | 1997-10-21 | United Microelectronics Corporation | Method of forming MOSFET devices with heavily doped local channel stops |
US5904551A (en) * | 1996-04-12 | 1999-05-18 | Lsi Logic Corporation | Process for low energy implantation of semiconductor substrate using channeling to form retrograde wells |
JP3529220B2 (ja) | 1996-04-26 | 2004-05-24 | 株式会社ルネサステクノロジ | 半導体装置及びその製造方法 |
US5861338A (en) * | 1997-01-21 | 1999-01-19 | Advanced Micro Devices, Inc. | Channel stop implant profile shaping scheme for field isolation |
US5728621A (en) * | 1997-04-28 | 1998-03-17 | Chartered Semiconductor Manufacturing Pte Ltd | Method for shallow trench isolation |
US5731241A (en) * | 1997-05-15 | 1998-03-24 | Taiwan Semiconductor Manufacturing Company, Ltd. | Self-aligned sacrificial oxide for shallow trench isolation |
US6057209A (en) * | 1997-07-10 | 2000-05-02 | Advanced Micro Devices, Inc. | Semiconductor device having a nitrogen bearing isolation region |
US5801082A (en) * | 1997-08-18 | 1998-09-01 | Vanguard International Semiconductor Corporation | Method for making improved shallow trench isolation with dielectric studs for semiconductor integrated circuits |
JP4187808B2 (ja) | 1997-08-25 | 2008-11-26 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
US6096612A (en) * | 1998-04-30 | 2000-08-01 | Texas Instruments Incorporated | Increased effective transistor width using double sidewall spacers |
US6080628A (en) * | 1998-05-15 | 2000-06-27 | Vanguard International Semiconductor Corporation | Method of forming shallow trench isolation for integrated circuit applications |
US6277682B1 (en) * | 1998-08-25 | 2001-08-21 | Texas Instruments Incorporated | Source drain implant process for mixed voltage CMOS devices |
US6346442B1 (en) * | 1999-02-04 | 2002-02-12 | Tower Semiconductor Ltd. | Methods for fabricating a semiconductor chip having CMOS devices and a fieldless array |
EP1122788B1 (fr) * | 1999-07-02 | 2009-03-25 | Mitsubishi Materials Silicon Corporation | Méthode de fabrication d'un substrat soi |
US6096623A (en) * | 1999-09-09 | 2000-08-01 | United Semiconductor Corp. | Method for forming shallow trench isolation structure |
JP2001111056A (ja) * | 1999-10-06 | 2001-04-20 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
JP2001144170A (ja) * | 1999-11-11 | 2001-05-25 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
US6277710B1 (en) * | 1999-11-15 | 2001-08-21 | Chartered Semiconductor Manufacturing Ltd. | Method of forming shallow trench isolation |
US6362035B1 (en) * | 2000-02-07 | 2002-03-26 | Taiwan Semiconductor Manufacturing Company | Channel stop ion implantation method for CMOS integrated circuits |
JP2001230315A (ja) | 2000-02-17 | 2001-08-24 | Mitsubishi Electric Corp | 半導体装置およびその製造方法 |
KR100327348B1 (en) * | 2000-07-26 | 2002-03-06 | Samsung Electronics Co Ltd | Semiconductor capable of decreasing junction leakage current and narrow width effect and fabricating method thereof |
SE519382C2 (sv) * | 2000-11-03 | 2003-02-25 | Ericsson Telefon Ab L M | Integrering av självinriktade MOS-högspänningskomponenter samt halvledarstruktur innefattande sådana |
US6614062B2 (en) * | 2001-01-17 | 2003-09-02 | Motorola, Inc. | Semiconductor tiling structure and method of formation |
JP4139105B2 (ja) * | 2001-12-20 | 2008-08-27 | 株式会社ルネサステクノロジ | 半導体装置の製造方法 |
JP2003243662A (ja) | 2002-02-14 | 2003-08-29 | Mitsubishi Electric Corp | 半導体装置およびその製造方法、半導体ウェハ |
US6734082B2 (en) * | 2002-08-06 | 2004-05-11 | Chartered Semiconductor Manufacturing Ltd. | Method of forming a shallow trench isolation structure featuring a group of insulator liner layers located on the surfaces of a shallow trench shape |
KR100461975B1 (ko) * | 2002-12-27 | 2004-12-17 | 매그나칩 반도체 유한회사 | 이미지센서의 트렌치 소자분리막 형성방법 |
-
2001
- 2001-12-20 JP JP2001387522A patent/JP4139105B2/ja not_active Expired - Fee Related
-
2002
- 2002-08-12 TW TW091118074A patent/TW552715B/zh not_active IP Right Cessation
- 2002-09-06 KR KR10-2002-0053741A patent/KR100487045B1/ko not_active IP Right Cessation
- 2002-09-09 US US10/237,022 patent/US6875663B2/en not_active Expired - Fee Related
- 2002-09-10 FR FR0211175A patent/FR2834125B1/fr not_active Expired - Fee Related
-
2004
- 2004-12-15 US US11/011,655 patent/US7183167B2/en not_active Expired - Fee Related
-
2006
- 2006-10-05 US US11/543,213 patent/US7494883B2/en not_active Expired - Fee Related
Also Published As
Publication number | Publication date |
---|---|
US20070032001A1 (en) | 2007-02-08 |
US20050101091A1 (en) | 2005-05-12 |
US20030119245A1 (en) | 2003-06-26 |
US7183167B2 (en) | 2007-02-27 |
US6875663B2 (en) | 2005-04-05 |
FR2834125A1 (fr) | 2003-06-27 |
KR100487045B1 (ko) | 2005-05-03 |
US7494883B2 (en) | 2009-02-24 |
TW552715B (en) | 2003-09-11 |
JP2003188250A (ja) | 2003-07-04 |
KR20030052236A (ko) | 2003-06-26 |
JP4139105B2 (ja) | 2008-08-27 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
TP | Transmission of property | ||
ST | Notification of lapse |
Effective date: 20150529 |