FR2775387B1 - Dispositif a semiconducteur ayant une structure soi et procede de fabrication - Google Patents

Dispositif a semiconducteur ayant une structure soi et procede de fabrication

Info

Publication number
FR2775387B1
FR2775387B1 FR9811927A FR9811927A FR2775387B1 FR 2775387 B1 FR2775387 B1 FR 2775387B1 FR 9811927 A FR9811927 A FR 9811927A FR 9811927 A FR9811927 A FR 9811927A FR 2775387 B1 FR2775387 B1 FR 2775387B1
Authority
FR
France
Prior art keywords
layer
aluminum pad
semiconductor device
soi structure
nickel
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9811927A
Other languages
English (en)
Other versions
FR2775387A1 (fr
Inventor
Shigenobu Maeda
Tadashi Nishimura
Kazuhito Tsutsumi
Shigeto Maegawa
Yuuichi Hirano
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Publication of FR2775387A1 publication Critical patent/FR2775387A1/fr
Application granted granted Critical
Publication of FR2775387B1 publication Critical patent/FR2775387B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
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    • H01L23/00Details of semiconductor or other solid state devices
    • H01L23/552Protection against radiation, e.g. light or electromagnetic waves
    • H01L23/556Protection against radiation, e.g. light or electromagnetic waves against alpha rays
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    • H01L24/02Bonding areas ; Manufacturing methods related thereto
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    • H01L24/04Structure, shape, material or disposition of the bonding areas prior to the connecting process
    • H01L24/05Structure, shape, material or disposition of the bonding areas prior to the connecting process of an individual bonding area
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    • H01L2224/02Bonding areas; Manufacturing methods related thereto
    • H01L2224/03Manufacturing methods
    • H01L2224/039Methods of manufacturing bonding areas involving a specific sequence of method steps
    • H01L2224/03914Methods of manufacturing bonding areas involving a specific sequence of method steps the bonding area, e.g. under bump metallisation [UBM], being used as a mask for patterning other parts
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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Toxicology (AREA)
  • Health & Medical Sciences (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Thin Film Transistor (AREA)
  • Wire Bonding (AREA)
FR9811927A 1998-02-26 1998-09-24 Dispositif a semiconducteur ayant une structure soi et procede de fabrication Expired - Fee Related FR2775387B1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10045459A JPH11243208A (ja) 1998-02-26 1998-02-26 半導体装置及びその製造方法

Publications (2)

Publication Number Publication Date
FR2775387A1 FR2775387A1 (fr) 1999-08-27
FR2775387B1 true FR2775387B1 (fr) 2002-09-06

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Application Number Title Priority Date Filing Date
FR9811927A Expired - Fee Related FR2775387B1 (fr) 1998-02-26 1998-09-24 Dispositif a semiconducteur ayant une structure soi et procede de fabrication

Country Status (6)

Country Link
US (2) US6459125B2 (fr)
JP (1) JPH11243208A (fr)
KR (2) KR19990071421A (fr)
DE (1) DE19842441B4 (fr)
FR (1) FR2775387B1 (fr)
TW (1) TW382817B (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
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JPH11243208A (ja) * 1998-02-26 1999-09-07 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP3824845B2 (ja) * 2000-06-21 2006-09-20 セイコーエプソン株式会社 Lcdドライバicチップ
JP2002270611A (ja) * 2001-03-14 2002-09-20 Mitsubishi Electric Corp 半導体装置及びその製造方法
JP2003045958A (ja) * 2001-07-27 2003-02-14 Denso Corp 半導体装置及びその製造方法
US6762503B2 (en) * 2002-08-29 2004-07-13 Micron Technology, Inc. Innovative solder ball pad structure to ease design rule, methods of fabricating same and substrates, electronic device assemblies and systems employing same
US6841874B1 (en) * 2002-11-01 2005-01-11 Amkor Technology, Inc. Wafer-level chip-scale package
DE10308275A1 (de) 2003-02-26 2004-09-16 Advanced Micro Devices, Inc., Sunnyvale Strahlungsresistentes Halbleiterbauteil
US8093097B2 (en) * 2005-06-15 2012-01-10 Nxp B.V. Layer sequence and method of manufacturing a layer sequence
US7736915B2 (en) * 2006-02-21 2010-06-15 International Business Machines Corporation Method for neutralizing trapped charge in a charge accumulation layer of a semiconductor structure
WO2009027888A2 (fr) * 2007-08-24 2009-03-05 Nxp B.V. Structure apte au brasage
JP2009064812A (ja) * 2007-09-04 2009-03-26 Panasonic Corp 半導体装置の電極構造およびその関連技術
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US6459125B2 (en) 2002-10-01
FR2775387A1 (fr) 1999-08-27
DE19842441B4 (de) 2004-07-29
DE19842441A1 (de) 1999-09-09
KR100377893B1 (ko) 2003-03-29
JPH11243208A (ja) 1999-09-07
KR20010072669A (ko) 2001-07-31
US20020003259A1 (en) 2002-01-10
US20020110954A1 (en) 2002-08-15

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