FR2773233B1 - Circuit pour masquer des donnees et procede pour masquer des donnees d'un dispositif de memoire a semi-conducteurs - Google Patents
Circuit pour masquer des donnees et procede pour masquer des donnees d'un dispositif de memoire a semi-conducteursInfo
- Publication number
- FR2773233B1 FR2773233B1 FR9814486A FR9814486A FR2773233B1 FR 2773233 B1 FR2773233 B1 FR 2773233B1 FR 9814486 A FR9814486 A FR 9814486A FR 9814486 A FR9814486 A FR 9814486A FR 2773233 B1 FR2773233 B1 FR 2773233B1
- Authority
- FR
- France
- Prior art keywords
- masking data
- circuit
- memory device
- semiconductor memory
- masking
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C7/00—Arrangements for writing information into, or reading information out from, a digital store
- G11C7/10—Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
- G11C7/1006—Data managing, e.g. manipulating data before writing or reading out, data bus switches or control circuits therefor
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
KR1019970060814A KR100252048B1 (ko) | 1997-11-18 | 1997-11-18 | 반도체 메모리장치의 데이터 마스킹 회로 및 데이터 마스킹방법 |
Publications (2)
Publication Number | Publication Date |
---|---|
FR2773233A1 FR2773233A1 (fr) | 1999-07-02 |
FR2773233B1 true FR2773233B1 (fr) | 2000-08-18 |
Family
ID=19524980
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FR9814486A Expired - Lifetime FR2773233B1 (fr) | 1997-11-18 | 1998-11-18 | Circuit pour masquer des donnees et procede pour masquer des donnees d'un dispositif de memoire a semi-conducteurs |
Country Status (7)
Country | Link |
---|---|
US (1) | US6034916A (ja) |
JP (1) | JP4070051B2 (ja) |
KR (1) | KR100252048B1 (ja) |
DE (1) | DE19852986B4 (ja) |
FR (1) | FR2773233B1 (ja) |
GB (1) | GB2331608B (ja) |
TW (1) | TW397994B (ja) |
Families Citing this family (71)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6401167B1 (en) | 1997-10-10 | 2002-06-04 | Rambus Incorporated | High performance cost optimized memory |
JP4079507B2 (ja) * | 1998-05-12 | 2008-04-23 | 富士通株式会社 | メモリ制御システムおよびメモリ制御方法 |
TW426847B (en) * | 1998-05-21 | 2001-03-21 | Nippon Electric Co | Semiconductor memory device capable of securing large latch margin |
JP2000100160A (ja) * | 1998-09-18 | 2000-04-07 | Nec Corp | 同期型半導体メモリ |
KR100306883B1 (ko) * | 1998-12-22 | 2001-11-02 | 박종섭 | 반도체메모리장치의입력버퍼 |
JP2001035153A (ja) * | 1999-07-23 | 2001-02-09 | Fujitsu Ltd | 半導体記憶装置 |
US6279073B1 (en) * | 1999-09-30 | 2001-08-21 | Silicon Graphics, Inc. | Configurable synchronizer for double data rate synchronous dynamic random access memory |
US6741520B1 (en) * | 2000-03-16 | 2004-05-25 | Mosel Vitelic, Inc. | Integrated data input sorting and timing circuit for double data rate (DDR) dynamic random access memory (DRAM) devices |
JP4011833B2 (ja) * | 2000-06-30 | 2007-11-21 | 株式会社東芝 | 半導体メモリ |
GB2370667B (en) * | 2000-09-05 | 2003-02-12 | Samsung Electronics Co Ltd | Semiconductor memory device having altered clock frequency for address and/or command signals, and memory module and system having the same |
GB2379542B (en) * | 2000-09-05 | 2003-09-10 | Samsung Electronics Co Ltd | System comprising memory module |
US6708298B2 (en) * | 2001-01-23 | 2004-03-16 | International Business Machines Corporation | Method for guaranteeing a minimum data strobe valid window and a minimum data valid window for DDR memory devices |
US6662279B2 (en) * | 2001-03-07 | 2003-12-09 | Micron Technology, Inc. | DQ mask to force internal data to mask external data in a flash memory |
US6532180B2 (en) | 2001-06-20 | 2003-03-11 | Micron Technology, Inc. | Write data masking for higher speed DRAMs |
US6918016B1 (en) * | 2001-07-17 | 2005-07-12 | Advanced Micro Devices, Inc. | Method and apparatus for preventing data corruption during a memory access command postamble |
JP2003085974A (ja) * | 2001-09-13 | 2003-03-20 | Toshiba Corp | 半導体集積回路およびメモリシステム |
KR100427037B1 (ko) | 2001-09-24 | 2004-04-14 | 주식회사 하이닉스반도체 | 적응적 출력 드라이버를 갖는 반도체 기억장치 |
KR100422947B1 (ko) * | 2001-11-22 | 2004-03-16 | 주식회사 하이닉스반도체 | 버스트 리드 데이터의 출력방법 및 출력장치 |
US6931479B2 (en) * | 2003-03-04 | 2005-08-16 | Micron Technology, Inc. | Method and apparatus for multi-functional inputs of a memory device |
KR100543203B1 (ko) * | 2003-03-20 | 2006-01-20 | 주식회사 하이닉스반도체 | 유효 데이타 윈도우의 조절이 가능한 반도체 메모리장치의 데이타 출력 버퍼 |
KR100532956B1 (ko) * | 2003-06-28 | 2005-12-01 | 주식회사 하이닉스반도체 | Ddr sdram에서의 링잉 현상 방지 방법 |
KR100548563B1 (ko) * | 2003-06-30 | 2006-02-02 | 주식회사 하이닉스반도체 | Ddr sdram 에서의 라이트 링잉 현상을 마스크하기위한 데이타 패스 제어 장치 및 방법 |
JP4005000B2 (ja) | 2003-07-04 | 2007-11-07 | 株式会社東芝 | 半導体記憶装置及びデータ書き込み方法。 |
US6922367B2 (en) * | 2003-07-09 | 2005-07-26 | Micron Technology, Inc. | Data strobe synchronization circuit and method for double data rate, multi-bit writes |
KR100557636B1 (ko) * | 2003-12-23 | 2006-03-10 | 주식회사 하이닉스반도체 | 클럭신호를 이용한 데이터 스트로브 회로 |
US7082073B2 (en) * | 2004-12-03 | 2006-07-25 | Micron Technology, Inc. | System and method for reducing power consumption during extended refresh periods of dynamic random access memory devices |
US7139207B2 (en) * | 2005-02-25 | 2006-11-21 | Hewlett-Packard Development Company, L.P. | Memory interface methods and apparatus |
US7392338B2 (en) * | 2006-07-31 | 2008-06-24 | Metaram, Inc. | Interface circuit system and method for autonomously performing power management operations in conjunction with a plurality of memory circuits |
US9507739B2 (en) | 2005-06-24 | 2016-11-29 | Google Inc. | Configurable memory circuit system and method |
US8397013B1 (en) | 2006-10-05 | 2013-03-12 | Google Inc. | Hybrid memory module |
US9542352B2 (en) * | 2006-02-09 | 2017-01-10 | Google Inc. | System and method for reducing command scheduling constraints of memory circuits |
US9171585B2 (en) | 2005-06-24 | 2015-10-27 | Google Inc. | Configurable memory circuit system and method |
US7590796B2 (en) * | 2006-07-31 | 2009-09-15 | Metaram, Inc. | System and method for power management in memory systems |
US8130560B1 (en) | 2006-11-13 | 2012-03-06 | Google Inc. | Multi-rank partial width memory modules |
US8089795B2 (en) | 2006-02-09 | 2012-01-03 | Google Inc. | Memory module with memory stack and interface with enhanced capabilities |
US8055833B2 (en) | 2006-10-05 | 2011-11-08 | Google Inc. | System and method for increasing capacity, performance, and flexibility of flash storage |
US8796830B1 (en) | 2006-09-01 | 2014-08-05 | Google Inc. | Stackable low-profile lead frame package |
US8327104B2 (en) | 2006-07-31 | 2012-12-04 | Google Inc. | Adjusting the timing of signals associated with a memory system |
US8386722B1 (en) | 2008-06-23 | 2013-02-26 | Google Inc. | Stacked DIMM memory interface |
US8335894B1 (en) | 2008-07-25 | 2012-12-18 | Google Inc. | Configurable memory system with interface circuit |
US8041881B2 (en) | 2006-07-31 | 2011-10-18 | Google Inc. | Memory device with emulated characteristics |
US20080082763A1 (en) | 2006-10-02 | 2008-04-03 | Metaram, Inc. | Apparatus and method for power management of memory circuits by a system or component thereof |
US20080028136A1 (en) | 2006-07-31 | 2008-01-31 | Schakel Keith R | Method and apparatus for refresh management of memory modules |
US8077535B2 (en) | 2006-07-31 | 2011-12-13 | Google Inc. | Memory refresh apparatus and method |
US8111566B1 (en) | 2007-11-16 | 2012-02-07 | Google, Inc. | Optimal channel design for memory devices for providing a high-speed memory interface |
US8081474B1 (en) | 2007-12-18 | 2011-12-20 | Google Inc. | Embossed heat spreader |
US8244971B2 (en) | 2006-07-31 | 2012-08-14 | Google Inc. | Memory circuit system and method |
US8090897B2 (en) | 2006-07-31 | 2012-01-03 | Google Inc. | System and method for simulating an aspect of a memory circuit |
US10013371B2 (en) | 2005-06-24 | 2018-07-03 | Google Llc | Configurable memory circuit system and method |
US7609567B2 (en) | 2005-06-24 | 2009-10-27 | Metaram, Inc. | System and method for simulating an aspect of a memory circuit |
US7386656B2 (en) * | 2006-07-31 | 2008-06-10 | Metaram, Inc. | Interface circuit system and method for performing power management operations in conjunction with only a portion of a memory circuit |
US7515453B2 (en) * | 2005-06-24 | 2009-04-07 | Metaram, Inc. | Integrated memory core and memory interface circuit |
US8438328B2 (en) | 2008-02-21 | 2013-05-07 | Google Inc. | Emulation of abstracted DIMMs using abstracted DRAMs |
US8169233B2 (en) | 2009-06-09 | 2012-05-01 | Google Inc. | Programming of DIMM termination resistance values |
US8359187B2 (en) | 2005-06-24 | 2013-01-22 | Google Inc. | Simulating a different number of memory circuit devices |
US8060774B2 (en) * | 2005-06-24 | 2011-11-15 | Google Inc. | Memory systems and memory modules |
DE112006002300B4 (de) | 2005-09-02 | 2013-12-19 | Google, Inc. | Vorrichtung zum Stapeln von DRAMs |
US9632929B2 (en) | 2006-02-09 | 2017-04-25 | Google Inc. | Translating an address associated with a command communicated between a system and memory circuits |
KR100784905B1 (ko) * | 2006-05-04 | 2007-12-11 | 주식회사 하이닉스반도체 | 반도체 메모리의 데이터 입력 장치 및 방법 |
US7724589B2 (en) | 2006-07-31 | 2010-05-25 | Google Inc. | System and method for delaying a signal communicated from a system to at least one of a plurality of memory circuits |
KR100800382B1 (ko) * | 2006-08-17 | 2008-02-01 | 삼성전자주식회사 | 반도체 메모리 장치에서의 신호제어방법 및 그에 따른컬럼선택라인 인에이블 신호 발생회로 |
JP2008198280A (ja) * | 2007-02-13 | 2008-08-28 | Elpida Memory Inc | 半導体記憶装置及びその動作方法 |
US8209479B2 (en) | 2007-07-18 | 2012-06-26 | Google Inc. | Memory circuit system and method |
US8080874B1 (en) | 2007-09-14 | 2011-12-20 | Google Inc. | Providing additional space between an integrated circuit and a circuit board for positioning a component therebetween |
KR101191942B1 (ko) * | 2007-10-10 | 2012-10-17 | 삼성전자주식회사 | 반도체 메모리 장치 및 반도체 메모리 장치의 명령 입력방법 |
JP4600467B2 (ja) * | 2007-12-03 | 2010-12-15 | 富士通セミコンダクター株式会社 | 電子装置及びダブル・データ・レート・シンクロナス・ダイナミック・ランダム・アクセス・メモリ |
US8149643B2 (en) | 2008-10-23 | 2012-04-03 | Cypress Semiconductor Corporation | Memory device and method |
KR20100101449A (ko) * | 2009-03-09 | 2010-09-17 | 삼성전자주식회사 | 메모리 장치, 그것의 마스크 데이터 전송 방법 및 입력 데이터 정렬 방법 |
KR101796116B1 (ko) | 2010-10-20 | 2017-11-10 | 삼성전자 주식회사 | 반도체 장치, 이를 포함하는 메모리 모듈, 메모리 시스템 및 그 동작방법 |
KR102617240B1 (ko) * | 2017-02-28 | 2023-12-27 | 에스케이하이닉스 주식회사 | 반도체 장치 |
US11295808B2 (en) | 2020-01-21 | 2022-04-05 | Samsung Electronics Co., Ltd. | Memory device transmitting and receiving data at high speed and low power |
Family Cites Families (12)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
KR960003526B1 (ko) * | 1992-10-02 | 1996-03-14 | 삼성전자주식회사 | 반도체 메모리장치 |
JPH05325545A (ja) * | 1992-05-25 | 1993-12-10 | Mitsubishi Electric Corp | 半導体記憶装置 |
KR950010564B1 (en) * | 1992-10-02 | 1995-09-19 | Samsung Electronics Co Ltd | Data output buffer of synchronous semiconductor memory device |
JPH06202933A (ja) * | 1992-12-28 | 1994-07-22 | Toshiba Corp | 同期式大規模集積回路記憶装置 |
US5539696A (en) * | 1994-01-31 | 1996-07-23 | Patel; Vipul C. | Method and apparatus for writing data in a synchronous memory having column independent sections and a method and apparatus for performing write mask operations |
KR970001699B1 (ko) * | 1994-03-03 | 1997-02-13 | 삼성전자 주식회사 | 자동프리차아지기능을 가진 동기식 반도체메모리장치 |
KR0122099B1 (ko) * | 1994-03-03 | 1997-11-26 | 김광호 | 라이트레이턴시제어기능을 가진 동기식 반도체메모리장치 |
JPH0955080A (ja) * | 1995-08-08 | 1997-02-25 | Fujitsu Ltd | 半導体記憶装置及び半導体記憶装置のセル情報の書き込み及び読み出し方法 |
KR0154726B1 (ko) * | 1995-09-19 | 1998-12-01 | 김광호 | 프리페치방식의 컬럼디코더 및 이를 구비한 반도체 메모리 장치 |
JP2904076B2 (ja) * | 1995-11-10 | 1999-06-14 | 日本電気株式会社 | 半導体記憶装置 |
JPH1069430A (ja) * | 1996-08-29 | 1998-03-10 | Nec Ic Microcomput Syst Ltd | 半導体記憶装置 |
JPH11203890A (ja) * | 1998-01-05 | 1999-07-30 | Mitsubishi Electric Corp | 半導体記憶装置 |
-
1997
- 1997-11-18 KR KR1019970060814A patent/KR100252048B1/ko not_active IP Right Cessation
-
1998
- 1998-05-26 TW TW087108149A patent/TW397994B/zh not_active IP Right Cessation
- 1998-09-24 JP JP27025498A patent/JP4070051B2/ja not_active Expired - Lifetime
- 1998-10-14 US US09/172,415 patent/US6034916A/en not_active Expired - Lifetime
- 1998-11-17 DE DE19852986A patent/DE19852986B4/de not_active Expired - Lifetime
- 1998-11-18 FR FR9814486A patent/FR2773233B1/fr not_active Expired - Lifetime
- 1998-11-18 GB GB9825292A patent/GB2331608B/en not_active Expired - Lifetime
Also Published As
Publication number | Publication date |
---|---|
JP4070051B2 (ja) | 2008-04-02 |
FR2773233A1 (fr) | 1999-07-02 |
KR100252048B1 (ko) | 2000-05-01 |
DE19852986B4 (de) | 2011-02-03 |
JPH11176164A (ja) | 1999-07-02 |
TW397994B (en) | 2000-07-11 |
GB2331608A (en) | 1999-05-26 |
GB2331608B (en) | 2001-09-12 |
GB9825292D0 (en) | 1999-01-13 |
KR19990040440A (ko) | 1999-06-05 |
US6034916A (en) | 2000-03-07 |
DE19852986A1 (de) | 1999-05-20 |
Similar Documents
Publication | Publication Date | Title |
---|---|---|
FR2773233B1 (fr) | Circuit pour masquer des donnees et procede pour masquer des donnees d'un dispositif de memoire a semi-conducteurs | |
FR2774209B1 (fr) | Procede de controle du circuit de lecture d'un plan memoire et dispositif de memoire correspondant | |
FR2679368B1 (fr) | Memoire tampon de sortie de donnees d'un dispositif de memoire a semiconducteurs. | |
FR2625038B1 (fr) | Procede et dispositif de refroidissement d'un boitier de circuit integre | |
FR2736474B1 (fr) | Procede pour fabriquer un dispositif laser a semi-conducteur et dispositif laser a semi-conducteur | |
FR2772491B1 (fr) | Systeme et procede pour simuler un dispositif de memorisation d'ordinateur | |
FR2781065B1 (fr) | Procede de placement-routage d'un circuit d'horloge globale sur un circuit integre, et dispositifs associes | |
FR2687003B1 (fr) | Circuit de sortie de donnees pour un dispositif de memoire a semi-conducteur. | |
FR2801419B1 (fr) | Procede et dispositif de lecture pour memoire en circuit integre | |
FR2656441B1 (fr) | Procede securise d'ecriture rapide d'informations pour dispositif de memoire de masse. | |
FR2765983B1 (fr) | Signal de donnees de modification d'une scene graphique, procede et dispositif correspondants | |
FR2728369B1 (fr) | Procede et dispositif pour accroitre la securite d'un circuit integre | |
GB9601211D0 (en) | Semiconductor memory device and data writing method thereof | |
FR2733065B1 (fr) | Procede et circuit de lecture anticipee d'instrutions/ donnees utilisant un cache de lecture anticipee non consulte | |
FR2728999B1 (fr) | Circuit tampon de sortie de donnees d'un dispositif de memoire a semi-conducteurs | |
FR2787212B1 (fr) | Circuit pour remettre a l'etat initial une paire de bus de donnees d'un dispositif de memoire a semiconducteur | |
FR2765984B1 (fr) | Signal de donnees d'animation d'une scene graphique a objet de quantification, procede et dispositif correspondants | |
FR2749415B1 (fr) | Dispositif et procede a support de donnees | |
FR2764392B1 (fr) | Procede d'identification d'un circuit integre et dispositif associe | |
FR2752494B1 (fr) | Dispositif de memoire a semiconducteurs et structure d'electrode de condensateur pour ce dispositif | |
FR2722051B1 (fr) | Procede et dispositif de donnees asynchrones sur un signal numerique | |
FR2765982B1 (fr) | Signal de donnees d'animation d'une scene graphique, procede et dispositif correspondants | |
FR2790886B1 (fr) | Procede et dispositif d'adressage sequentiel des entrees d'un multiplexeur de circuit d'acquisition de donnees | |
FR2722593B1 (fr) | Dispositif recepteur pour une carte a memoire electronique | |
FR2527880B1 (fr) | Dispositif d'ecriture pour circuit memoire |
Legal Events
Date | Code | Title | Description |
---|---|---|---|
PLFP | Fee payment |
Year of fee payment: 18 |
|
PLFP | Fee payment |
Year of fee payment: 19 |
|
PLFP | Fee payment |
Year of fee payment: 20 |