FR2675946B1 - Procede de montage d'une puce a circuit integre sur un substrat de cablage. - Google Patents

Procede de montage d'une puce a circuit integre sur un substrat de cablage.

Info

Publication number
FR2675946B1
FR2675946B1 FR9105368A FR9105368A FR2675946B1 FR 2675946 B1 FR2675946 B1 FR 2675946B1 FR 9105368 A FR9105368 A FR 9105368A FR 9105368 A FR9105368 A FR 9105368A FR 2675946 B1 FR2675946 B1 FR 2675946B1
Authority
FR
France
Prior art keywords
chip
mounting
integrated circuit
wiring substrate
wiring
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
FR9105368A
Other languages
English (en)
Other versions
FR2675946A1 (fr
Inventor
Massiot Michel
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
SOREP
Original Assignee
SOREP
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by SOREP filed Critical SOREP
Priority to FR9105368A priority Critical patent/FR2675946B1/fr
Priority to PCT/FR1992/000327 priority patent/WO1992020101A1/fr
Publication of FR2675946A1 publication Critical patent/FR2675946A1/fr
Application granted granted Critical
Publication of FR2675946B1 publication Critical patent/FR2675946B1/fr
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/80—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected
    • H01L24/81—Methods for connecting semiconductor or other solid state bodies using means for bonding being attached to, or being formed on, the surface to be connected using a bump connector
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L24/00—Arrangements for connecting or disconnecting semiconductor or solid-state bodies; Methods or apparatus related thereto
    • H01L24/74—Apparatus for manufacturing arrangements for connecting or disconnecting semiconductor or solid-state bodies
    • H01L24/75—Apparatus for connecting with bump connectors or layer connectors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/11—Manufacturing methods
    • H01L2224/113—Manufacturing methods by local deposition of the material of the bump connector
    • H01L2224/1133—Manufacturing methods by local deposition of the material of the bump connector in solid form
    • H01L2224/1134—Stud bumping, i.e. using a wire-bonding apparatus
    • H—ELECTRICITY
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    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
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    • H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10—Bump connectors; Manufacturing methods related thereto
    • H01L2224/12—Structure, shape, material or disposition of the bump connectors prior to the connecting process
    • H01L2224/13—Structure, shape, material or disposition of the bump connectors prior to the connecting process of an individual bump connector
    • H01L2224/13001—Core members of the bump connector
    • H01L2224/13099—Material
    • H01L2224/131—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof
    • H01L2224/13101—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron [B], silicon [Si], germanium [Ge], arsenic [As], antimony [Sb], tellurium [Te] and polonium [Po], and alloys thereof the principal constituent melting at a temperature of less than 400°C
    • H01L2224/13109—Indium [In] as principal constituent
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    • H01L2224/161—Disposition
    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16235—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a via metallisation of the item
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    • H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
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    • H01L2224/16151—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • H01L2224/16237—Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation the bump connector connecting to a bonding area disposed in a recess of the surface of the item
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    • H01L2224/42—Wire connectors; Manufacturing methods related thereto
    • H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
    • H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
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    • H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
    • H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
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    • H01L2224/7525—Means for applying energy, e.g. heating means
    • H01L2224/753—Means for applying energy, e.g. heating means by means of pressure
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    • H01L2924/11—Device type
    • H01L2924/14—Integrated circuits
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1515—Shape
    • H01L2924/15153—Shape the die mounting substrate comprising a recess for hosting the device
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    • H01L2924/15—Details of package parts other than the semiconductor or other solid state devices to be connected
    • H01L2924/151—Die mounting substrate
    • H01L2924/1517—Multilayer substrate

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Wire Bonding (AREA)
FR9105368A 1991-04-25 1991-04-25 Procede de montage d'une puce a circuit integre sur un substrat de cablage. Expired - Fee Related FR2675946B1 (fr)

Priority Applications (2)

Application Number Priority Date Filing Date Title
FR9105368A FR2675946B1 (fr) 1991-04-25 1991-04-25 Procede de montage d'une puce a circuit integre sur un substrat de cablage.
PCT/FR1992/000327 WO1992020101A1 (fr) 1991-04-25 1992-04-14 Procede de montage d'une puce a circuit integre sur un substrat de cablage

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
FR9105368A FR2675946B1 (fr) 1991-04-25 1991-04-25 Procede de montage d'une puce a circuit integre sur un substrat de cablage.

Publications (2)

Publication Number Publication Date
FR2675946A1 FR2675946A1 (fr) 1992-10-30
FR2675946B1 true FR2675946B1 (fr) 1993-08-20

Family

ID=9412437

Family Applications (1)

Application Number Title Priority Date Filing Date
FR9105368A Expired - Fee Related FR2675946B1 (fr) 1991-04-25 1991-04-25 Procede de montage d'une puce a circuit integre sur un substrat de cablage.

Country Status (2)

Country Link
FR (1) FR2675946B1 (fr)
WO (1) WO1992020101A1 (fr)

Family Cites Families (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS61133637A (ja) * 1984-12-03 1986-06-20 Nec Corp 接続電極の形成方法
EP0191434B1 (fr) * 1985-02-15 1991-01-16 International Business Machines Corporation Connexion à brasure entre une puce microélectronique et un substrat et son procédé de fabrication
JPS62111457A (ja) * 1985-11-11 1987-05-22 Nec Corp マルチチツプパツケ−ジ
JPS62122258A (ja) * 1985-11-22 1987-06-03 Nec Corp マルチチツプパツケ−ジ
EP0376924A3 (fr) * 1987-05-21 1990-08-22 RAYCHEM CORPORATION (a Delaware corporation) Liaison par compression à or
US4926241A (en) * 1988-02-19 1990-05-15 Microelectronics And Computer Technology Corporation Flip substrate for chip mount
JPH0378290A (ja) * 1989-08-21 1991-04-03 Hitachi Ltd 多層配線基板

Also Published As

Publication number Publication date
FR2675946A1 (fr) 1992-10-30
WO1992020101A1 (fr) 1992-11-12

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