FR2518315A1 - Procede pour la formation de regions implantees d'ions auto-alignees avec des parties de couche isolantes superposees - Google Patents

Procede pour la formation de regions implantees d'ions auto-alignees avec des parties de couche isolantes superposees Download PDF

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Publication number
FR2518315A1
FR2518315A1 FR8220395A FR8220395A FR2518315A1 FR 2518315 A1 FR2518315 A1 FR 2518315A1 FR 8220395 A FR8220395 A FR 8220395A FR 8220395 A FR8220395 A FR 8220395A FR 2518315 A1 FR2518315 A1 FR 2518315A1
Authority
FR
France
Prior art keywords
layer
photosensitive resin
photoresist
insulating layer
implanted
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR8220395A
Other languages
English (en)
French (fr)
Other versions
FR2518315B1 (enExample
Inventor
Manohar Lai Malwah
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Koninklijke Philips NV
Original Assignee
Philips Gloeilampenfabrieken NV
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Philips Gloeilampenfabrieken NV filed Critical Philips Gloeilampenfabrieken NV
Publication of FR2518315A1 publication Critical patent/FR2518315A1/fr
Application granted granted Critical
Publication of FR2518315B1 publication Critical patent/FR2518315B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76—Making of isolation regions between components
    • H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/76297—Dielectric isolation using EPIC techniques, i.e. epitaxial passivated integrated circuit
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/0271—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising organic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/26—Bombardment with radiation
    • H01L21/263—Bombardment with radiation with high-energy radiation
    • H01L21/265—Bombardment with radiation with high-energy radiation producing ion implantation
    • H01L21/266—Bombardment with radiation with high-energy radiation producing ion implantation using masks
    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10D—INORGANIC ELECTRIC SEMICONDUCTOR DEVICES
    • H10D62/00—Semiconductor bodies, or regions thereof, of devices having potential barriers
    • H10D62/10—Shapes, relative sizes or dispositions of the regions of the semiconductor bodies; Shapes of the semiconductor bodies
    • H10D62/102—Constructional design considerations for preventing surface leakage or controlling electric field concentration
    • H10D62/112—Constructional design considerations for preventing surface leakage or controlling electric field concentration for preventing surface leakage due to surface inversion layers, e.g. by using channel stoppers

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • General Physics & Mathematics (AREA)
  • Manufacturing & Machinery (AREA)
  • Computer Hardware Design (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Power Engineering (AREA)
  • High Energy & Nuclear Physics (AREA)
  • Health & Medical Sciences (AREA)
  • Toxicology (AREA)
  • Element Separation (AREA)
  • Drying Of Semiconductors (AREA)
FR8220395A 1981-12-10 1982-12-06 Procede pour la formation de regions implantees d'ions auto-alignees avec des parties de couche isolantes superposees Granted FR2518315A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US06/329,364 US4398964A (en) 1981-12-10 1981-12-10 Method of forming ion implants self-aligned with a cut

Publications (2)

Publication Number Publication Date
FR2518315A1 true FR2518315A1 (fr) 1983-06-17
FR2518315B1 FR2518315B1 (enExample) 1985-03-01

Family

ID=23285045

Family Applications (1)

Application Number Title Priority Date Filing Date
FR8220395A Granted FR2518315A1 (fr) 1981-12-10 1982-12-06 Procede pour la formation de regions implantees d'ions auto-alignees avec des parties de couche isolantes superposees

Country Status (5)

Country Link
US (1) US4398964A (enExample)
JP (1) JPS58107630A (enExample)
DE (1) DE3244588A1 (enExample)
FR (1) FR2518315A1 (enExample)
GB (1) GB2111305B (enExample)

Families Citing this family (16)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2117175A (en) * 1982-03-17 1983-10-05 Philips Electronic Associated Semiconductor device and method of manufacture
US4586243A (en) * 1983-01-14 1986-05-06 General Motors Corporation Method for more uniformly spacing features in a semiconductor monolithic integrated circuit
US4679303A (en) * 1983-09-30 1987-07-14 Hughes Aircraft Company Method of fabricating high density MOSFETs with field aligned channel stops
US4564584A (en) * 1983-12-30 1986-01-14 Ibm Corporation Photoresist lift-off process for fabricating semiconductor devices
US4567132A (en) * 1984-03-16 1986-01-28 International Business Machines Corporation Multi-level resist image reversal lithography process
JPS61127174A (ja) * 1984-11-26 1986-06-14 Toshiba Corp 半導体装置の製造方法
US4592132A (en) * 1984-12-07 1986-06-03 Hughes Aircraft Company Process for fabricating multi-level-metal integrated circuits at high yields
GB2172427A (en) * 1985-03-13 1986-09-17 Philips Electronic Associated Semiconductor device manufacture using a deflected ion beam
US4737468A (en) * 1987-04-13 1988-04-12 Motorola Inc. Process for developing implanted buried layer and/or key locators
US5262392A (en) * 1991-07-15 1993-11-16 Eastman Kodak Company Method for patterning metallo-organic percursor film and method for producing a patterned ceramic film and film products
US5830789A (en) * 1996-11-19 1998-11-03 Integrated Device Technology, Inc. CMOS process forming wells after gate formation
DE10302104A1 (de) * 2003-01-21 2004-08-05 Friwo Gerätebau Gmbh Verfahren zum Herstellen von Schaltungsträgern mit intergrierten passiven Bauelementen
US7064048B2 (en) * 2003-10-17 2006-06-20 United Microelectronics Corp. Method of forming a semi-insulating region
US7208401B2 (en) * 2004-03-12 2007-04-24 Hewlett-Packard Development Company, L.P. Method for forming a thin film
KR100881017B1 (ko) * 2007-05-17 2009-01-30 주식회사 동부하이텍 반도체 소자의 제조 방법
JP6728638B2 (ja) * 2015-11-10 2020-07-22 富士電機株式会社 半導体デバイスの製造方法

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1432309A (en) * 1973-03-02 1976-04-14 Signetics Corp Semiconductor structures

Family Cites Families (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4004044A (en) * 1975-05-09 1977-01-18 International Business Machines Corporation Method for forming patterned films utilizing a transparent lift-off mask
US4022932A (en) * 1975-06-09 1977-05-10 International Business Machines Corporation Resist reflow method for making submicron patterned resist masks
US4040891A (en) * 1976-06-30 1977-08-09 Ibm Corporation Etching process utilizing the same positive photoresist layer for two etching steps
US4201800A (en) * 1978-04-28 1980-05-06 International Business Machines Corp. Hardened photoresist master image mask process
US4144101A (en) * 1978-06-05 1979-03-13 International Business Machines Corporation Process for providing self-aligned doping regions by ion-implantation and lift-off
US4253888A (en) * 1978-06-16 1981-03-03 Matsushita Electric Industrial Co., Ltd. Pretreatment of photoresist masking layers resulting in higher temperature device processing
FR2460037A1 (fr) * 1979-06-22 1981-01-16 Thomson Csf Procede d'auto-alignement de regions differemment dopees d'une structure de semi-conducteur
US4350541A (en) * 1979-08-13 1982-09-21 Nippon Telegraph & Telephone Public Corp. Doping from a photoresist layer
US4231811A (en) * 1979-09-13 1980-11-04 Intel Corporation Variable thickness self-aligned photoresist process
DE2945854A1 (de) * 1979-11-13 1981-05-21 Deutsche Itt Industries Gmbh, 7800 Freiburg Ionenimplantationsverfahren

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB1432309A (en) * 1973-03-02 1976-04-14 Signetics Corp Semiconductor structures

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
IBM TECHNICAL DISCLOSURE BULLETIN, vol. 16, no. 9, février 1974, New York P.E. CARR et al. "Photolithographic etching method for integrated circuits" *

Also Published As

Publication number Publication date
JPS58107630A (ja) 1983-06-27
FR2518315B1 (enExample) 1985-03-01
GB2111305A (en) 1983-06-29
US4398964A (en) 1983-08-16
DE3244588A1 (de) 1983-07-14
GB2111305B (en) 1985-11-20

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