FR2427685A1 - Perfectionnements aux transistors a effet de champ et a leur fabrication - Google Patents

Perfectionnements aux transistors a effet de champ et a leur fabrication

Info

Publication number
FR2427685A1
FR2427685A1 FR7914017A FR7914017A FR2427685A1 FR 2427685 A1 FR2427685 A1 FR 2427685A1 FR 7914017 A FR7914017 A FR 7914017A FR 7914017 A FR7914017 A FR 7914017A FR 2427685 A1 FR2427685 A1 FR 2427685A1
Authority
FR
France
Prior art keywords
substrate
face
manufacturing
field effect
forming
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
FR7914017A
Other languages
English (en)
Inventor
Brian Thomas Hughes
John Charles Vokes
David Robert Wight
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
UK Government
Original Assignee
UK Government
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by UK Government filed Critical UK Government
Publication of FR2427685A1 publication Critical patent/FR2427685A1/fr
Withdrawn legal-status Critical Current

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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
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    • H01L29/66—Types of semiconductor device ; Multistep manufacturing processes therefor
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    • H01L29/76—Unipolar devices, e.g. field effect transistors
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    • H01L29/78—Field effect transistors with field effect produced by an insulated gate
    • H01L29/786—Thin film transistors, i.e. transistors with a channel being at least partly a thin film
    • H01L29/78645—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate
    • H01L29/78648—Thin film transistors, i.e. transistors with a channel being at least partly a thin film with multiple gate arranged on opposing sides of the channel
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    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
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    • H01L2924/30105—Capacitance

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  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Ceramic Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Chemical & Material Sciences (AREA)
  • General Chemical & Material Sciences (AREA)
  • Chemical Kinetics & Catalysis (AREA)
  • Junction Field-Effect Transistors (AREA)
  • Bipolar Transistors (AREA)

Abstract

L'invention concerne un procédé de fabrication d'un transistor à effet de champ consistant, successivement, à former une couche 4 de matière semi-conductrice (par exemple GaAs) à la surface d'un premier substrat 1 en matière semi-conductrice (par exemple également GaAs), à former une électrode de goulot 7 sur une face de la couche active, à appliquer un second substrat 11 de matière isolante sur une face de cette structure, à éliminer le premier substrat, et à former les électrodes de cathode et d'anode sur la face de la couche active opposée à l'électrode de goulot. Facultativement, l'élimination du premier substrat par attaque corrosive sélective est facilitée par l'addition d'une couche intermédiaire 2 en GaAlAs entre le premier et le second substrats. Une seconde électrode de goulot pourra être formée sur la face de la couche active opposée à celle portant la première électrode de goulot. Le procédé convient particulièrement à la fabrication des T.E.C. pour hautes fréquences.
FR7914017A 1978-05-31 1979-05-31 Perfectionnements aux transistors a effet de champ et a leur fabrication Withdrawn FR2427685A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
GB25552/78A GB1601059A (en) 1978-05-31 1978-05-31 Fet devices and their fabrication

Publications (1)

Publication Number Publication Date
FR2427685A1 true FR2427685A1 (fr) 1979-12-28

Family

ID=10229538

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7914017A Withdrawn FR2427685A1 (fr) 1978-05-31 1979-05-31 Perfectionnements aux transistors a effet de champ et a leur fabrication

Country Status (6)

Country Link
US (1) US4317125A (fr)
EP (1) EP0006001A1 (fr)
JP (1) JPS54158881A (fr)
AU (1) AU4758379A (fr)
FR (1) FR2427685A1 (fr)
GB (1) GB1601059A (fr)

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FR2524713A1 (fr) * 1982-04-02 1983-10-07 Thomson Csf Transistor a effet de champ du type planar a grille supplementaire enterree et procede de realisation d'un tel transistor
US4474623A (en) * 1982-04-26 1984-10-02 Raytheon Company Method of passivating a semiconductor body
JPS58196056A (ja) * 1982-05-11 1983-11-15 Matsushita Electric Ind Co Ltd 半導体装置の製造方法
IT1175541B (it) * 1984-06-22 1987-07-01 Telettra Lab Telefon Procedimento per la connessione a terra di dispositivi planari e circuiti integrati e prodotti cosi' ottenuti
US4784967A (en) * 1986-12-19 1988-11-15 American Telephone And Telegraph Company, At&T Bell Laboratories Method for fabricating a field-effect transistor with a self-aligned gate
US4927782A (en) * 1989-06-27 1990-05-22 The United States Of America As Represented By The Secretary Of The Navy Method of making self-aligned GaAs/AlGaAs FET's
JPH0344067A (ja) * 1989-07-11 1991-02-25 Nec Corp 半導体基板の積層方法
GB9208324D0 (en) * 1992-04-15 1992-06-03 British Tech Group Semiconductor devices
US5236871A (en) * 1992-04-29 1993-08-17 The United States Of America As Represented By The Administrator Of The National Aeronautics And Space Administration Method for producing a hybridization of detector array and integrated circuit for readout
US5302842A (en) * 1992-07-20 1994-04-12 Bell Communications Research, Inc. Field-effect transistor formed over gate electrode
US5244817A (en) * 1992-08-03 1993-09-14 Eastman Kodak Company Method of making backside illuminated image sensors
KR100228385B1 (ko) * 1996-12-21 1999-11-01 정선종 반도체 소자의 게이트 전극 제조 방법
US6127272A (en) * 1998-01-26 2000-10-03 Motorola, Inc. Method of electron beam lithography on very high resistivity substrates
FR2838866B1 (fr) * 2002-04-23 2005-06-24 St Microelectronics Sa Procede de fabrication de composants electroniques et produit electronique incorporant un composant ainsi obtenu
US6611029B1 (en) * 2002-11-08 2003-08-26 Advanced Micro Devices, Inc. Double gate semiconductor device having separate gates
US7148526B1 (en) 2003-01-23 2006-12-12 Advanced Micro Devices, Inc. Germanium MOSFET devices and methods for making same
US6800885B1 (en) * 2003-03-12 2004-10-05 Advance Micro Devices, Inc. Asymmetrical double gate or all-around gate MOSFET devices and methods for making same
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GB1601059A (en) 1981-10-21
AU4758379A (en) 1979-12-06
EP0006001A1 (fr) 1979-12-12
US4317125A (en) 1982-02-23
JPS54158881A (en) 1979-12-15

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