FR2399712A1 - Dispositif pour tester des memoires a semi-conducteur - Google Patents

Dispositif pour tester des memoires a semi-conducteur

Info

Publication number
FR2399712A1
FR2399712A1 FR7822813A FR7822813A FR2399712A1 FR 2399712 A1 FR2399712 A1 FR 2399712A1 FR 7822813 A FR7822813 A FR 7822813A FR 7822813 A FR7822813 A FR 7822813A FR 2399712 A1 FR2399712 A1 FR 2399712A1
Authority
FR
France
Prior art keywords
latch circuit
threshold
latched
reference voltage
memory cell
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
FR7822813A
Other languages
English (en)
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sperry Corp
Original Assignee
Sperry Rand Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Priority claimed from US05/821,271 external-priority patent/US4130897A/en
Priority claimed from US05/821,272 external-priority patent/US4127901A/en
Application filed by Sperry Rand Corp filed Critical Sperry Rand Corp
Publication of FR2399712A1 publication Critical patent/FR2399712A1/fr
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/26—Sensing or reading circuits; Data output circuits
    • G11C16/28—Sensing or reading circuits; Data output circuits using differential sensing or reference cells, e.g. dummy cells
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50004—Marginal testing, e.g. race, voltage or current testing of threshold voltage
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C29/50—Marginal testing, e.g. race, voltage or current testing
    • G11C29/50016—Marginal testing, e.g. race, voltage or current testing of retention
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2201/00—Indexing scheme relating to error detection, to error correction, and to monitoring
    • G06F2201/81—Threshold
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • For Increasing The Reliability Of Semiconductor Memories (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)

Abstract

Ce dispositif pour tester des mémoires est de type de ceux dont les cellules de mémoire sont constituées par des dispositifs semi-conducteurs à seuil variable. Une tension de seuil d'une cellule de mémoire est appliquée à l'un des côtés d'un circuit bistable à verrouillage et une tension de référence est appliquée à son autre côté; la tension de référence est élevée pas à pas jusqu'à ce que le circuit bistable à verrouillage soit verrouille dans le sens opposé, ce qui donne une mesure de la tension de seuil. Le dispositif peut également fonctionner avec deux tensions de seuil provenant dune seule cellule de mémoire et appliquées, aux deux côtés du circuit à verrouillage, de sorte que ce dernier lise le contenu de la cellule. Les sorties du circuit à verrouillage peuvent être couplées en croix aux circuits d'entrée par des circuits à transistors, ce qui augmente l'écart des tensions du circuit à verrouillage et réduit sa consommation d'énergie. Le dispositif peut être réalisé sur une seule microplaquette intégrée et, notamment sur la même microplaquette qu'un ensemble de mémoire.
FR7822813A 1977-08-03 1978-08-02 Dispositif pour tester des memoires a semi-conducteur Pending FR2399712A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US05/821,271 US4130897A (en) 1977-08-03 1977-08-03 MNOS FET memory retention characterization test circuit with enhanced sensitivity and power conservation
US05/821,272 US4127901A (en) 1977-08-03 1977-08-03 MNOS FET memory retention characterization test circuit

Publications (1)

Publication Number Publication Date
FR2399712A1 true FR2399712A1 (fr) 1979-03-02

Family

ID=27124528

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7822813A Pending FR2399712A1 (fr) 1977-08-03 1978-08-02 Dispositif pour tester des memoires a semi-conducteur

Country Status (4)

Country Link
JP (1) JPS5427733A (fr)
DE (1) DE2833828A1 (fr)
FR (1) FR2399712A1 (fr)
GB (1) GB2002129B (fr)

Families Citing this family (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55117034A (en) * 1979-02-28 1980-09-09 Yamaha Motor Co Ltd Apparatus for inhibiting rotation of rotatable part of engine
US4253059A (en) * 1979-05-14 1981-02-24 Fairchild Camera & Instrument Corp. EPROM Reliability test circuit
KR940006676B1 (ko) * 1991-10-14 1994-07-25 삼성전자 주식회사 시험회로를 내장한 기억용 반도체 집적회로

Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3795859A (en) * 1972-07-03 1974-03-05 Ibm Method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors
US3909806A (en) * 1973-07-13 1975-09-30 Tokyo Shibaura Electric Co Analogue memory device

Family Cites Families (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3824564A (en) * 1973-07-19 1974-07-16 Sperry Rand Corp Integrated threshold mnos memory with decoder and operating sequence

Patent Citations (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3795859A (en) * 1972-07-03 1974-03-05 Ibm Method and apparatus for determining the electrical characteristics of a memory cell having field effect transistors
US3909806A (en) * 1973-07-13 1975-09-30 Tokyo Shibaura Electric Co Analogue memory device

Also Published As

Publication number Publication date
DE2833828A1 (de) 1979-02-08
GB2002129A (en) 1979-02-14
JPS5427733A (en) 1979-03-02
GB2002129B (en) 1982-01-20

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