FR2389234A1 - Procede de fabrication de dispositifs semi-conducteurs en logique a injection integree (iil) et dispositifs en resultant - Google Patents

Procede de fabrication de dispositifs semi-conducteurs en logique a injection integree (iil) et dispositifs en resultant

Info

Publication number
FR2389234A1
FR2389234A1 FR7809186A FR7809186A FR2389234A1 FR 2389234 A1 FR2389234 A1 FR 2389234A1 FR 7809186 A FR7809186 A FR 7809186A FR 7809186 A FR7809186 A FR 7809186A FR 2389234 A1 FR2389234 A1 FR 2389234A1
Authority
FR
France
Prior art keywords
iil
devices
cell
npn
base
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7809186A
Other languages
English (en)
Other versions
FR2389234B1 (fr
Inventor
Francisco H De La Moneda
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2389234A1 publication Critical patent/FR2389234A1/fr
Application granted granted Critical
Publication of FR2389234B1 publication Critical patent/FR2389234B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/77—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate
    • H01L21/78—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices
    • H01L21/82—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components
    • H01L21/822—Manufacture or treatment of devices consisting of a plurality of solid state components or integrated circuits formed in, or on, a common substrate with subsequent division of the substrate into plural individual devices to produce devices, e.g. integrated circuits, each consisting of a plurality of components the substrate being a semiconductor, using silicon technology
    • H01L21/8222—Bipolar technology
    • H01L21/8226—Bipolar technology comprising merged transistor logic or integrated injection logic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/027—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34
    • H01L21/033—Making masks on semiconductor bodies for further photolithographic processing not provided for in group H01L21/18 or H01L21/34 comprising inorganic layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having potential barriers; including integrated passive circuit elements having potential barriers
    • H01L27/0203—Particular design considerations for integrated circuits
    • H01L27/0214—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L
    • H01L27/0229—Particular design considerations for integrated circuits for internal polarisation, e.g. I2L of bipolar structures
    • H01L27/0233—Integrated injection logic structures [I2L]

Landscapes

  • Engineering & Computer Science (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Inorganic Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Bipolar Integrated Circuits (AREA)
  • Bipolar Transistors (AREA)
  • Logic Circuits (AREA)

Abstract

Procédé de fabrication de dispositifs semi-conducteurs en logique à injection intégrée (IIL) et dispositifs en résultant. Le dispositif représente montre une cellule de base en technologie IIL composée d'un transistor NPN vertical et d'un transistor PNP latéral. Un substrat de type N**+ est recouvert par une couche épitaxiale de type P 18. La cellule est isolée par un anneau dielectrique en SiO**2 14. La base non active du NPN 25 est relativement plus dopée grâce à l'exodiffusion d'une région enterrée formée par implantation ionique, que la base active 31. La base du PNP 24 obtenue par étalement, est relativement à concentration constante. VIN représente le contact de base de la cellule, VO1 et VO2 sont les sorties de collecteur. De façon classique l'émetteur 52 et NPN est à la masse. Eb est la polarisation de l'émetteur de l'injection. Application à l'industrie des semi-conducteurs et plus particulierement aux cellules IIL à vitesse et efficacité élevées et à grande densité d'intégration.
FR7809186A 1977-04-29 1978-03-23 Procede de fabrication de dispositifs semi-conducteurs en logique a injection integree (iil) et dispositifs en resultant Granted FR2389234A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/792,277 US4149906A (en) 1977-04-29 1977-04-29 Process for fabrication of merged transistor logic (MTL) cells

Publications (2)

Publication Number Publication Date
FR2389234A1 true FR2389234A1 (fr) 1978-11-24
FR2389234B1 FR2389234B1 (fr) 1982-06-04

Family

ID=25156339

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7809186A Granted FR2389234A1 (fr) 1977-04-29 1978-03-23 Procede de fabrication de dispositifs semi-conducteurs en logique a injection integree (iil) et dispositifs en resultant

Country Status (5)

Country Link
US (1) US4149906A (fr)
JP (1) JPS53135584A (fr)
DE (1) DE2813154A1 (fr)
FR (1) FR2389234A1 (fr)
GB (1) GB1599954A (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4258379A (en) * 1978-09-25 1981-03-24 Hitachi, Ltd. IIL With in and outdiffused emitter pocket
JPS5839070A (ja) * 1981-08-31 1983-03-07 Toshiba Corp 半導体装置
JPS5855875U (ja) * 1981-10-12 1983-04-15 三菱マテリアル株式会社 回転装置
JPS58182101A (ja) * 1982-04-19 1983-10-25 Hitachi Ltd テ−プレコ−ダ装置
JPS5988224A (ja) * 1982-11-12 1984-05-22 Seiko Instr & Electronics Ltd 組立装置
US4546539A (en) * 1982-12-08 1985-10-15 Harris Corporation I2 L Structure and fabrication process compatible with high voltage bipolar transistors
US4843448A (en) * 1988-04-18 1989-06-27 The United States Of America As Represented By The Secretary Of The Navy Thin-film integrated injection logic
JPH0447961U (fr) * 1990-08-29 1992-04-23
JP2002324846A (ja) * 2001-04-25 2002-11-08 Sanken Electric Co Ltd 半導体装置及びその製造方法
WO2012085677A1 (fr) * 2010-12-20 2012-06-28 Diodes Zetex Semiconductors Limited Émetteur asservi complémentaire darlington à vitesse de commutation améliorée et à réglage de croisement amélioré, et à tension de sortie accrue
US9117759B2 (en) * 2011-08-10 2015-08-25 Micron Technology, Inc. Methods of forming bulb-shaped trenches in silicon

Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2160667A1 (fr) * 1971-11-20 1973-06-29 Itt
GB1362345A (en) * 1973-05-11 1974-08-07 Mullard Ltd Semiconductor device manufacture
DE2538326A1 (de) * 1974-09-03 1976-03-11 Western Electric Co Halbleiteraufbau
US3993513A (en) * 1974-10-29 1976-11-23 Fairchild Camera And Instrument Corporation Combined method for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors and the resulting structures
FR2316730A1 (fr) * 1975-06-19 1977-01-28 Texas Instruments Inc Circuit logique integre et son procede de fabrication

Family Cites Families (4)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL170901C (nl) * 1971-04-03 1983-01-03 Philips Nv Werkwijze voor het vervaardigen van een halfgeleiderinrichting.
DE2344320C2 (de) * 1973-09-03 1975-06-26 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Kompensation von Grenzflächenladungen bei epitaktisch auf ein Substrat aufgewachsenen Siliziumdünnschichten
DE2453134C3 (de) * 1974-11-08 1983-02-10 Deutsche Itt Industries Gmbh, 7800 Freiburg Planardiffusionsverfahren
DE2507613C3 (de) * 1975-02-21 1979-07-05 Siemens Ag, 1000 Berlin Und 8000 Muenchen Verfahren zur Herstellung eines invers betriebenen Transistors

Patent Citations (5)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
FR2160667A1 (fr) * 1971-11-20 1973-06-29 Itt
GB1362345A (en) * 1973-05-11 1974-08-07 Mullard Ltd Semiconductor device manufacture
DE2538326A1 (de) * 1974-09-03 1976-03-11 Western Electric Co Halbleiteraufbau
US3993513A (en) * 1974-10-29 1976-11-23 Fairchild Camera And Instrument Corporation Combined method for fabricating oxide-isolated vertical bipolar transistors and complementary oxide-isolated lateral bipolar transistors and the resulting structures
FR2316730A1 (fr) * 1975-06-19 1977-01-28 Texas Instruments Inc Circuit logique integre et son procede de fabrication

Non-Patent Citations (2)

* Cited by examiner, † Cited by third party
Title
EXBK/75 *
EXBK/76 *

Also Published As

Publication number Publication date
JPS5526623B2 (fr) 1980-07-15
DE2813154A1 (de) 1978-11-02
GB1599954A (en) 1981-10-07
JPS53135584A (en) 1978-11-27
US4149906A (en) 1979-04-17
FR2389234B1 (fr) 1982-06-04

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Legal Events

Date Code Title Description
ST Notification of lapse