FR2375719A1 - Procede d'interconnexion de couches metalliques dans des circuits integres et structures resultantes - Google Patents

Procede d'interconnexion de couches metalliques dans des circuits integres et structures resultantes

Info

Publication number
FR2375719A1
FR2375719A1 FR7734661A FR7734661A FR2375719A1 FR 2375719 A1 FR2375719 A1 FR 2375719A1 FR 7734661 A FR7734661 A FR 7734661A FR 7734661 A FR7734661 A FR 7734661A FR 2375719 A1 FR2375719 A1 FR 2375719A1
Authority
FR
France
Prior art keywords
metal layers
integrated circuits
resulting structures
interconnecting metal
level
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
FR7734661A
Other languages
English (en)
Other versions
FR2375719B1 (fr
Inventor
Homi G Sarkary
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
International Business Machines Corp
Original Assignee
International Business Machines Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by International Business Machines Corp filed Critical International Business Machines Corp
Publication of FR2375719A1 publication Critical patent/FR2375719A1/fr
Application granted granted Critical
Publication of FR2375719B1 publication Critical patent/FR2375719B1/fr
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/768—Applying interconnections to be used for carrying current between separate components within a device comprising conductors and dielectrics
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/52—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames
    • H01L23/522—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames including external interconnections consisting of a multilayer structure of conductive and insulating layers inseparably formed on the semiconductor body
    • H01L23/5226—Via connections in a multilevel interconnection structure
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/0001—Technical content checked by a classifier
    • H01L2924/0002—Not covered by any one of groups H01L24/00, H01L24/00 and H01L2224/00
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/30—Technical effects
    • H01L2924/301—Electrical effects
    • H01L2924/3011—Impedance

Landscapes

  • Engineering & Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)

Abstract

Procédé d'interconnexion de couches métalliques dans des circuits intégrés et structures résultantes. Ce procédé comprend la formation de doigts parallèles 22A et 22B aux extrémités des bandes conductrices 22 qui constituent la configuration conductrice de premier niveau formée au-dessus d'un substrat semiconducteur 10 recouvert par un revêtement isolant 11. On dépose une nouvelle couche isolante 23 et par des procédés photolithographiques on forme une ouverture entre lesdits doigts qui expose une portion 222 de ceux-ci. Il ne reste plus qu'à deposer la configuration conductrice de second niveau qui assure la liaison électrique avec celle du premier niveau. Application à la fabrication de dispositifs intégrés à semi-conducteurs.
FR7734661A 1976-12-22 1977-11-10 Procede d'interconnexion de couches metalliques dans des circuits integres et structures resultantes Granted FR2375719A1 (fr)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US05/753,240 US4109275A (en) 1976-12-22 1976-12-22 Interconnection of integrated circuit metallization

Publications (2)

Publication Number Publication Date
FR2375719A1 true FR2375719A1 (fr) 1978-07-21
FR2375719B1 FR2375719B1 (fr) 1980-08-22

Family

ID=25029785

Family Applications (1)

Application Number Title Priority Date Filing Date
FR7734661A Granted FR2375719A1 (fr) 1976-12-22 1977-11-10 Procede d'interconnexion de couches metalliques dans des circuits integres et structures resultantes

Country Status (5)

Country Link
US (1) US4109275A (fr)
JP (1) JPS5378792A (fr)
DE (1) DE2753489A1 (fr)
FR (1) FR2375719A1 (fr)
GB (1) GB1591264A (fr)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3206413A1 (de) * 1982-02-23 1983-09-01 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von aus silizium oder aus siliziden hochschmelzender metalle bestehenden schichten unter verwendung einer planar-magnetron-zerstaeubungsanlage

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
NL7700420A (nl) * 1977-01-17 1978-07-19 Philips Nv Halfgeleiderinrichting en werkwijze ter ver- vaardiging daarvan.
JPS561579A (en) * 1979-06-18 1981-01-09 Shunpei Yamazaki Semiconductor device
JPS5772349A (en) * 1980-10-23 1982-05-06 Nec Corp Semiconductor integrated circuit device
US4622576A (en) * 1984-10-22 1986-11-11 National Semiconductor Corporation Conductive non-metallic self-passivating non-corrodable IC bonding pads
US4761386A (en) * 1984-10-22 1988-08-02 National Semiconductor Corporation Method of fabricating conductive non-metallic self-passivating non-corrodable IC bonding pads
US6965165B2 (en) 1998-12-21 2005-11-15 Mou-Shiung Lin Top layers of metal for high performance IC's
KR100562308B1 (ko) * 2004-12-15 2006-03-22 동부아남반도체 주식회사 반도체소자의 콘택홀 형성방법
EP3696851B1 (fr) * 2019-02-18 2022-10-12 Infineon Technologies AG Agencement de semiconducteur et son procédé de fabrication

Family Cites Families (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3303071A (en) * 1964-10-27 1967-02-07 Bell Telephone Labor Inc Fabrication of a semiconductive device with closely spaced electrodes
US3390308A (en) * 1966-03-31 1968-06-25 Itt Multiple chip integrated circuit assembly
US3483096A (en) * 1968-04-25 1969-12-09 Avco Corp Process for making an indium antimonide infrared detector contact
US3577036A (en) * 1969-05-05 1971-05-04 Ibm Method and means for interconnecting conductors on different metalization pattern levels on monolithically fabricated integrated circuit chips
US3823349A (en) * 1970-01-22 1974-07-09 Ibm Interconnection metallurgy system for semiconductor devices
JPS5145438B1 (fr) * 1971-06-25 1976-12-03
US3751292A (en) * 1971-08-20 1973-08-07 Motorola Inc Multilayer metallization system
US4000502A (en) * 1973-11-05 1976-12-28 General Dynamics Corporation Solid state radiation detector and process
US4023197A (en) * 1974-04-15 1977-05-10 Ibm Corporation Integrated circuit chip carrier and method for forming the same

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE3206413A1 (de) * 1982-02-23 1983-09-01 Siemens AG, 1000 Berlin und 8000 München Verfahren zum herstellen von aus silizium oder aus siliziden hochschmelzender metalle bestehenden schichten unter verwendung einer planar-magnetron-zerstaeubungsanlage

Also Published As

Publication number Publication date
GB1591264A (en) 1981-06-17
FR2375719B1 (fr) 1980-08-22
JPS5378792A (en) 1978-07-12
DE2753489A1 (de) 1978-06-29
US4109275A (en) 1978-08-22

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Legal Events

Date Code Title Description
ST Notification of lapse