FI70660C - Saett och anordning foer att i ett telekommunikationssystem relera faslaeget hos en styrd signal i foerhaollande till e n eferenssignal - Google Patents
Saett och anordning foer att i ett telekommunikationssystem relera faslaeget hos en styrd signal i foerhaollande till e n eferenssignal Download PDFInfo
- Publication number
- FI70660C FI70660C FI792703A FI792703A FI70660C FI 70660 C FI70660 C FI 70660C FI 792703 A FI792703 A FI 792703A FI 792703 A FI792703 A FI 792703A FI 70660 C FI70660 C FI 70660C
- Authority
- FI
- Finland
- Prior art keywords
- signal
- reference signal
- delayed
- controlled
- comparison
- Prior art date
Links
- 230000003111 delayed effect Effects 0.000 claims description 12
- 238000000034 method Methods 0.000 claims description 5
- 238000011156 evaluation Methods 0.000 claims description 4
- 230000001276 controlling effect Effects 0.000 claims 1
- 230000001105 regulatory effect Effects 0.000 claims 1
- 239000000872 buffer Substances 0.000 description 4
- 238000001514 detection method Methods 0.000 description 2
- 238000010586 diagram Methods 0.000 description 2
- 238000005259 measurement Methods 0.000 description 2
- 238000006243 chemical reaction Methods 0.000 description 1
- 230000007423 decrease Effects 0.000 description 1
Classifications
-
- H—ELECTRICITY
- H03—ELECTRONIC CIRCUITRY
- H03L—AUTOMATIC CONTROL, STARTING, SYNCHRONISATION OR STABILISATION OF GENERATORS OF ELECTRONIC OSCILLATIONS OR PULSES
- H03L7/00—Automatic control of frequency or phase; Synchronisation
- H03L7/06—Automatic control of frequency or phase; Synchronisation using a reference signal applied to a frequency- or phase-locked loop
- H03L7/08—Details of the phase-locked loop
- H03L7/085—Details of the phase-locked loop concerning mainly the frequency- or phase-detection arrangement including the filtering or amplification of its output signal
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/02—Speed or phase control by the received code signals, the signals containing no special synchronisation information
- H04L7/033—Speed or phase control by the received code signals, the signals containing no special synchronisation information using the transitions of the received signal to control the phase of the synchronising-signal-generating means, e.g. using a phase-locked loop
Landscapes
- Engineering & Computer Science (AREA)
- Computer Networks & Wireless Communication (AREA)
- Signal Processing (AREA)
- Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Manipulation Of Pulses (AREA)
- Synchronizing For Television (AREA)
- Control Of Velocity Or Acceleration (AREA)
Claims (7)
1. Tapa ohjatun signaalin vaiheaseman määräämiseksi vertai-lusignaaliin nähden tietoliikennejärjestelmässä, tunnettu siitä, että vertailusignaalia (C2) viivästetään, viivästettyä ver-tailusignaalia (D1) verrataan ohjattuun signaaliin (C1) ensimmäisen vertailusignaalin (Q1) muodostamiseksi, jonka taso on korkea vast, alhainen riippuen viivästetyn vertailusginaalin (D1) ja ohjatun signaalin (C1) välisestä vaihe-erosta, ja ohjattua signaalia (Cl) viivytetään, viivytettyä, ohjattua signaalia (D2) verrataan ver-tailusignaaliin (C2) toisen vertailusignaalin (Q2) muodostamiseksi, jonka taso on korkea ja vast, alhainen riippuen viivytetyn, ohjatun signaalin (D2) ja vertailusignaalin (C2) välisestä vaihe-erosta, jolloin riippuen signaalien (Q1 ja Q2) loogisista tasoista tehdään looginen päätös, jota päätöstä käytetään ohjaussignaalina ohjatun signaalin (Cl) vaiheaseman korjaamiseksi suhteessa vertailusignaalin (C2) vaiheasemaan.
2. Patenttivaatimuksen 1 mukainen laite, ohjatun signaalin vaiheaseman säätämiseksi suhteessa vertailusignaaliin tietoliikennejärjestelmässä, tunnettu siitä, että se sisältää: ensimmäisen vertailupiirin (FF1), joka on sitä tyyppiä, joka riippuen kahden sen tulokohtiin syötetyn signaalin välisestä vaihe-erosta kehittää lähtösignaalin, jonka taso on korkea ja vast, alhainen, ja jonka toiseen tulokohtaan syötetään vertailusignaali (C2) viivytyspiirin (DL1) kautta ja toiseen' tulokohtaan syötetään ohjattu signaali (Cl) suoraan; ja toisen vertailupiirin (FF2) joka on samaa tyyppiä kuin ensiksimainittu ja jonka toiseen tulo-kohtaan syötetään ohjattu signaali (C1) viivytyspiirin (DL2) kautta ja jonka toiseen tulokohtaan syötetään vertailusignaali (C2) suoraan, jolloin vertailupiirien (FF1, FF2) lähtökohdat on liitetty loogiseen lähtöarviointipiiriin (LC) vastaavan lähtösignaalin (Q1, Q2) syöttämiseksi tämän kahteen tulokohtaan, joka lähtöar-viointipiiri riippuen sen tulokohdissaan saamasta signaaliyhdistel-mästä kehittää binäärisen ohjaussignaalin.
3. Patenttivaatimuksen 2 mukainen laite, tunnettu siitä, että kun ei-viivytetty ohjattu signaali (C1) saapuu laitteeseen myöhempänä ajankohtana kuin viivytetty vertailusignaali
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
SE7809934A SE413826B (sv) | 1978-09-21 | 1978-09-21 | Sett att i ett telekommunikationssystem reglera fasleget hos en styrd signal i forhallande till en referenssignal samt anordning for genomforande av settet |
SE7809934 | 1978-09-21 |
Publications (3)
Publication Number | Publication Date |
---|---|
FI792703A FI792703A (fi) | 1980-03-22 |
FI70660B FI70660B (fi) | 1986-06-06 |
FI70660C true FI70660C (fi) | 1986-09-24 |
Family
ID=20335888
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI792703A FI70660C (fi) | 1978-09-21 | 1979-08-30 | Saett och anordning foer att i ett telekommunikationssystem relera faslaeget hos en styrd signal i foerhaollande till e n eferenssignal |
Country Status (22)
Country | Link |
---|---|
US (1) | US4380083A (fi) |
EP (1) | EP0010077B1 (fi) |
JP (1) | JPS55500724A (fi) |
AR (1) | AR229083A1 (fi) |
AU (1) | AU525914B2 (fi) |
CA (1) | CA1142238A (fi) |
CS (1) | CS216684B2 (fi) |
DD (1) | DD146230A5 (fi) |
DE (1) | DE2963616D1 (fi) |
DK (1) | DK149292C (fi) |
EG (1) | EG14080A (fi) |
ES (1) | ES484315A1 (fi) |
FI (1) | FI70660C (fi) |
HU (1) | HU178531B (fi) |
IE (1) | IE48553B1 (fi) |
IN (1) | IN153004B (fi) |
MX (1) | MX149453A (fi) |
NO (1) | NO150260C (fi) |
PL (1) | PL128123B1 (fi) |
SE (1) | SE413826B (fi) |
WO (1) | WO1980000901A1 (fi) |
YU (1) | YU228379A (fi) |
Families Citing this family (65)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US4400667A (en) * | 1981-01-12 | 1983-08-23 | Sangamo Weston, Inc. | Phase tolerant bit synchronizer for digital signals |
CA1180416A (en) * | 1981-05-19 | 1985-01-02 | Botaro Hirosaki | Timing recovery circuit |
US4518998A (en) * | 1982-06-03 | 1985-05-21 | Klimsch/Optronics, Inc. | Method and apparatus for producing a time advanced output pulse train from an input pulse train |
US4473760A (en) * | 1982-12-13 | 1984-09-25 | Western Digital Corporation | Fast digital sample resolution circuit |
US4648060A (en) * | 1984-07-30 | 1987-03-03 | Hewlett-Packard Company | Dual channel frequency synthesizer system |
DE3441501A1 (de) * | 1984-11-14 | 1986-05-15 | Standard Elektrik Lorenz Ag, 7000 Stuttgart | Schaltungsanordnung zum regenerieren und synchronisieren eines digitalen signals |
FR2608863B1 (fr) * | 1986-12-19 | 1994-04-29 | Nec Corp | Circuit integre logique comportant des bascules electroniques d'entree et de sortie pour stabiliser les durees des impulsions |
JPS63228206A (ja) * | 1987-03-17 | 1988-09-22 | Nec Corp | クロツク分配方式 |
US5101117A (en) * | 1988-02-17 | 1992-03-31 | Mips Computer Systems | Variable delay line phase-locked loop circuit synchronization system |
IL89120A (en) * | 1988-02-17 | 1992-08-18 | Mips Computer Systems Inc | Circuit synchronization system |
EP0364451A1 (en) * | 1988-03-26 | 1990-04-25 | BELL TELEPHONE MANUFACTURING COMPANY Naamloze Vennootschap | Synchronizing circuit |
DE3917217A1 (de) * | 1989-05-26 | 1990-11-29 | Ant Nachrichtentech | Regenerator fuer digitalsignale |
US4959846A (en) * | 1989-09-11 | 1990-09-25 | Raynet Corporation | Clock recovery apparatus including a clock frequency adjuster |
US4975929A (en) * | 1989-09-11 | 1990-12-04 | Raynet Corp. | Clock recovery apparatus |
US5036230A (en) * | 1990-03-01 | 1991-07-30 | Intel Corporation | CMOS clock-phase synthesizer |
US5083049A (en) * | 1991-05-10 | 1992-01-21 | Ast Research, Inc. | Asynchronous circuit with edge-triggered inputs |
US5229752A (en) * | 1991-09-20 | 1993-07-20 | The United States Of America As Represented By The United States Department Of Energy | Method and apparatus for detecting timing errors in a system oscillator |
DE4139117C1 (fi) * | 1991-11-28 | 1993-06-09 | Texas Instruments Deutschland Gmbh, 8050 Freising, De | |
TW234796B (fi) * | 1993-02-24 | 1994-11-21 | Advanced Micro Devices Inc | |
WO1995034127A1 (en) * | 1994-06-03 | 1995-12-14 | Sierra Semiconductor Corporation | A three-state phase-detector/charge pump circuit with no dead-band region |
SE503069C2 (sv) * | 1994-07-06 | 1996-03-18 | Ericsson Telefon Ab L M | Förfarande och anordning för att fasvrida en signal |
GB9505350D0 (en) * | 1995-03-16 | 1995-05-03 | British Tech Group | Electronic identification system |
US5712580A (en) * | 1996-02-14 | 1998-01-27 | International Business Machines Corporation | Linear phase detector for half-speed quadrature clocking architecture |
US5818890A (en) * | 1996-09-24 | 1998-10-06 | Motorola, Inc. | Method for synchronizing signals and structures therefor |
KR100244466B1 (ko) * | 1997-04-26 | 2000-02-01 | 김영환 | 클럭 위상 비교기 |
KR100215889B1 (ko) * | 1997-05-06 | 1999-08-16 | 구본준 | 클럭 동기 회로 |
EP1057894B1 (en) * | 1999-06-04 | 2010-04-28 | Sumitomo Chemical Company, Limited | Esterase genes and uses of the same |
DE10020171A1 (de) | 2000-04-25 | 2001-10-31 | Ericsson Telefon Ab L M | Pulsdetektor |
US8149048B1 (en) | 2000-10-26 | 2012-04-03 | Cypress Semiconductor Corporation | Apparatus and method for programmable power management in a programmable analog circuit block |
US8176296B2 (en) | 2000-10-26 | 2012-05-08 | Cypress Semiconductor Corporation | Programmable microcontroller architecture |
US8103496B1 (en) | 2000-10-26 | 2012-01-24 | Cypress Semicondutor Corporation | Breakpoint control in an in-circuit emulation system |
US8160864B1 (en) | 2000-10-26 | 2012-04-17 | Cypress Semiconductor Corporation | In-circuit emulator and pod synchronized boot |
US6724220B1 (en) | 2000-10-26 | 2004-04-20 | Cyress Semiconductor Corporation | Programmable microcontroller architecture (mixed analog/digital) |
US7765095B1 (en) | 2000-10-26 | 2010-07-27 | Cypress Semiconductor Corporation | Conditional branching in an in-circuit emulation system |
PL207443B1 (pl) * | 2001-04-20 | 2010-12-31 | Aloys Wobben | Sposób sterowania pracą siłowni wiatrowej i siłownia wiatrowa |
DE10119624A1 (de) | 2001-04-20 | 2002-11-21 | Aloys Wobben | Verfahren zum Betreiben einer Windenergieanlage |
US7406674B1 (en) | 2001-10-24 | 2008-07-29 | Cypress Semiconductor Corporation | Method and apparatus for generating microcontroller configuration information |
US8078970B1 (en) | 2001-11-09 | 2011-12-13 | Cypress Semiconductor Corporation | Graphical user interface with user-selectable list-box |
US8042093B1 (en) | 2001-11-15 | 2011-10-18 | Cypress Semiconductor Corporation | System providing automatic source code generation for personalization and parameterization of user modules |
US7844437B1 (en) * | 2001-11-19 | 2010-11-30 | Cypress Semiconductor Corporation | System and method for performing next placements and pruning of disallowed placements for programming an integrated circuit |
US7770113B1 (en) | 2001-11-19 | 2010-08-03 | Cypress Semiconductor Corporation | System and method for dynamically generating a configuration datasheet |
US7774190B1 (en) | 2001-11-19 | 2010-08-10 | Cypress Semiconductor Corporation | Sleep and stall in an in-circuit emulation system |
US6971004B1 (en) | 2001-11-19 | 2005-11-29 | Cypress Semiconductor Corp. | System and method of dynamically reconfiguring a programmable integrated circuit |
US8069405B1 (en) | 2001-11-19 | 2011-11-29 | Cypress Semiconductor Corporation | User interface for efficiently browsing an electronic document using data-driven tabs |
US8103497B1 (en) | 2002-03-28 | 2012-01-24 | Cypress Semiconductor Corporation | External interface for event architecture |
US7761845B1 (en) | 2002-09-09 | 2010-07-20 | Cypress Semiconductor Corporation | Method for parameterizing a user module |
US7295049B1 (en) * | 2004-03-25 | 2007-11-13 | Cypress Semiconductor Corporation | Method and circuit for rapid alignment of signals |
US8069436B2 (en) | 2004-08-13 | 2011-11-29 | Cypress Semiconductor Corporation | Providing hardware independence to automate code generation of processing device firmware |
US7332976B1 (en) | 2005-02-04 | 2008-02-19 | Cypress Semiconductor Corporation | Poly-phase frequency synthesis oscillator |
US7400183B1 (en) | 2005-05-05 | 2008-07-15 | Cypress Semiconductor Corporation | Voltage controlled oscillator delay cell and method |
US8085067B1 (en) | 2005-12-21 | 2011-12-27 | Cypress Semiconductor Corporation | Differential-to-single ended signal converter circuit and method |
US8067948B2 (en) | 2006-03-27 | 2011-11-29 | Cypress Semiconductor Corporation | Input/output multiplexer bus |
WO2008012915A1 (fr) * | 2006-07-28 | 2008-01-31 | Fujitsu Limited | Appareil de détermination de phase et appareil de synchronisation de phase |
US8026739B2 (en) | 2007-04-17 | 2011-09-27 | Cypress Semiconductor Corporation | System level interconnect with programmable switching |
US8130025B2 (en) | 2007-04-17 | 2012-03-06 | Cypress Semiconductor Corporation | Numerical band gap |
US8092083B2 (en) | 2007-04-17 | 2012-01-10 | Cypress Semiconductor Corporation | Temperature sensor with digital bandgap |
US8040266B2 (en) | 2007-04-17 | 2011-10-18 | Cypress Semiconductor Corporation | Programmable sigma-delta analog-to-digital converter |
US8516025B2 (en) * | 2007-04-17 | 2013-08-20 | Cypress Semiconductor Corporation | Clock driven dynamic datapath chaining |
US9564902B2 (en) | 2007-04-17 | 2017-02-07 | Cypress Semiconductor Corporation | Dynamically configurable and re-configurable data path |
US8266575B1 (en) | 2007-04-25 | 2012-09-11 | Cypress Semiconductor Corporation | Systems and methods for dynamically reconfiguring a programmable system on a chip |
US9720805B1 (en) | 2007-04-25 | 2017-08-01 | Cypress Semiconductor Corporation | System and method for controlling a target device |
US8065653B1 (en) | 2007-04-25 | 2011-11-22 | Cypress Semiconductor Corporation | Configuration of programmable IC design elements |
US8049569B1 (en) | 2007-09-05 | 2011-11-01 | Cypress Semiconductor Corporation | Circuit and method for improving the accuracy of a crystal-less oscillator having dual-frequency modes |
US9448964B2 (en) | 2009-05-04 | 2016-09-20 | Cypress Semiconductor Corporation | Autonomous control in a programmable system |
US8970276B1 (en) * | 2013-12-17 | 2015-03-03 | Analog Devices, Inc. | Clock signal synchronization |
Family Cites Families (13)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NL272023A (fi) * | 1960-12-05 | |||
US3521172A (en) * | 1965-11-26 | 1970-07-21 | Martin Marietta Corp | Binary phase comparator |
US3495184A (en) * | 1968-03-11 | 1970-02-10 | Radiation Inc | Phase-locked loop having improved acquisition range |
US3701039A (en) * | 1968-10-28 | 1972-10-24 | Ibm | Random binary data signal frequency and phase compensation circuit |
US3660647A (en) * | 1969-12-24 | 1972-05-02 | Us Navy | Automatic signal delay tracking system |
US3614635A (en) * | 1969-12-31 | 1971-10-19 | Ibm | Variable frequency control system and data standardizer |
US3714463A (en) * | 1971-01-04 | 1973-01-30 | Motorola Inc | Digital frequency and/or phase detector charge pump |
BE786226A (fr) * | 1971-07-16 | 1973-01-15 | Siemens Ag | Alimentation en courant rythme pour un systeme de circuits de commutation a deux canaux |
US3839599A (en) * | 1972-11-10 | 1974-10-01 | Gte Automatic Electric Lab Inc | Line variation compensation system for synchronized pcm digital switching |
JPS5721064B2 (fi) * | 1974-06-07 | 1982-05-04 | ||
US4001713A (en) * | 1976-01-15 | 1977-01-04 | Gte Sylvania Incorporated | Phase lock loop circuit |
JPS52124848A (en) * | 1976-04-12 | 1977-10-20 | Fujitsu Ltd | Digital phase detection circuit |
DE2735053C3 (de) * | 1977-08-03 | 1980-05-22 | Siemens Ag, 1000 Berlin Und 8000 Muenchen | Digitaler Phasenregelkreis |
-
1978
- 1978-09-21 SE SE7809934A patent/SE413826B/sv not_active IP Right Cessation
-
1979
- 1979-08-29 IN IN610/DEL/79A patent/IN153004B/en unknown
- 1979-08-30 FI FI792703A patent/FI70660C/fi not_active IP Right Cessation
- 1979-09-18 DD DD79215609A patent/DD146230A5/de unknown
- 1979-09-19 CS CS796317A patent/CS216684B2/cs unknown
- 1979-09-19 YU YU02283/79A patent/YU228379A/xx unknown
- 1979-09-19 AR AR278117A patent/AR229083A1/es active
- 1979-09-19 IE IE1778/79A patent/IE48553B1/en unknown
- 1979-09-19 EG EG559/79A patent/EG14080A/xx active
- 1979-09-20 ES ES484315A patent/ES484315A1/es not_active Expired
- 1979-09-20 CA CA000335989A patent/CA1142238A/en not_active Expired
- 1979-09-20 NO NO793023A patent/NO150260C/no unknown
- 1979-09-20 HU HU79EI878A patent/HU178531B/hu unknown
- 1979-09-20 AU AU50993/79A patent/AU525914B2/en not_active Expired
- 1979-09-20 PL PL1979218426A patent/PL128123B1/pl unknown
- 1979-09-20 MX MX179346A patent/MX149453A/es unknown
- 1979-09-21 US US06/196,556 patent/US4380083A/en not_active Expired - Lifetime
- 1979-09-21 EP EP79850087A patent/EP0010077B1/en not_active Expired
- 1979-09-21 JP JP50162179A patent/JPS55500724A/ja active Pending
- 1979-09-21 WO PCT/SE1979/000194 patent/WO1980000901A1/en unknown
- 1979-09-21 DE DE7979850087T patent/DE2963616D1/de not_active Expired
-
1980
- 1980-05-20 DK DK220080A patent/DK149292C/da active
Also Published As
Publication number | Publication date |
---|---|
CS216684B2 (en) | 1982-11-26 |
IN153004B (fi) | 1984-05-19 |
FI792703A (fi) | 1980-03-22 |
WO1980000901A1 (en) | 1980-05-01 |
DD146230A5 (de) | 1981-01-28 |
YU228379A (en) | 1982-10-31 |
DK149292C (da) | 1987-01-19 |
IE48553B1 (en) | 1985-03-06 |
NO793023L (no) | 1980-03-24 |
PL218426A1 (fi) | 1980-08-11 |
HU178531B (en) | 1982-05-28 |
DK149292B (da) | 1986-04-21 |
NO150260B (no) | 1984-06-04 |
DK220080A (da) | 1980-05-20 |
AU5099379A (en) | 1980-03-27 |
PL128123B1 (en) | 1983-12-31 |
AU525914B2 (en) | 1982-12-09 |
EP0010077A1 (en) | 1980-04-16 |
EG14080A (en) | 1983-03-31 |
EP0010077B1 (en) | 1982-09-01 |
JPS55500724A (fi) | 1980-10-02 |
AR229083A1 (es) | 1983-06-15 |
ES484315A1 (es) | 1980-05-16 |
FI70660B (fi) | 1986-06-06 |
DE2963616D1 (en) | 1982-10-28 |
IE791778L (en) | 1980-03-21 |
US4380083A (en) | 1983-04-12 |
NO150260C (no) | 1984-09-12 |
MX149453A (es) | 1983-11-08 |
SE413826B (sv) | 1980-06-23 |
CA1142238A (en) | 1983-03-01 |
SE7809934L (sv) | 1980-03-22 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MA | Patent expired |
Owner name: OY L M ERICSSON AB |