EP0364451A1 - Synchronizing circuit - Google Patents

Abstract

The synchronization circuit described comprises a variable delay circuit (DLC) through which an input signal (DIN) passes intended to adjust the phase of a regenerated output signal (DIN1) with respect to a clock signal ( CL1) at the frequency of the input signal, as well as a decision circuit (DC) used to adjust the variable delay (DL1 / 8) so that it covers half of a period of the input signal and, after detecting a predetermined lack of synchronism, modifies the value of the variable delay so that it can be adjusted to cover the other half of the period.

Description

SYNCHRONIZING CIRCUIT The present invention relates to a synchronizing circuit including a variable delay circuit, through which an input signal is passed to adjust the phase of a regenerated output signal with respect to a clock signal at the frequency of the input signal, and a decision circuit to determine whether a phase lead or a phase lag of said output signal leads to synchronism and to adjust the variable delay accordingly. Such a synchronizing circuit is already known from the German patent application No 3441501 as well as from the published European patent application No 0225587. These known synchronizing circuits may for instance be used to synchronize a high bit-rate digital input signal, such as a television signal or a video telephone signal because propagation delay changes result in fluctuations, e.g. phase jitter of the incoming signal bits. Naturally, if this signal is not of the self-clocking type, or accompanied by a clock signal, but is of the Non-Return-to-Zero type, suitable changes in the binary value should be present in order that synchronization can be maintained.

In both the known synchronizing circuits, the variable delay provided by the delay circuit comprises fourteen different delays covering substantially a complete bit period of the binary input signal. The decision circuit bases its decision to adjust the variable delay at least partly on the values (binary levels) of three successive samples of the output signal which is produced by subjecting the binary input signal to 1 out of the 14 possible delays. In the synchronizing circuit according to the above mentioned German patent application, the decision circuit includes a counter with 14 positions corresponding to the 14 delays and adjusts the variable delay in function of the values of the above mentioned three samples. If the first (lead) and second (actual output) out of the three samples are of opposite values, the decision circuit steps the counter in one direction, whereas when the second and third (lag) samples are of opposite value, it steps the counter in the opposite direction. However, when the first and third samples have the same value the counter position is not modified, as it is assumed that even if the second sample has an opposite value this is a spurious condition, and that phase synchronism has been reached. In the synchronizing circuit according to the above mentioned published European patent application the decision circuit is more complex than in the German patent application. Indeed, one adjusts the variable delay not only in function of the values of the above three samples of the output signal, but also in function of the values of two additional samples of this output signal preceding the above second (actual output) sample by a complete and by a half bit period respectively. By the use of these additional samples the synch ronizing circuit is able to ensure a correct synchronization even if considerable changes of the bit period occur.

The above known synchronizing circuits require the use of a delay circuit providing a variable delay covering substantially a whole bit period. This may be relatively expensive, especially when the synchronizing circuit has to operate at an even higher frequency than that considered in the above German patent application, e.g. of the order of 700 MHz instead of 140 MHz. In this case it might be necessary to use a different technology, e.g. gallium arsenide, to realise the variable delay whereas the decision circuit can operate at a much lower frequency. Indeed, as disclosed in the above European patent application, only every eighth bit period is analyzed enabling a relatively low frequency technology to be used for the decision circuit.

An object of the present invention is to provide a synchronizing circuit of the above type, but which allows the use, as compared to the known solution, of a variable delay covering a smaller part of the period of the input signal, i.e. less expensive, or providing a higher resolution.

According to the invention this object is achieved due to the fact that said decision circuit is able to adjust said variable delay so that it covers a first part of a period of said input signal and after having detected a predetermined lack of synchronism when using said variable delay it modifies the value thereof by an additional delay such that the variable delay may then be adjusted to cover a second part of said period. Another characteristic feature of the present synchronizing circuit is that said first and second parts are each equal to half said period.

Thus, although the variable delay only covers part of the period of the input signal the whole period may be scanned due to the use of the additional delay. The introduction of this additional delay after the detection of the predetermined lack of synchronism is based on the insight that such a synchronism could not be reached for the first part of the period because the signal was scanned at both sides of a signal transition and that by subjecting this signal to the additional delay the scanning will no longer be so located. Thus the chances of reaching synchronism are increased.

Still another characteristic feature of the present synchronizing circuit is that said clock signal is a square wave and that said decision circuit reverses the phase of said square wave to secure said additional delay.

Thus the additional delay equal to half the period of the input signal is provided without any need for a supplementary delay circuit and the whale period can be scanned even when the clock frequency is already the highest that can be used for the, e.g. gallium arsenide, technology at stake. In the above known synchronizing circuits the decision circuit increases the minimum value or decreases the maximum value of the variable delay by a predetermined value equal to half the signal period when it detects that for this minimum or maximum value the delay has still to be decreased or increased respectively to reach synchronism. Because the variable delay covers a whole signal period it is thus made equal to a predetermined or preset value in both cases. This function is in fact performed by presetting means. A further object of the present invention is to provide a synchronizing circuit of the above type, but which does not require the use of such presetting means to allow synchronism to be reached rapidly.

According to the invention this object is achieved due to the fact that said decision circuit after having modified said variable delay by said predetermined value at least two times, changes the value of said variable delay by said additional delay and that said decision circuit prior and after this change modifies the value of said variable delay in a bidirectional and cyclic way . By introducing the additional delay only after at least two changes of the variable delay by half the signal period have been performed, it has been found that synchronism may be reached in a relatively rapid way. On the other hand, because the variable delay only covers half a signal period and is used bidirectionally and in a cyclic way no presetting means are required.

The above mentioned and other objects and features of the invention will become more apparent and the invention itsdelf will be bezst understood by referring to the following description of an embodiment taken in conjunction with the accompaying drawings wherein :

Fig. 1 represents a synchronizing circuit according to the invention, Fig. 2 shows pulse waveforms illustrating the operation of the circuit of Fig. 1.

The synchronizing circuit shown includes the following circuits : - a dual 8sl data multiplexer MUX of the type 10G046, D-flipflops FF1/11 of the type 10G021A, exclusive OR-gates EX0R1/3 of the type 10G002, and fan-out buffers F01/3 of the type 10G011, all these devices being manufactured by Giga Bit Logic Inc. Oak Terrace Lane, Newbury Park, California, USA, - variable delay lines DL1/13 of the type VDK 2010 manufactured by Allied Electronics GMBH, Breite Strasse 155, Cologne, Germany each providing a delay variable from 0 to 2 nanoseconds in increments of 50 picoseconds, - programmable logic arrays PAL1/2 of the type PAL 10H20P8 manufactured by the US firm Monolithic Memories, - a clock circuit CL providing a 700 MHz clock signal CL. The clock signal CL could also be an input signal to the circuit; - a frequency divider FD,

- an inverter INV.

To be noted that the non-inverting outputs of the D-flipflops are indicated by Q whilst the inverting outputs are indicated by QB .

The synchronizing circuit shown has a data input DIN (and a clock input CL) as well as a data output DOUT and a clock output CLl and mainly includes a variable delay circuit DLC, a sampling circuit SC and a decision circuit DC, all. interconnected in a loop, the clock signal CL crontrrolling SC and DC.

The variable delay circuit DLC mainly includes the delay units DL1/8 and the multiplexer MUX. It has the data input DIN which is connected to each of the eight inputs of the multiplexer MUX via the series connection of a fan-out buffer F01/2 and a delay unit DLl/8, F01 and F02 being common to the group DL1/4 and DL5/8 respectively. The output DINl of the multiplexer MUX ponstitutes the output of the delay circuit DLC. This multiplexer MUX further has selection inputs Q6/8 connected to like named outputs of the D-flipflops FF6/8 forming part of the decision circuit DC.

The sampling circuit SC mainly includes the fan-out buffer F03, the delay units DL9/11, the D-flipflops FF1/3 and the exclusive OR-gates EX0R1/3. The output DIN1 of the multiplexer MUX is connected to the data inputs D1/3 of these D-flipflops FF1/3 via the fan-out buffer. F03 and the respective delay units DL9/11. These D-flipflops FF1/3 further have data outputs QB1, QB2, QB3 of which QB1, QB2 and QB2, QB3 are connected to the inputs of the gates EXOR1 and EX0R2 respectively, and clock inputs C1/3. The output CL of the clock CL is connected to these clock inputs C1/3 via the - exclusive-OR gate EXOR3 which has clock output CL1 and is moreover controlled by output Q11 of the D-flipflop FF11 forming part of the decision circuit DC. The data output Q2 of D-flipflop FF2 constitutes the data output DOUT of the synchronizing circuit, whilst the outputs D4/5 of the gates EXOR 1/2 are the outputs of the sampling circuit SC. The output CL1 is the clock output of the synchronizing circuit. The output signals of these gates may be represented by the relations (1) and (2) given on page 16 of the specification.

The decision circuit DC mainly includes the D-flipflops FF4/5, a three-bit bidirectional ring counter comprising the D-flipflops FF6/8, a two-bit unidirectional ring counter constituted by the D-flipflops FF9/10, the decision D-flipflop FF11, the logic array PAL1 controlling FF6/8, the logic array PAL2 controlling FF9/10 and FF11, the frequency divider FD, the delay units. DL12/13 and the inverter INV.

The D-flipflops FF4/5 form part of a further sampling circuit and have data inputs D4/5 connected to the like named outputs of the gates EX0R1/2, data outputs Q4 or U and Q5 or D and clock inputs C4/5. The clock output CL1 of the gate EXOR3 is connected to these clock inputs C4/5 through the frequency divider FD, having output CL2, in series with the delay unit DL12 having output CL3. The gate array PAL1 has inputs U , D and Q6/8 respectively connected to the outputs U, D of FF4/5 and Q6/8 of the 3-bit counter FF6/8. It also has outputs D6/8 and E connected to the like named D-inputs of FF6/8 and the E-input of PAL2 respectively. The output CL2 of the frequency divider FD is connected to the clock inputs C6/8 of FF6/8 via the series connection of the inverter INV having output CL4 and the delay unit DL13 having output CL5. As already mentioned above the outputs Q6/8 of FF6/8 control the selection inputs of the multiplexer MUX. The array PAL1 is so programmed that it generates at its outputs D6/8 and E signals which may be represented by the relations (3) to (6) given on page 16, wherein DB an UB are the complements of D and U respectively. From these relations it follows that :

- if U.DB=1 then the contents of the bidirectional 3-bit ring counter FF6/8 which operates modulo 8 are increased by 1. When the counter stores the value 7 it is thus stepped to the position 0. Then E=1, else E=0;

- if UB.D=1 then the contents of the 3-bit counter FF6/8 are decreased by 1. When the counter stores the value 0 it is thus stepped to the position 7. Then E=1, else E=0, - if U=D then the contents of the 3-bit counter FF6/8 are not modified and E=0.

The gate array PAL2 has inputs E and Q9/11 connected to the like named outputs of PAL1 and FF9/11 respectively. It also has outputs D9/11 connected to the like named D-inputs of FF9/11 which have clock inputs

C9/11 to which the output CL5 of the delay unit DL13 is connected. As already mentioned the output Q11 of FF11 controls an input of the gate EXOR3.

The array PAL2 is so programmed that s - if E=1 then the contents of the unidirectional 2-bit counter FF9/10 which operates modulo 4 are increased by 1. When the counter is in the position 3 it is thus stepped to the position 0. Then D11=QB11, else D11=Q11; - if E=0 then the contents of the 2-bit counter FF9/10 are not modified and D11=Q11.

It is assumed that a 700 Mbit/sec binary input signal is applied to the data input DIN and that the square wave clock signal CL has a frequency equal to 700 MHz. With equal positive and negative half-periods T/2, each positive or negative clock pulse thus lasts about 700 picoseconds.

The delay unit DL1 is so adjusted that it provides a minimum delay which is theoretically equal to 0, but which in practice may for instance vary between 0 and 200 picoseconds. The other delay units DL2/8 are so adjusted that the delays provided by neighbouring delay units differ by a same fraction equal to l/7th of half the bit period i.e. by or 100 picoseconds. In other words the delay units DL1, DL2, .... , DL8 provide the increasing delays DL1, DL1+100, ... , DL1+700 picoseconds respectively. These 8 delays thus constitute a variable delay which covers a range substantially equal to half the bit period or 700 picoseconds and are able to be selectively connected to an input of the MUX under the control of the selection signals Q6/8.

In a similar way the delay unit DL9 is so adjusted that it provides a minimum delay and the other delay units DL10/11 are so adjusted that the delays provided by neighbouring delay units differ by a same value equal to 100 picoseconds. In other words the delay units DL9, DL10 and DL11 provide the increasing delays DL9, DL9+100, and DL9+200 picoseconds respectively. It should be noted that whereas the delays provided by the units DL1/8 are chosen in function of the frequency of the binary input signal since they have to cover a range substantially equal to half the bit period of this signal, this is not so for the delays provided by the units DL9/11. Indeed, the latter have to be so chosen that the edges of the three differently delayed binary signals generated at the outputs of DL9/11 have a time separation which remains sufficiently large even when the binary input signal is subjected to considerable phase jitter. For this reason, when the input signal for instance has a bitrate which is smaller than 700 Mbit/sec the delays provided by DL1/8 are increased, whereas those provided by DL9/11 are maintained constant. The above described synchronizing circuit operates as follows, it being supposed - as an example - that :

- the counter FF6/8 stores the value 4 so that Q8=1 and Q7=Q6=0,

- the counter FF9/10 stores the value 0, - the flipflop FF1 is in the reset position wherein Q11=0;

- the delay units DL12 and DL13 are not considered, their effect being explained later.

The clock signal CL1 is equal to CL as follows from relation (7) given on page 16 because the control signal Q11 applied to EXOR3 is equal to 0. In the frequency divider FD the frequency of this clock signal CLl is divided by 32 so that the clock signal CL2 has a frequency equal to 21.875 MHz. When the 700 Mbit/sec binary input signal DIN is applied to the data input DIN of the delay circuit DLC it is fed through the fan-out buffer F02 and the delay unit DL5 to the fifth input of the multiplexer MUX. Indeed, this delay unit DL5 is selected by the selection signals Q8,Q7,Q6=1,0,0. The thus delayed input signal DIN1 appears at the output DIN1 of the multiplexer MUX.

It is then further delayed in the delay units DL9, DL10 and DL11 of the sampling circuit SC. The input signal DIN and the signals D9, D10 and D11 appearing at the outputs of these units are represented in Fig. 2.

The latter signals D9/10 are the sampled at the sampling instance X defined by the raising edge of the clock signal CL1. As a consequence the 3 sample values 1, 1, 0 forming a set of three are stored in FF1, FF2 and FF3 respectively so that the output signals D4 and D5 of the gate EXOR1 and EXOR2 become equal to 0 and 1 respectively, as follows from the relations (1) and (2). The signal stored in FF2 and provided at the output Q2 or DOUT thereof is the data output signal DOUT which is the complement of the sample QB2. Because the samples of the set are different this output signal and the clock signal are considered not to be synchronized. To realise this synchronism the samples should be equal and from Fig. 2 it follows that to reach this goal the sample of the delayed signal D11 should be subjected together with D9 and D10, to a delay smaller than that provided by DL5. This is realised by the decision circuit DC, as explained hereinafter.

Although the output signals D4/5 are provided at the frequency of the clock signal CL1 they are only evaluated in the decision circuit DC by the clock signal CL2 (CL3 when considering DL12) whose frequency is 32 times smaller than that of CL1. Thus the decision circuit DC may be made of components which are less expensive than those of the delay circuit DL6 which uses high speed gallium arsenide technology. Supposing that the output signals D4/5 are still equal to 0 and 1 at the moment (X) they are sampled by a raising edge of the clock signal CL2 these values are registered in the D-flipflops FF4 and FF5 so that the outputs U and D thereof become equal to 0 and 1 respectively. From the above relations (3) to (6) it follows that the decision circuit DC then decrements the counter FF6/8 by 1 from the value 100 to the value 011 as a consequence of which the delay unit DL4 is then substituted for the delay unit DL5.

Thus the time position of each set of three samples with respect to the bit period is modified, as clearly visible in Fig. 2 which shows D9, D10 and D11 subjected to delays depending on DL5 and DL4 respectively.

Instead of modifying this time position by subjecting the input signal DIN to three different delays and maintaining the clock position unmodified, it is also possible to attain the same goal by maintaining the input signal unmodified and subjecting the clock signal to three different delays. Also, instead of taking sets of three samples it is also possible to use sets of two samples. The input signal which is thus subjected to the smaller delay provided by the delay unit DL4 is processed in the way described above. The decision circuit DC thereby again checks the output D4/5 provided by the exclusive OR-ing of sets of three samples and either detects that these samples are equal, thus indicating that synchronism is reached, or not. In the affirmative no further actions are taken, whereas in the negative the delay is again changed, etc.

In principle, by proceeding in this way, i.e. by modifying the time position of the sets of samples, synchronism will finally be reached. However, it has been found that this may require a considerable time because due to phase jitter it may happen that a long series of sets whose samples are different is generated. The time required to reach synchronism under these adverse circumstances is now reduced in the way described hereinafter .

Assuming that sets are generated whose samples are different, so that U=1, D=0 or U=0, D=1, then it is clear that the ring counter FF6/8 will be incremented in a stepwise manner from an arbitrary previous value, e.g. 4, to the maximum value 7 or be decremented from this arbitrary value to the minimum value 0 respectively.

When for this maximum or minimum delay value the samples of the following set are still different and such that U=1, D=0 or U=0, D=1 respectively, this means that the delay is still too small or too large respectively. This fact is registered in the counter FF9/10. Indeed, in both cases the output E of PAL1 becomes activated due to which the counter FF9/10 is stepped to its position 1 wherein D10=0 and D9=1, as follows from what has been mentioned above in relation to PAL1 and PAL2.

When afterwards the samples of the sets investigated by the decision circuit DC are still found different, i.e. when the absence of synchronism persists, the counter FF6/8 is again stepped and it thereby varies the delay by means of the delay units DL1/8. In a similar way as described above, each time the counter FF6/7 is stepped from position 7 to 0 or vice-versa, thus decreasing or increasing the delay by T/2 respectively, the output E of PAL1 becomes activated and this fact is registered in the counter FF9/10. When the latter is finally stepped from position 3 to 0 this means that notwithstanding the various attempts to reach synchronism by varying the delay over substantially one half of a bit period and by means of DLl/8 no such synchronism was reached.

For this reason when the counter FF9/10 is stepped (after at least 4 steps) from position 3 to 0, i.e. when a predetermined lack of synchronism is reached, it sets the D-flipflop FFll due to which the output Q11 thereof becomes activated. From the relation (7) it follows that the clock signal CL1 is then inverted from CL to CLB. As a consequence a common delay equal to T/2 , is added to the delay provided by DL1/8 or to the delays provided at the outputs D9/11 of DL 9/11 so that the samples taken by the sampling circuit will then cover another half bit period than that which was previously covered by varying the delays DL1/8. The reason for introducing in these circumstances such a phase shift equal to T/2 is based on the following insight : because the previously taken samples of the sets were different even after at least 4 attempts were made to reach synchronism , they were repeatedly taken in the neighbourhood of edges of the three delayed versions D9/11 of the input signal. Indeed, even if only 4 attempts were made, these must necessarily have been due to the counter FF6/7 stepping alternately from position 0 to 7 and vice-versa. Hence, by immediately thereafter taking these samples half a bit period later the probability of still having sets whose samples are different due to phase jitter is reduced. This is for instance so for the samples taken from the signals D9/10/11 shown in Fig. 2 for which the change of sampling instant from X to Y indicates that this will lead to phase synchronism which would only fail if at that instant the DIN input signal was simultaneously subjected to a spurious sudden delay of the order to T/2.

In connection with the above, and still without considering the delay units DL12/13, it should be noted that the sampling operation by the clock signal CL2 is followed by the processing of the samples in the PALI and in the PAL2 and finally by the storage of the result in the D-flipflops FF6/11. To take this processing time into account the latter storage operation is delayed with respect to the sampling operation by half a period of the clock signal CL2. Indeed, it is performed under the control of the clock signal CL4 which is the complement of CL2 and obtained by inverting CL2 in the inverter INV. As described above, the signals D9/11 are sampled by a raising edge of the clock signal CL1 and are then gated in EXOR1/2 before being sampled by a raising edge of the clock signal CL2. In order that this edge should coincide with stable output signals D4 and D5 of these gates it is delayed by a suitable time interval in the delay unit DL12.

Since, the delay unit DL12 has been introduced and in order not to influence the above described function of the inverter INV a delay DL13 substantially equal to DL12 is used to delay the clock signal CL4 before applying it to the clock inputs of FF6/8.

While the principles of the invention have been described above in connection with specific apparatus, it is to be clearly understood that this description is made only by way of example and not as a limitation on the scope of the invention.

D4 = QB1.Q2+QB2.Q1 (1)

D5 = QB2.Q3+QB3.Q2 (2)

D6. = (DB.UB+D.U).Q6 + (DB.U+D.UB).QB6 (3) D7 = (DB.UB+D.U).Q7 + DB.U.Q6.QB7 + D.UB.QB6.QB7 + U . QB6.Q7+UB.Q6.Q7 (4)

D8 = D.UB.QB6.QB7.QB8 + DB.U.Q6.Q7.QB8 + Q6.QB7.Q8 + QB6.Q7.Q8 + DB . UB . Q8

+ U.QB7.Q8 + D.Q6.Q8 (5)

E = DB.U.Q6.Q7.Q8 + D .UB . QB6.QB7. QB8 (6) CL1 = CL.QB11 + CLB.Q11 (7)

Claims

1. Synchronizing circuit including a variable delay circuit (DLC), through which an input signal (DIN) is passed to adjust the phase of a regenerated output signal (DIN1) with respect to a clock signal (CL1) at the frequency of the input signal, and a decision circuit (DC) to determine whether a phase lead or a phase lag of said output signal (DIN1) leads to synchronism and to adjust the variable delay (DL1/8) accordingly, characterized in that said decision circuit (DC) is able to adjust said variable delay (DL1/8) so that it covers a first part (T/2) of a period (T) of said input signal (DIN) and after having detected a predetermined lack of synchronism when using said variable delay it modifies the value thereof by an additional delay such that the variable delay may then be adjusted to cover a second part (T/2) of said period (T).

2. Synchronizing circuit according to claim 1, characterized in that said first and second parts are each equal to half (T/2) said period (T).

3. Synchronizing circuit according to claim 2, characterized in that said clock signal (CL1) is a square wave and that said decision circuit (DC) reverses the phase of said square wave to secure said additional delay.

4. Synchronizing circuit according to claim 1, wherein said decision circuit (DC) is able to increase/decrease said variable delay (DL1/8) by a predetermined value (T/2) equal to half the signal period when it detects that for the minimum/maximum value of said variable delay the latter has still to be decreased/increased respectively to reach synchronism, characterised in that said decision circuit (DC) after having modified said variable delay (DL1/8) by said predetermined value (T/2) at least two times, changes the value of said variable delay by said additional delay and that said decision circuit prior and after this change modifies the value of said variable delay in a bidirectional and cyclic way .

5. Synchronizing circuit according to claim 3, characterized in that it further includes a sampling circuit (SC) able to generate at least two differently delayed versions (DL9/11) of said output signal and to sample these versions simultaneously by said clock signal (CL1) so as to provide a set of samples, that said decision circuit (DC) detects for at least part of said sets if synchronism is reached or not by checking if the samples thereof are the same or not respectively and adjusts said variable delay (DL1/8) when the samples are different, and that said decision circuit (DC) after having detected that the samples of each of a number of sets are different concludes that said predetermined lack of synchronism is reached and accordingly reverses the phase of said clock signal (CL1).

6. Synchronizing circuit according to claims 3 and 4, characterized in that said decision circuit (DC) includes a bidirectional first counter (FF6/8) which is a ring counter able to be stepped through various positions and to accordingly control via its output signals (Q6/8) said delay circuit (DLC) to bidirectionnally and cyclically vary the delay (DL1/8) established thereby, two adjacent predetermined ones (0,7) of said counter positions corresponding to said minimum (DL1) and said maximum (DL8) delay value respectively, and that said decision circuit (DC) further includes a unidirectional second counter (FF9/10) which is stepped each time said first counter (FF6/8) is brought from one to the other of said two predetermined positions and vice-versa and which when having been stepped at least said two times, thus indicating said predetermined lack of synchronism, reverses the phase of said clock signal (CL1).

7. Synchronizing circuit according to claims 5 and

6, characterized in that said delay circuit (DC) includes a plurality of first delay units (DL1/8) which constitute said variable delay and are each connected between a common data input (DIN) and a respective input of a multiplexer circuit (MUX) whose output (DIN1)is connected through further parallel connected second delay units (DL9/11) which provide said delayed versions, the selection inputs (Q6/8) of said multiplexer being controlled by said output signals (Q6/8) of said first counter (FF6/8).

8. Synchronizing circuit according to claim 7, characterized in that said sampling circuit (SC) includes three of said second delay units (DL9/11) providing three differently delayed versions (DL9/1), that said sampling circuit (SC9 when sampling these versions generates three successive phase shifted first, second and third samples at its respective first (QB1), second (QB2) and third (QB3) outputs and that said decision circuit (DC) further includes first (EXOR1) and second (EXOR2) exclusive-OR gates to which said first and second and said second and third outputs of said sampling circuit (SC) are coupled respectively and which has outputs connected to a second sampling circuit (FF4/5) which is controlled by a second clock signal (CL3) having a frequency which is much smaller than that of said first clock signal (CL1), said second sampling circuit providing output signals (U, D) which control said first counter and indicate thereto that the variable delay has to be maintained unmodified (U=D), increased (U=1, D=0) or decreased (U=0, D=1).

9. Synchronizing circuit according to claim 8, characterized in that said outputs (U, D) of said second sampling circuit CFF9/10) are coupled to logic circuitry (PALI) associated to said first counter (FF6/8).