FI20011922A0 - Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur - Google Patents
Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstrukturInfo
- Publication number
- FI20011922A0 FI20011922A0 FI20011922A FI20011922A FI20011922A0 FI 20011922 A0 FI20011922 A0 FI 20011922A0 FI 20011922 A FI20011922 A FI 20011922A FI 20011922 A FI20011922 A FI 20011922A FI 20011922 A0 FI20011922 A0 FI 20011922A0
- Authority
- FI
- Finland
- Prior art keywords
- layer
- cavities
- cavity structure
- soi wafer
- silicon
- Prior art date
Links
- 238000000034 method Methods 0.000 title abstract 3
- XUIMIQQOPSSXEZ-UHFFFAOYSA-N Silicon Chemical compound [Si] XUIMIQQOPSSXEZ-UHFFFAOYSA-N 0.000 abstract 4
- 229910052710 silicon Inorganic materials 0.000 abstract 4
- 239000010703 silicon Substances 0.000 abstract 4
- 238000005530 etching Methods 0.000 abstract 1
- 239000007789 gas Substances 0.000 abstract 1
- 238000004519 manufacturing process Methods 0.000 abstract 1
- 239000000463 material Substances 0.000 abstract 1
- 229910021421 monocrystalline silicon Inorganic materials 0.000 abstract 1
- 235000012431 wafers Nutrition 0.000 abstract 1
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
- H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
- H01L21/18—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
- H01L21/30—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
- H01L21/322—Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00015—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
- B81C1/00023—Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
- B81C1/00047—Cavities
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C1/00—Manufacture or treatment of devices or systems in or on a substrate
- B81C1/00388—Etch mask forming
- B81C1/00412—Mask characterised by its behaviour during the etching process, e.g. soluble masks
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
- H01L21/70—Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
- H01L21/71—Manufacture of specific parts of devices defined in group H01L21/70
- H01L21/76—Making of isolation regions between components
- H01L21/762—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
- H01L21/7624—Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
- H01L21/76264—SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
- H01L21/76286—Lateral isolation by refilling of trenches with polycristalline material
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2201/00—Manufacture or treatment of microstructural devices or systems
- B81C2201/01—Manufacture or treatment of microstructural devices or systems in or on a substrate
- B81C2201/0101—Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
- B81C2201/0111—Bulk micromachining
- B81C2201/0115—Porous silicon
-
- B—PERFORMING OPERATIONS; TRANSPORTING
- B81—MICROSTRUCTURAL TECHNOLOGY
- B81C—PROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
- B81C2203/00—Forming microstructural systems
- B81C2203/01—Packaging MEMS
- B81C2203/0145—Hermetically sealing an opening in the lid
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/47—Structure, shape, material or disposition of the wire connectors after the connecting process
- H01L2224/48—Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
- H01L2224/4805—Shape
- H01L2224/4809—Loop shape
- H01L2224/48091—Arched
Landscapes
- Engineering & Computer Science (AREA)
- Manufacturing & Machinery (AREA)
- Microelectronics & Electronic Packaging (AREA)
- Power Engineering (AREA)
- Physics & Mathematics (AREA)
- Condensed Matter Physics & Semiconductors (AREA)
- General Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- Analytical Chemistry (AREA)
- Chemical & Material Sciences (AREA)
- Pressure Sensors (AREA)
- Micromachines (AREA)
- Drying Of Semiconductors (AREA)
- Element Separation (AREA)
Priority Applications (8)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20011922A FI114755B (sv) | 2001-10-01 | 2001-10-01 | Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur |
JP2003533331A JP2005504644A (ja) | 2001-10-01 | 2002-09-27 | Soi基板にキャビティ構造を形成する方法およびsoi基板に形成されたキャビティ構造 |
EP02764899.7A EP1433199B1 (en) | 2001-10-01 | 2002-09-27 | Method for forming a cavity structure in an soi substrate and cavity structure formed in an soi substrate |
PCT/FI2002/000772 WO2003030234A1 (en) | 2001-10-01 | 2002-09-27 | Method for forming a cavity structure on soi substrate and cavity structure formed on soi substrate |
CNB028194314A CN1288724C (zh) | 2001-10-01 | 2002-09-27 | 在绝缘体上硅基底上形成腔结构的方法 |
US10/491,193 US6930366B2 (en) | 2001-10-01 | 2002-09-27 | Method for forming a cavity structure on SOI substrate and cavity structure formed on SOI substrate |
KR1020047004728A KR100889115B1 (ko) | 2001-10-01 | 2002-09-27 | Soi 기판상에 공동구조를 형성하는 방법 및 soi기판상에 형성된 공동구조 |
HK05105143A HK1072497A1 (en) | 2001-10-01 | 2005-06-21 | Method for forming a cavity structure on soil substrate |
Applications Claiming Priority (2)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
FI20011922 | 2001-10-01 | ||
FI20011922A FI114755B (sv) | 2001-10-01 | 2001-10-01 | Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur |
Publications (3)
Publication Number | Publication Date |
---|---|
FI20011922A0 true FI20011922A0 (sv) | 2001-10-01 |
FI20011922A FI20011922A (sv) | 2003-04-02 |
FI114755B FI114755B (sv) | 2004-12-15 |
Family
ID=8561984
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
FI20011922A FI114755B (sv) | 2001-10-01 | 2001-10-01 | Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur |
Country Status (8)
Country | Link |
---|---|
US (1) | US6930366B2 (sv) |
EP (1) | EP1433199B1 (sv) |
JP (1) | JP2005504644A (sv) |
KR (1) | KR100889115B1 (sv) |
CN (1) | CN1288724C (sv) |
FI (1) | FI114755B (sv) |
HK (1) | HK1072497A1 (sv) |
WO (1) | WO2003030234A1 (sv) |
Families Citing this family (17)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US7625603B2 (en) * | 2003-11-14 | 2009-12-01 | Robert Bosch Gmbh | Crack and residue free conformal deposited silicon oxide with predictable and uniform etching characteristics |
WO2005089348A2 (en) * | 2004-03-15 | 2005-09-29 | Georgia Tech Research Corporation | Packaging for micro electro-mechanical systems and methods of fabricating thereof |
US7292111B2 (en) * | 2004-04-26 | 2007-11-06 | Northrop Grumman Corporation | Middle layer of die structure that comprises a cavity that holds an alkali metal |
JP4534622B2 (ja) * | 2004-06-23 | 2010-09-01 | ソニー株式会社 | 機能素子およびその製造方法、流体吐出ヘッド、並びに印刷装置 |
KR100579490B1 (ko) * | 2004-09-20 | 2006-05-15 | 삼성전자주식회사 | 실리콘 절연체 실리콘 구조물 및 그 제조방법 |
US7303936B2 (en) * | 2005-04-13 | 2007-12-04 | Delphi Technologies, Inc. | Method for forming anti-stiction bumps on a micro-electro mechanical structure |
CN101456532B (zh) * | 2005-07-04 | 2012-06-20 | 俞度立 | 微涡卷叶片及微涡卷基板的制造方法 |
DE102008002332B4 (de) * | 2008-06-10 | 2017-02-09 | Robert Bosch Gmbh | Verfahren zur Herstellung einer mikromechanischen Membranstruktur mit Zugang von der Substratrückseite |
US8877648B2 (en) * | 2009-03-26 | 2014-11-04 | Semprius, Inc. | Methods of forming printable integrated circuit devices by selective etching to suspend the devices from a handling substrate and devices formed thereby |
KR101298114B1 (ko) * | 2009-06-02 | 2013-08-20 | 한국과학기술원 | Mems 또는 mems 소자의 패키지 및 패키징 방법 |
DE102010006769A1 (de) * | 2010-02-04 | 2014-10-30 | Dominik Mösch | Verfahren zur Herstellung von kleinen Hohlräumen oder Maskierungen/Strukturen in der Halbleiterindustrie, Mikroelektronik, Mikrosystemtechnik o.ä. anhand von Substanzen mit einem geringen Schmelz- und Siedepunkt |
DE102010008044B4 (de) | 2010-02-16 | 2016-11-24 | Epcos Ag | MEMS-Mikrofon und Verfahren zur Herstellung |
CH708827A2 (fr) * | 2013-11-08 | 2015-05-15 | Nivarox Sa | Pièce de micromécanique creuse, à plusieurs niveaux fonctionnels et monobloc en un matériau à base d'un allotrope synthétique du carbone. |
CN103926028B (zh) * | 2014-03-25 | 2016-05-18 | 慧石(上海)测控科技有限公司 | 一种应变片的结构设计及制作工艺 |
CN103926034B (zh) * | 2014-03-25 | 2016-08-31 | 慧石(上海)测控科技有限公司 | 硅压力芯片结构设计及工艺 |
FI128447B (sv) | 2016-04-26 | 2020-05-15 | Teknologian Tutkimuskeskus Vtt Oy | Anordning förknippad med analys av tunnfilmsskikt och förfarande för framställning därav |
CN114267628A (zh) * | 2021-03-24 | 2022-04-01 | 青岛昇瑞光电科技有限公司 | 超薄绝缘体上硅(soi)衬底基片及其制备方法 |
Family Cites Families (9)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
FR2700003B1 (fr) * | 1992-12-28 | 1995-02-10 | Commissariat Energie Atomique | Procédé de fabrication d'un capteur de pression utilisant la technologie silicium sur isolant et capteur obtenu. |
SE9304145D0 (sv) * | 1993-12-10 | 1993-12-10 | Pharmacia Lkb Biotech | Sätt att tillverka hålrumsstrukturer |
US5942802A (en) * | 1995-10-09 | 1999-08-24 | Matsushita Electric Industrial Co., Ltd. | Semiconductor device and method of producing the same |
DE69627645T2 (de) | 1996-07-31 | 2004-02-05 | Stmicroelectronics S.R.L., Agrate Brianza | Integrierter piezoresistiver Druckwandler und Herstellungsverfahren dazu |
US6093330A (en) | 1997-06-02 | 2000-07-25 | Cornell Research Foundation, Inc. | Microfabrication process for enclosed microstructures |
EP1062684B1 (en) * | 1998-01-15 | 2010-06-09 | Cornell Research Foundation, Inc. | Trench isolation for micromechanical devices |
JP2000124469A (ja) * | 1998-10-13 | 2000-04-28 | Toyota Central Res & Dev Lab Inc | 微小密閉容器及びその製造方法 |
JP4168497B2 (ja) * | 1998-10-13 | 2008-10-22 | 株式会社デンソー | 半導体力学量センサの製造方法 |
EP1077475A3 (en) * | 1999-08-11 | 2003-04-02 | Applied Materials, Inc. | Method of micromachining a multi-part cavity |
-
2001
- 2001-10-01 FI FI20011922A patent/FI114755B/sv not_active IP Right Cessation
-
2002
- 2002-09-27 EP EP02764899.7A patent/EP1433199B1/en not_active Expired - Lifetime
- 2002-09-27 KR KR1020047004728A patent/KR100889115B1/ko active IP Right Grant
- 2002-09-27 JP JP2003533331A patent/JP2005504644A/ja active Pending
- 2002-09-27 WO PCT/FI2002/000772 patent/WO2003030234A1/en active Application Filing
- 2002-09-27 US US10/491,193 patent/US6930366B2/en not_active Expired - Lifetime
- 2002-09-27 CN CNB028194314A patent/CN1288724C/zh not_active Expired - Lifetime
-
2005
- 2005-06-21 HK HK05105143A patent/HK1072497A1/xx not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100889115B1 (ko) | 2009-03-16 |
WO2003030234A1 (en) | 2003-04-10 |
HK1072497A1 (en) | 2005-08-26 |
US20040248376A1 (en) | 2004-12-09 |
CN1288724C (zh) | 2006-12-06 |
US6930366B2 (en) | 2005-08-16 |
FI20011922A (sv) | 2003-04-02 |
EP1433199B1 (en) | 2013-11-06 |
EP1433199A1 (en) | 2004-06-30 |
CN1561539A (zh) | 2005-01-05 |
JP2005504644A (ja) | 2005-02-17 |
FI114755B (sv) | 2004-12-15 |
KR20040037218A (ko) | 2004-05-04 |
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Legal Events
Date | Code | Title | Description |
---|---|---|---|
MA | Patent expired |