FI114755B - Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur - Google Patents

Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur Download PDF

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Publication number
FI114755B
FI114755B FI20011922A FI20011922A FI114755B FI 114755 B FI114755 B FI 114755B FI 20011922 A FI20011922 A FI 20011922A FI 20011922 A FI20011922 A FI 20011922A FI 114755 B FI114755 B FI 114755B
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FI
Finland
Prior art keywords
layer
silicon
cavity
cavities
layers
Prior art date
Application number
FI20011922A
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English (en)
Finnish (fi)
Other versions
FI20011922A0 (sv
FI20011922A (sv
Inventor
Jyrki Kiihamaeki
Original Assignee
Valtion Teknillinen
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Valtion Teknillinen filed Critical Valtion Teknillinen
Publication of FI20011922A0 publication Critical patent/FI20011922A0/sv
Priority to FI20011922A priority Critical patent/FI114755B/sv
Priority to EP02764899.7A priority patent/EP1433199B1/en
Priority to KR1020047004728A priority patent/KR100889115B1/ko
Priority to PCT/FI2002/000772 priority patent/WO2003030234A1/en
Priority to JP2003533331A priority patent/JP2005504644A/ja
Priority to CNB028194314A priority patent/CN1288724C/zh
Priority to US10/491,193 priority patent/US6930366B2/en
Publication of FI20011922A publication Critical patent/FI20011922A/sv
Application granted granted Critical
Publication of FI114755B publication Critical patent/FI114755B/sv
Priority to HK05105143A priority patent/HK1072497A1/xx

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Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/18Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer the devices having semiconductor bodies comprising elements of Group IV of the Periodic Table or AIIIBV compounds with or without impurities, e.g. doping materials
    • H01L21/30Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26
    • H01L21/322Treatment of semiconductor bodies using processes or apparatus not provided for in groups H01L21/20 - H01L21/26 to modify their internal properties, e.g. to produce internal imperfections
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00015Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems
    • B81C1/00023Manufacture or treatment of devices or systems in or on a substrate for manufacturing microsystems without movable or flexible elements
    • B81C1/00047Cavities
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C1/00Manufacture or treatment of devices or systems in or on a substrate
    • B81C1/00388Etch mask forming
    • B81C1/00412Mask characterised by its behaviour during the etching process, e.g. soluble masks
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/70Manufacture or treatment of devices consisting of a plurality of solid state components formed in or on a common substrate or of parts thereof; Manufacture of integrated circuit devices or of parts thereof
    • H01L21/71Manufacture of specific parts of devices defined in group H01L21/70
    • H01L21/76Making of isolation regions between components
    • H01L21/762Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers
    • H01L21/7624Dielectric regions, e.g. EPIC dielectric isolation, LOCOS; Trench refilling techniques, SOI technology, use of channel stoppers using semiconductor on insulator [SOI] technology
    • H01L21/76264SOI together with lateral isolation, e.g. using local oxidation of silicon, or dielectric or polycristalline material refilled trench or air gap isolation regions, e.g. completely isolated semiconductor islands
    • H01L21/76286Lateral isolation by refilling of trenches with polycristalline material
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2201/00Manufacture or treatment of microstructural devices or systems
    • B81C2201/01Manufacture or treatment of microstructural devices or systems in or on a substrate
    • B81C2201/0101Shaping material; Structuring the bulk substrate or layers on the substrate; Film patterning
    • B81C2201/0111Bulk micromachining
    • B81C2201/0115Porous silicon
    • BPERFORMING OPERATIONS; TRANSPORTING
    • B81MICROSTRUCTURAL TECHNOLOGY
    • B81CPROCESSES OR APPARATUS SPECIALLY ADAPTED FOR THE MANUFACTURE OR TREATMENT OF MICROSTRUCTURAL DEVICES OR SYSTEMS
    • B81C2203/00Forming microstructural systems
    • B81C2203/01Packaging MEMS
    • B81C2203/0145Hermetically sealing an opening in the lid
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/42Wire connectors; Manufacturing methods related thereto
    • H01L2224/47Structure, shape, material or disposition of the wire connectors after the connecting process
    • H01L2224/48Structure, shape, material or disposition of the wire connectors after the connecting process of an individual wire connector
    • H01L2224/4805Shape
    • H01L2224/4809Loop shape
    • H01L2224/48091Arched

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  • Engineering & Computer Science (AREA)
  • Manufacturing & Machinery (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Analytical Chemistry (AREA)
  • Chemical & Material Sciences (AREA)
  • Pressure Sensors (AREA)
  • Micromachines (AREA)
  • Drying Of Semiconductors (AREA)
  • Element Separation (AREA)

Claims (6)

1. Förfarande för utformning av kaviteter i förtillverkade kiselskivor bestäende av ett första kiselskikt (1), ett andra enkristallint kiselskikt, ett sä kallat strukturskikt (3) väsentligen parallellt med det första kiselskiktet (1) samt av ett isoleringsskikt (2) 5 anordnat mellan skikten (1,3), vid vilket förfarande - i ätminstone det ena kiselskiktet (1,3) formas häl (4), som sträcker sig igenom skiktet, - fördjupningar etsas i isoleringsskiktet (2) med hjälp av etsningsmedel ledda via de bildade hälen (4), 10 kännetecknat av att - efter hälens (4) utformning och före etsningsfasen bildas pä den yta som skall behandlas ett tunt poröst skikt (5), genom vilket etsningsmedlen bringas att ledas tili de kaviteter (6) som skall etsas, och - efter kavitetemas (6) utformning bildas ätminstone ett tilläggsskikt (7) för att 15 ändra det porösa materialet tili att bli ogenomträngligt för gas.
2. Förfarande enligt patentkrav 1, kännetecknat av att i samband med hälens (4) . utformning formas även i isoleringsskiktet (2) en fördjupning (8), som i samband med ! skiktens (5 och 7) utformning ästadkommer en knottra (9), som sträcker sig in i , ; *, kaviteten (6). ,,,,; 20
3. Förfarande enligt patentkrav 1 eller 2, kännetecknat av att behandlingsytan hos det , * * ·. skikt (1,3) väri hälen (4) utformas väsentligen utplanas för att härtill ansluta integrerade komponenter (13) och metalleringar.
, · · ·. 4. Kavitetsstruktur i en förtillverkad kiselskiva bestäende av ett första kiselskikt (1), ett * f I . ‘ , andra enkristallint kiselskikt, ett sä kallat strukturskikt (3) väsentligen parallellt med det 25 första kiselskiktet (1) samt av ett isoleringsskikt (2) anordnat mellan skikten (1, 3), varvid • * ‘ - kavitetsstrukturen (6) är formad ätminstone väsentligen i isoleringsskiktet (2) mellan det första (1) och andra (3) kiselskiktet, och - ätminstone en sluten hälstruktur (4, 5, 7) avgränsar varje kavitet (6), 114755 kännetecknad av att - den mot kaviteten (6) belägna änden av den slutna hälstrukturen (4, 5, 7) uppvisar ätminstone ett poröst skikt (5), genom vilket etsningsmedel i tillverkningsfasen är bringade att ledas tili de kaviteter (6) som skall etsas, och 5 - den slutna hälstrukturen (4, 5, 7) uppvisar ätminstone ett tilläggsskikt (7) för att ändra det porösa materialet tili att bli ogenomträngligt för gas.
5. Kavitetsstruktur enligt patentkrav 4, kannetecknat av att hälstrukturen (4, 5, 7) bildar en knottra (9), som sträcker sig in i kaviteten (6).
6. Kavitetsstruktur enligt patentkrav 4 eller 5, kannetecknat av att behandlingsytan hos 10 det skikt (1, 3) väri hälstrukturen (4, 5, 7) bildas är väsentligen utplanad för att härtill ansluta integrerade komponenter (13) och metalleringar. i · tilli I » tl» » 1 » » I t * » I | • I 1 >
FI20011922A 2001-10-01 2001-10-01 Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur FI114755B (sv)

Priority Applications (8)

Application Number Priority Date Filing Date Title
FI20011922A FI114755B (sv) 2001-10-01 2001-10-01 Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur
JP2003533331A JP2005504644A (ja) 2001-10-01 2002-09-27 Soi基板にキャビティ構造を形成する方法およびsoi基板に形成されたキャビティ構造
KR1020047004728A KR100889115B1 (ko) 2001-10-01 2002-09-27 Soi 기판상에 공동구조를 형성하는 방법 및 soi기판상에 형성된 공동구조
PCT/FI2002/000772 WO2003030234A1 (en) 2001-10-01 2002-09-27 Method for forming a cavity structure on soi substrate and cavity structure formed on soi substrate
EP02764899.7A EP1433199B1 (en) 2001-10-01 2002-09-27 Method for forming a cavity structure in an soi substrate and cavity structure formed in an soi substrate
CNB028194314A CN1288724C (zh) 2001-10-01 2002-09-27 在绝缘体上硅基底上形成腔结构的方法
US10/491,193 US6930366B2 (en) 2001-10-01 2002-09-27 Method for forming a cavity structure on SOI substrate and cavity structure formed on SOI substrate
HK05105143A HK1072497A1 (en) 2001-10-01 2005-06-21 Method for forming a cavity structure on soil substrate

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
FI20011922A FI114755B (sv) 2001-10-01 2001-10-01 Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur
FI20011922 2001-10-01

Publications (3)

Publication Number Publication Date
FI20011922A0 FI20011922A0 (sv) 2001-10-01
FI20011922A FI20011922A (sv) 2003-04-02
FI114755B true FI114755B (sv) 2004-12-15

Family

ID=8561984

Family Applications (1)

Application Number Title Priority Date Filing Date
FI20011922A FI114755B (sv) 2001-10-01 2001-10-01 Förfarande för utformning av en kavitetsstruktur för en SOI-skiva samt en SOI-skivas kavitetsstruktur

Country Status (8)

Country Link
US (1) US6930366B2 (sv)
EP (1) EP1433199B1 (sv)
JP (1) JP2005504644A (sv)
KR (1) KR100889115B1 (sv)
CN (1) CN1288724C (sv)
FI (1) FI114755B (sv)
HK (1) HK1072497A1 (sv)
WO (1) WO2003030234A1 (sv)

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JP4534622B2 (ja) * 2004-06-23 2010-09-01 ソニー株式会社 機能素子およびその製造方法、流体吐出ヘッド、並びに印刷装置
KR100579490B1 (ko) * 2004-09-20 2006-05-15 삼성전자주식회사 실리콘 절연체 실리콘 구조물 및 그 제조방법
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CN101456532B (zh) * 2005-07-04 2012-06-20 俞度立 微涡卷叶片及微涡卷基板的制造方法
DE102008002332B4 (de) * 2008-06-10 2017-02-09 Robert Bosch Gmbh Verfahren zur Herstellung einer mikromechanischen Membranstruktur mit Zugang von der Substratrückseite
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KR101298114B1 (ko) * 2009-06-02 2013-08-20 한국과학기술원 Mems 또는 mems 소자의 패키지 및 패키징 방법
DE102010006769A1 (de) * 2010-02-04 2014-10-30 Dominik Mösch Verfahren zur Herstellung von kleinen Hohlräumen oder Maskierungen/Strukturen in der Halbleiterindustrie, Mikroelektronik, Mikrosystemtechnik o.ä. anhand von Substanzen mit einem geringen Schmelz- und Siedepunkt
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CN103926028B (zh) * 2014-03-25 2016-05-18 慧石(上海)测控科技有限公司 一种应变片的结构设计及制作工艺
FI128447B (sv) 2016-04-26 2020-05-15 Teknologian Tutkimuskeskus Vtt Oy Anordning förknippad med analys av tunnfilmsskikt och förfarande för framställning därav
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Also Published As

Publication number Publication date
HK1072497A1 (en) 2005-08-26
US20040248376A1 (en) 2004-12-09
JP2005504644A (ja) 2005-02-17
EP1433199B1 (en) 2013-11-06
CN1561539A (zh) 2005-01-05
WO2003030234A1 (en) 2003-04-10
KR100889115B1 (ko) 2009-03-16
CN1288724C (zh) 2006-12-06
EP1433199A1 (en) 2004-06-30
FI20011922A0 (sv) 2001-10-01
FI20011922A (sv) 2003-04-02
KR20040037218A (ko) 2004-05-04
US6930366B2 (en) 2005-08-16

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