ES2583328T3 - Sistema y procedimiento para reducir el uso de energía de una memoria de contenido direccionable - Google Patents
Sistema y procedimiento para reducir el uso de energía de una memoria de contenido direccionable Download PDFInfo
- Publication number
- ES2583328T3 ES2583328T3 ES11749322.1T ES11749322T ES2583328T3 ES 2583328 T3 ES2583328 T3 ES 2583328T3 ES 11749322 T ES11749322 T ES 11749322T ES 2583328 T3 ES2583328 T3 ES 2583328T3
- Authority
- ES
- Spain
- Prior art keywords
- bank
- valid data
- addressable memory
- content addressable
- procedure
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Active
Links
Classifications
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C15/00—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores
- G11C15/04—Digital stores in which information comprising one or more characteristic parts is written into the store and in which information is read-out by searching for one or more of these characteristic parts, i.e. associative or content-addressed stores using semiconductor elements
-
- G—PHYSICS
- G11—INFORMATION STORAGE
- G11C—STATIC STORES
- G11C5/00—Details of stores covered by group G11C11/00
- G11C5/14—Power supply arrangements, e.g. power down, chip selection or deselection, layout of wirings or power grids, or multiple supply levels
Landscapes
- Engineering & Computer Science (AREA)
- Power Engineering (AREA)
- Power Sources (AREA)
- Memory System Of A Hierarchy Structure (AREA)
- Information Retrieval, Db Structures And Fs Structures Therefor (AREA)
Applications Claiming Priority (3)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| US12/862,277 US8984217B2 (en) | 2010-08-24 | 2010-08-24 | System and method of reducing power usage of a content addressable memory |
| US862277 | 2010-08-24 | ||
| PCT/US2011/048892 WO2012027429A1 (en) | 2010-08-24 | 2011-08-24 | System and method of reducing power usage of a content addressable memory |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| ES2583328T3 true ES2583328T3 (es) | 2016-09-20 |
Family
ID=44515072
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| ES11749322.1T Active ES2583328T3 (es) | 2010-08-24 | 2011-08-24 | Sistema y procedimiento para reducir el uso de energía de una memoria de contenido direccionable |
Country Status (8)
| Country | Link |
|---|---|
| US (1) | US8984217B2 (cg-RX-API-DMAC7.html) |
| EP (1) | EP2609595B1 (cg-RX-API-DMAC7.html) |
| JP (2) | JP2013537680A (cg-RX-API-DMAC7.html) |
| KR (1) | KR101654118B1 (cg-RX-API-DMAC7.html) |
| CN (1) | CN103069497B (cg-RX-API-DMAC7.html) |
| ES (1) | ES2583328T3 (cg-RX-API-DMAC7.html) |
| HU (1) | HUE028001T2 (cg-RX-API-DMAC7.html) |
| WO (1) | WO2012027429A1 (cg-RX-API-DMAC7.html) |
Families Citing this family (8)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US9214231B2 (en) * | 2013-01-31 | 2015-12-15 | Hewlett-Packard Development Company, L.P. | Crossbar memory to provide content addressable functionality |
| US20150279463A1 (en) * | 2014-03-31 | 2015-10-01 | Dell Products, L.P. | Adjustable non-volatile memory regions of dram-based memory module |
| JP2017097940A (ja) * | 2015-11-26 | 2017-06-01 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP6659486B2 (ja) | 2016-07-20 | 2020-03-04 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| JP2019008845A (ja) * | 2017-06-22 | 2019-01-17 | ルネサスエレクトロニクス株式会社 | 半導体装置 |
| US11347514B2 (en) * | 2019-02-15 | 2022-05-31 | Apple Inc. | Content-addressable memory filtering based on microarchitectural state |
| US10922020B2 (en) * | 2019-04-12 | 2021-02-16 | Micron Technology, Inc. | Writing and querying operations in content addressable memory systems with content addressable memory buffers |
| US11017857B2 (en) * | 2019-07-15 | 2021-05-25 | Micron Technology, Inc. | Ranged content-addressable memory |
Family Cites Families (20)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JP4246812B2 (ja) * | 1997-06-12 | 2009-04-02 | パナソニック株式会社 | 半導体回路及びその制御方法 |
| US6341327B1 (en) | 1998-08-13 | 2002-01-22 | Intel Corporation | Content addressable memory addressable by redundant form input |
| JP2000149573A (ja) | 1998-11-04 | 2000-05-30 | Internatl Business Mach Corp <Ibm> | 連想メモリ及び連想メモリのデータ検索方法 |
| JP3478749B2 (ja) | 1999-02-05 | 2003-12-15 | インターナショナル・ビジネス・マシーンズ・コーポレーション | 連想メモリ（ｃａｍ）のワードマッチラインのプリチャージ回路および方法 |
| JP2001023380A (ja) * | 1999-07-12 | 2001-01-26 | Kawasaki Steel Corp | 連想メモリ |
| JP2001167585A (ja) | 1999-12-09 | 2001-06-22 | Toshiba Corp | 連想記憶装置 |
| JP2002124088A (ja) * | 2000-10-13 | 2002-04-26 | Kawasaki Microelectronics Kk | 連想メモリ装置およびそのメモリデータ移動方法 |
| JP2003045189A (ja) | 2001-07-31 | 2003-02-14 | Fujitsu Ltd | 半導体メモリ |
| US7401180B1 (en) * | 2001-12-27 | 2008-07-15 | Netlogic Microsystems, Inc. | Content addressable memory (CAM) device having selectable access and method therefor |
| US7100013B1 (en) * | 2002-08-30 | 2006-08-29 | Nvidia Corporation | Method and apparatus for partial memory power shutoff |
| JP2004164395A (ja) | 2002-11-14 | 2004-06-10 | Renesas Technology Corp | アドレス変換装置 |
| US20040128574A1 (en) * | 2002-12-31 | 2004-07-01 | Franco Ricci | Reducing integrated circuit power consumption |
| WO2004104841A1 (ja) | 2003-05-21 | 2004-12-02 | Fujitsu Limited | アドレス変換バッファの電力制御方法及びその装置 |
| JP2005011434A (ja) * | 2003-06-19 | 2005-01-13 | Mitsubishi Electric Corp | ダイナミックメモリ制御装置及びこれを用いた携帯端末 |
| JP2006040089A (ja) * | 2004-07-29 | 2006-02-09 | Fujitsu Ltd | セカンドキャッシュ駆動制御回路、セカンドキャッシュ、ｒａｍ、及びセカンドキャッシュ駆動制御方法 |
| US20080005516A1 (en) * | 2006-06-30 | 2008-01-03 | Meinschein Robert J | Memory power management through high-speed intra-memory data transfer and dynamic memory address remapping |
| US7616468B2 (en) | 2006-08-04 | 2009-11-10 | Qualcomm Incorporated | Method and apparatus for reducing power consumption in a content addressable memory |
| KR100911189B1 (ko) * | 2007-06-11 | 2009-08-06 | 주식회사 하이닉스반도체 | 반도체 메모리 장치의 클럭 제어 회로 |
| JP2010108381A (ja) * | 2008-10-31 | 2010-05-13 | Fujitsu Ltd | 集積回路、集積回路の制御方法および半導体デバイス |
| CN102473453B (zh) | 2009-09-02 | 2014-10-22 | 松下电器产业株式会社 | 半导体存储装置 |
-
2010
- 2010-08-24 US US12/862,277 patent/US8984217B2/en active Active
-
2011
- 2011-08-24 ES ES11749322.1T patent/ES2583328T3/es active Active
- 2011-08-24 WO PCT/US2011/048892 patent/WO2012027429A1/en not_active Ceased
- 2011-08-24 EP EP11749322.1A patent/EP2609595B1/en active Active
- 2011-08-24 KR KR1020137007340A patent/KR101654118B1/ko active Active
- 2011-08-24 CN CN201180039036.5A patent/CN103069497B/zh active Active
- 2011-08-24 JP JP2013525013A patent/JP2013537680A/ja not_active Withdrawn
- 2011-08-24 HU HUE11749322A patent/HUE028001T2/en unknown
-
2015
- 2015-09-18 JP JP2015185314A patent/JP6081546B2/ja active Active
Also Published As
| Publication number | Publication date |
|---|---|
| EP2609595B1 (en) | 2016-04-27 |
| CN103069497B (zh) | 2015-10-21 |
| KR20130048787A (ko) | 2013-05-10 |
| WO2012027429A1 (en) | 2012-03-01 |
| CN103069497A (zh) | 2013-04-24 |
| US20120054426A1 (en) | 2012-03-01 |
| JP2016001515A (ja) | 2016-01-07 |
| US8984217B2 (en) | 2015-03-17 |
| JP2013537680A (ja) | 2013-10-03 |
| HUE028001T2 (en) | 2016-11-28 |
| JP6081546B2 (ja) | 2017-02-15 |
| KR101654118B1 (ko) | 2016-09-05 |
| EP2609595A1 (en) | 2013-07-03 |
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