ES2206988T3 - Circuito integrado. - Google Patents

Circuito integrado.

Info

Publication number
ES2206988T3
ES2206988T3 ES98945427T ES98945427T ES2206988T3 ES 2206988 T3 ES2206988 T3 ES 2206988T3 ES 98945427 T ES98945427 T ES 98945427T ES 98945427 T ES98945427 T ES 98945427T ES 2206988 T3 ES2206988 T3 ES 2206988T3
Authority
ES
Spain
Prior art keywords
input
circuit
amplifier
amplifier stage
input terminal
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES98945427T
Other languages
English (en)
Spanish (es)
Inventor
James Digby Yarlet Collier
Ian Michael Sabberton
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Qualcomm Technologies International Ltd
Original Assignee
Cambridge Silicon Radio Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Cambridge Silicon Radio Ltd filed Critical Cambridge Silicon Radio Ltd
Priority claimed from CA002299992A external-priority patent/CA2299992A1/en
Application granted granted Critical
Publication of ES2206988T3 publication Critical patent/ES2206988T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H03ELECTRONIC CIRCUITRY
    • H03KPULSE TECHNIQUE
    • H03K23/00Pulse counters comprising counting chains; Frequency dividers comprising counting chains
    • H03K23/40Gating or clocking signals applied to all stages, i.e. synchronous counters
    • H03K23/50Gating or clocking signals applied to all stages, i.e. synchronous counters using bi-stable regenerative trigger circuits
    • H03K23/54Ring counters, i.e. feedback shift register counters
    • H03K23/542Ring counters, i.e. feedback shift register counters with crossed-couplings, i.e. Johnson counters

Landscapes

  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Pulse Circuits (AREA)
  • Logic Circuits (AREA)
  • Amplifiers (AREA)
  • Circuits Of Receivers In General (AREA)
ES98945427T 1997-10-03 1998-10-02 Circuito integrado. Expired - Lifetime ES2206988T3 (es)

Applications Claiming Priority (3)

Application Number Priority Date Filing Date Title
GB9721082 1997-10-03
GBGB9721082.7A GB9721082D0 (en) 1997-10-03 1997-10-03 Integrated circuit
CA002299992A CA2299992A1 (en) 1997-10-03 2000-03-03 Integrated circuit

Publications (1)

Publication Number Publication Date
ES2206988T3 true ES2206988T3 (es) 2004-05-16

Family

ID=25681597

Family Applications (1)

Application Number Title Priority Date Filing Date
ES98945427T Expired - Lifetime ES2206988T3 (es) 1997-10-03 1998-10-02 Circuito integrado.

Country Status (8)

Country Link
US (1) US7091756B2 (enExample)
EP (1) EP1020031B1 (enExample)
JP (1) JP2001519615A (enExample)
DE (1) DE69818699T2 (enExample)
DK (1) DK1020031T3 (enExample)
ES (1) ES2206988T3 (enExample)
GB (1) GB9721082D0 (enExample)
WO (1) WO1999018668A2 (enExample)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE10250869B3 (de) * 2002-10-31 2004-04-29 Infineon Technologies Ag D-Flipflop mit reduzierter Transistoranzahl
KR20070029147A (ko) * 2004-03-11 2007-03-13 코닌클리즈케 필립스 일렉트로닉스 엔.브이. 주파수 분주기
US7453294B1 (en) * 2005-06-28 2008-11-18 Altera Corporation Dynamic frequency divider with improved leakage tolerance
US8779810B2 (en) 2011-07-15 2014-07-15 Qualcomm Incorporated Dynamic divide by 2 with 25% duty cycle output waveforms
WO2013096886A1 (en) * 2011-12-22 2013-06-27 Arrayed Fiberoptics Corporation Non-contact optical fiber connector component
TWI500266B (zh) * 2013-09-04 2015-09-11 Ind Tech Res Inst 栓鎖器與其操作方法與比較器
US20160079985A1 (en) * 2014-09-16 2016-03-17 Qualcomm Incorporated Quadrature local oscillator phase synthesis and architecture for divide-by-odd-number frequency dividers
KR102487109B1 (ko) * 2015-12-15 2023-01-09 엘지디스플레이 주식회사 게이트 구동회로 및 이를 포함하는 표시 장치
US10209735B1 (en) * 2018-05-24 2019-02-19 Realtek Semiconductor Corp. High-speed quadrature clock generator and method thereof

Family Cites Families (21)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4193539A (en) * 1977-11-07 1980-03-18 Ncr Corporation Signal generator
US4356411A (en) * 1978-12-12 1982-10-26 Tokyo Shibaura Denki Kabushiki Kaisha Flip-flop circuit
JPS57103434A (en) * 1980-12-17 1982-06-28 Matsushita Electric Ind Co Ltd Frequency dividing circuit
JPS60224319A (ja) * 1984-04-20 1985-11-08 Seiko Epson Corp フリツプ・フロツプ回路
JPS61294932A (ja) * 1985-06-21 1986-12-25 Mitsubishi Electric Corp 半導体装置およびデ−タ伝送路
GB2198603A (en) * 1986-12-05 1988-06-15 Philips Electronic Associated Divider circuit
US5020082A (en) * 1988-06-15 1991-05-28 Seiko Epson Corporation Asynchronous counter
US5036217A (en) * 1989-06-02 1991-07-30 Motorola, Inc. High-speed low-power flip-flop
JPH03121620A (ja) * 1989-10-04 1991-05-23 Nec Corp スタティック型分周器
FR2653277A1 (fr) * 1989-10-17 1991-04-19 Thomson Composants Microondes Circuit integre logique, a temps de basculement reglable.
JP2853894B2 (ja) * 1990-08-24 1999-02-03 三菱電機株式会社 分周回路及びパルス信号作成回路
US5341031A (en) * 1990-08-27 1994-08-23 Mitsubishi Denki Kabushiki Kaisha Stable high speed clock generator
FR2666706B1 (fr) * 1990-09-12 1993-08-06 Sgs Thomson Microelectronics Compteur/divisdeur rapide et application a un compteur avaleur.
US5049760A (en) * 1990-11-06 1991-09-17 Motorola, Inc. High speed complementary flipflop
JP2871087B2 (ja) * 1990-11-30 1999-03-17 日本電気株式会社 フリップフロップ回路
JPH04245713A (ja) * 1991-01-30 1992-09-02 Nec Corp フリップフロップ回路
JP3349170B2 (ja) 1992-06-15 2002-11-20 日本電信電話株式会社 Cmos可変分周回路
US5465060A (en) * 1994-06-10 1995-11-07 International Business Machines Corporation Fast edge triggered self-resetting CMOS receiver with parallel L1/L2 (Master/Slave) latch
DE69532377D1 (de) * 1995-10-12 2004-02-05 St Microelectronics Srl Implementierung einer Flip-Flop-Schaltung niedrigen Verbrauchs und hoher Packungsdichte, insbesondere für Standardzellen-Bibliotheken
JPH09232920A (ja) * 1996-02-28 1997-09-05 Nec Ic Microcomput Syst Ltd フリップフロップ回路
US6507228B2 (en) * 2001-05-03 2003-01-14 International Business Machines Corporation Method and apparatus for latching a clocked data signal

Also Published As

Publication number Publication date
DK1020031T3 (da) 2004-01-26
WO1999018668A2 (en) 1999-04-15
US20030006812A1 (en) 2003-01-09
GB9721082D0 (en) 1997-12-03
EP1020031B1 (en) 2003-10-01
DE69818699T2 (de) 2004-04-22
DE69818699D1 (de) 2003-11-06
EP1020031A2 (en) 2000-07-19
JP2001519615A (ja) 2001-10-23
WO1999018668A3 (en) 1999-06-24
US7091756B2 (en) 2006-08-15

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