ES2195873T3 - Aparato de interconexion con conduccion de ondas dinamicas y metodos asociados. - Google Patents
Aparato de interconexion con conduccion de ondas dinamicas y metodos asociados.Info
- Publication number
- ES2195873T3 ES2195873T3 ES00907775T ES00907775T ES2195873T3 ES 2195873 T3 ES2195873 T3 ES 2195873T3 ES 00907775 T ES00907775 T ES 00907775T ES 00907775 T ES00907775 T ES 00907775T ES 2195873 T3 ES2195873 T3 ES 2195873T3
- Authority
- ES
- Spain
- Prior art keywords
- operable
- delay
- values
- preselectable
- data signals
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired - Lifetime
Links
- 230000004048 modification Effects 0.000 abstract 1
- 238000012986 modification Methods 0.000 abstract 1
Classifications
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
-
- G—PHYSICS
- G06—COMPUTING; CALCULATING OR COUNTING
- G06F—ELECTRIC DIGITAL DATA PROCESSING
- G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
- G06F13/38—Information transfer, e.g. on bus
- G06F13/42—Bus transfer protocol, e.g. handshake; Synchronisation
- G06F13/4204—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus
- G06F13/4208—Bus transfer protocol, e.g. handshake; Synchronisation on a parallel bus being a system bus, e.g. VME bus, Futurebus, Multibus
-
- H—ELECTRICITY
- H04—ELECTRIC COMMUNICATION TECHNIQUE
- H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
- H04L7/00—Arrangements for synchronising receiver with transmitter
- H04L7/04—Speed or phase control by synchronisation signals
Landscapes
- Engineering & Computer Science (AREA)
- Theoretical Computer Science (AREA)
- General Engineering & Computer Science (AREA)
- General Physics & Mathematics (AREA)
- Physics & Mathematics (AREA)
- Information Transfer Systems (AREA)
- Synchronisation In Digital Transmission Systems (AREA)
- Measuring Volume Flow (AREA)
- Hydrogenated Pyridines (AREA)
- Pipeline Systems (AREA)
- Investigating Or Analyzing Materials By The Use Of Ultrasonic Waves (AREA)
- Ultra Sonic Daignosis Equipment (AREA)
- Surface Acoustic Wave Elements And Circuit Networks Thereof (AREA)
- Pulse Circuits (AREA)
- Selective Calling Equipment (AREA)
- Communication Control (AREA)
- Complex Calculations (AREA)
- Rigid Pipes And Flexible Pipes (AREA)
- Medicines Containing Antibodies Or Antigens For Use As Internal Diagnostic Agents (AREA)
- Supports For Pipes And Cables (AREA)
Abstract
Un aparato de interfaz (200) que comprende: una pluralidad de dispositivos de retraso (406, 408, 410) siendo cada dispositivo operable para la recepción de una señal de datos correspondiente, teniendo cada dispositivo de retraso un tiempo de retraso preseleccionable, y generando una señal de datos tras el tiempo de retraso preseleccionado, caracterizado por: circuitería (418, 440, 442) acoplada a la mencionada pluralidad de dispositivos de retraso operables en la fijación de cada tiempo de retraso preseleccionable, fijándose esos tiempos de retraso preseleccionables en respuesta a un tiempo de llegada de la mencionada señal correspondiente de datos, en donde dicha circuitería operable para la fijación de cada tiempo de retraso preseleccionable comprende: una lógica de comparación de datos (424) operable para la recepción de un subgrupo predeterminado de señales de datos, y generando un primer valor de señal de salida predeterminado cuando dicho subgrupo de señales de datos comprende un primer grupo predeterminado de valores, y genera un segundo valor de señal de salida predeterminado cuando dicho subgrupo de señales de datos tiene un segundo grupo de valores predeterminado, en donde dicho subgrupo de señales de datos asume uno de los mencionados primer y segundo grupo predeterminado de valores en respuesta a los mencionados tiempos de llegada asociados; y una circuitería operable para la modificación de los mencionados tiempos de retraso preseleccionados en respuesta a los indicados primeros y segundos valores predeterminados de señal de salida.
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
US09/263,662 US6654897B1 (en) | 1999-03-05 | 1999-03-05 | Dynamic wave-pipelined interface apparatus and methods therefor |
Publications (1)
Publication Number | Publication Date |
---|---|
ES2195873T3 true ES2195873T3 (es) | 2003-12-16 |
Family
ID=23002734
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
ES00907775T Expired - Lifetime ES2195873T3 (es) | 1999-03-05 | 2000-03-03 | Aparato de interconexion con conduccion de ondas dinamicas y metodos asociados. |
Country Status (18)
Country | Link |
---|---|
US (1) | US6654897B1 (es) |
EP (1) | EP1159687B1 (es) |
JP (1) | JP3725429B2 (es) |
KR (1) | KR100487206B1 (es) |
CN (1) | CN1181440C (es) |
AT (1) | ATE239944T1 (es) |
AU (1) | AU2925200A (es) |
BR (1) | BR0009251B1 (es) |
CA (1) | CA2365288C (es) |
CZ (1) | CZ20013179A3 (es) |
DE (1) | DE60002567T2 (es) |
ES (1) | ES2195873T3 (es) |
HU (1) | HUP0105099A3 (es) |
IL (2) | IL144674A0 (es) |
PL (1) | PL202169B1 (es) |
RU (1) | RU2213992C2 (es) |
TW (1) | TW459179B (es) |
WO (1) | WO2000054164A1 (es) |
Families Citing this family (32)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
US6950957B1 (en) * | 2000-09-11 | 2005-09-27 | Adc Telecommunications, Inc. | Phase comparator for a phase locked loop |
US6928571B1 (en) | 2000-09-15 | 2005-08-09 | Intel Corporation | Digital system of adjusting delays on circuit boards |
US6920552B2 (en) * | 2001-03-16 | 2005-07-19 | Broadcom Corporation | Network interface with double data rate and delay locked loop |
US6675272B2 (en) | 2001-04-24 | 2004-01-06 | Rambus Inc. | Method and apparatus for coordinating memory operations among diversely-located memory components |
US8391039B2 (en) | 2001-04-24 | 2013-03-05 | Rambus Inc. | Memory module with termination component |
DE60220863T2 (de) * | 2001-04-24 | 2008-03-13 | Rambus Inc., Los Altos | Verfahren und Gerät zum Koordinieren von Speicheroperationen zwischen unterschiedlich angeordneten Speicherkomponenten |
US7076678B2 (en) * | 2002-02-11 | 2006-07-11 | Micron Technology, Inc. | Method and apparatus for data transfer |
US6954870B2 (en) * | 2002-03-12 | 2005-10-11 | International Business Machines Corporation | Method for receiver delay detection and latency minimization for a source synchronous wave pipelined interface |
US6934867B2 (en) * | 2002-05-17 | 2005-08-23 | International Business Machines Corporation | Digital system having a multiplicity of self-calibrating interfaces |
ATE459053T1 (de) * | 2002-07-17 | 2010-03-15 | Chronologic Pty Ltd | Synchronisierter multikanal-usb |
DE102004013929B3 (de) * | 2004-03-22 | 2005-08-11 | Infineon Technologies Ag | Verfahren zum Steuern des Einlesens eines Datensignals sowie eine Eingangsschaltung für eine elektronische Schaltung |
US7301831B2 (en) | 2004-09-15 | 2007-11-27 | Rambus Inc. | Memory systems with variable delays for write data signals |
KR20060081522A (ko) * | 2005-01-10 | 2006-07-13 | 삼성전자주식회사 | 피씨아이 익스프레스의 바이트 스큐 보상방법 및 이를위한 피씨아이 익스프레스 물리 계층 수신기 |
US20060164909A1 (en) * | 2005-01-24 | 2006-07-27 | International Business Machines Corporation | System, method and storage medium for providing programmable delay chains for a memory system |
US7412618B2 (en) * | 2005-02-11 | 2008-08-12 | International Business Machines Corporation | Combined alignment scrambler function for elastic interface |
US7461287B2 (en) * | 2005-02-11 | 2008-12-02 | International Business Machines Corporation | Elastic interface de-skew mechanism |
US20060242473A1 (en) * | 2005-04-07 | 2006-10-26 | Wahl Mark A | Phase optimization for data communication between plesiochronous time domains |
US8037370B2 (en) | 2007-05-02 | 2011-10-11 | Ati Technologies Ulc | Data transmission apparatus with information skew and redundant control information and method |
TW200939033A (en) * | 2008-01-07 | 2009-09-16 | Nikon Systems Inc | Data transfer device and camera |
WO2009147697A1 (ja) * | 2008-06-03 | 2009-12-10 | 富士通株式会社 | 情報処理装置及びその制御方法 |
JP2010028450A (ja) * | 2008-07-18 | 2010-02-04 | Nikon Corp | データ転送装置および電子カメラ |
JP5341503B2 (ja) | 2008-12-26 | 2013-11-13 | 株式会社東芝 | メモリデバイス、ホストデバイスおよびサンプリングクロックの調整方法 |
JP5304280B2 (ja) * | 2009-01-30 | 2013-10-02 | 株式会社ニコン | 位相調整装置およびカメラ |
CN101493304B (zh) * | 2009-03-06 | 2012-10-03 | 北京铱钵隆芯科技有限责任公司 | 可编程延时装置及其控制流程 |
CN101996149B (zh) * | 2009-08-12 | 2012-09-26 | 炬力集成电路设计有限公司 | 一种数据采集方法及装置 |
USD675498S1 (en) | 2010-06-18 | 2013-02-05 | Master Lock Company Llc | Ratchet |
WO2012147258A1 (ja) | 2011-04-25 | 2012-11-01 | パナソニック株式会社 | チャネル間スキュー調整回路 |
TW201246881A (en) * | 2011-05-12 | 2012-11-16 | Novatek Microelectronics Corp | Signal calibration method and client circuit and transmission system using the same |
CN102780552A (zh) * | 2011-05-13 | 2012-11-14 | 联咏科技股份有限公司 | 信号校正方法及相关的客户端电路及传输系统 |
TWI460574B (zh) * | 2011-05-19 | 2014-11-11 | Novatek Microelectronics Corp | 校正行動產業處理器介面中訊號偏移的方法及相關傳輸系統 |
USD681411S1 (en) | 2011-08-30 | 2013-05-07 | Master Lock Company Llc | Ratchet lock |
JP7217204B2 (ja) * | 2019-06-28 | 2023-02-02 | 株式会社アドバンテスト | 信号処理装置および信号処理方法 |
Family Cites Families (26)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
NZ220548A (en) * | 1986-06-18 | 1990-05-28 | Fujitsu Ltd | Tdm frame synchronising circuit |
US4922141A (en) * | 1986-10-07 | 1990-05-01 | Western Digital Corporation | Phase-locked loop delay line |
US5086500A (en) * | 1987-08-07 | 1992-02-04 | Tektronix, Inc. | Synchronized system by adjusting independently clock signals arriving at a plurality of integrated circuits |
JPH0683172B2 (ja) * | 1988-09-27 | 1994-10-19 | 日本電気株式会社 | フレームアライメント方式 |
US4965884A (en) * | 1989-11-22 | 1990-10-23 | Northern Telecom Limited | Data alignment method and apparatus |
US5258660A (en) | 1990-01-16 | 1993-11-02 | Cray Research, Inc. | Skew-compensated clock distribution system |
US5229668A (en) * | 1992-03-25 | 1993-07-20 | North Carolina State University Of Raleigh | Method and apparatus for high speed digital sampling of a data signal |
CA2151456C (en) * | 1992-12-09 | 2004-03-02 | John S. Hendricks | Reprogrammable terminal for suggesting programs offered on a television program delivery system |
US5467464A (en) * | 1993-03-09 | 1995-11-14 | Apple Computer, Inc. | Adaptive clock skew and duty cycle compensation for a serial data bus |
JPH0764957A (ja) * | 1993-08-23 | 1995-03-10 | Mitsubishi Electric Corp | タイマ装置 |
JPH07154381A (ja) * | 1993-11-30 | 1995-06-16 | Hitachi Ltd | データ転送装置 |
US5442636A (en) * | 1993-12-14 | 1995-08-15 | At&T Corp. | Circuit and method for alignment of digital information packets |
JPH07311735A (ja) | 1994-05-18 | 1995-11-28 | Hitachi Ltd | データ転送装置 |
US6032282A (en) * | 1994-09-19 | 2000-02-29 | Advantest Corp. | Timing edge forming circuit for IC test system |
JP3233801B2 (ja) * | 1994-12-09 | 2001-12-04 | 沖電気工業株式会社 | ビット位相同期回路 |
US5507029A (en) * | 1995-01-11 | 1996-04-09 | International Business Machines Corporation | Method for minimizing the time skew of electrical signals in very large scale integrated circuits |
US6167528A (en) * | 1995-12-21 | 2000-12-26 | Cypress Semiconductor | Programmably timed storage element for integrated circuit input/output |
US5872959A (en) * | 1996-09-10 | 1999-02-16 | Lsi Logic Corporation | Method and apparatus for parallel high speed data transfer |
US5838936A (en) | 1997-03-10 | 1998-11-17 | Emulex Corporation | Elastic bus interface data buffer |
US6247138B1 (en) * | 1997-06-12 | 2001-06-12 | Fujitsu Limited | Timing signal generating circuit, semiconductor integrated circuit device and semiconductor integrated circuit system to which the timing signal generating circuit is applied, and signal transmission system |
US6229367B1 (en) * | 1997-06-26 | 2001-05-08 | Vitesse Semiconductor Corp. | Method and apparatus for generating a time delayed signal with a minimum data dependency error using an oscillator |
US6031847A (en) * | 1997-07-01 | 2000-02-29 | Silicon Graphics, Inc | Method and system for deskewing parallel bus channels |
WO1999012316A2 (en) * | 1997-09-04 | 1999-03-11 | Silicon Image, Inc. | Controllable delays in multiple synchronized signals for reduced electromagnetic interference at peak frequencies |
JPH11145945A (ja) * | 1997-11-12 | 1999-05-28 | Fujitsu Ltd | 符号化フレーム同期方法及び符号化フレーム同期回路 |
US6269451B1 (en) * | 1998-02-27 | 2001-07-31 | Micron Technology, Inc. | Method and apparatus for adjusting data timing by delaying clock signal |
US6289468B1 (en) * | 1998-11-06 | 2001-09-11 | Advanced Micro Devices, Inc. | Technique for controlling system bus timing with on-chip programmable delay lines |
-
1999
- 1999-03-05 US US09/263,662 patent/US6654897B1/en not_active Expired - Lifetime
-
2000
- 2000-02-29 TW TW089103445A patent/TW459179B/zh not_active IP Right Cessation
- 2000-03-03 IL IL14467400A patent/IL144674A0/xx active IP Right Grant
- 2000-03-03 RU RU2001126557/09A patent/RU2213992C2/ru not_active IP Right Cessation
- 2000-03-03 EP EP00907775A patent/EP1159687B1/en not_active Expired - Lifetime
- 2000-03-03 ES ES00907775T patent/ES2195873T3/es not_active Expired - Lifetime
- 2000-03-03 WO PCT/GB2000/000756 patent/WO2000054164A1/en active IP Right Grant
- 2000-03-03 KR KR10-2001-7011113A patent/KR100487206B1/ko not_active IP Right Cessation
- 2000-03-03 HU HU0105099A patent/HUP0105099A3/hu unknown
- 2000-03-03 AU AU29252/00A patent/AU2925200A/en not_active Abandoned
- 2000-03-03 DE DE60002567T patent/DE60002567T2/de not_active Expired - Lifetime
- 2000-03-03 AT AT00907775T patent/ATE239944T1/de not_active IP Right Cessation
- 2000-03-03 CN CNB008046468A patent/CN1181440C/zh not_active Expired - Lifetime
- 2000-03-03 CZ CZ20013179A patent/CZ20013179A3/cs unknown
- 2000-03-03 JP JP2000604321A patent/JP3725429B2/ja not_active Expired - Lifetime
- 2000-03-03 BR BRPI0009251-7A patent/BR0009251B1/pt not_active IP Right Cessation
- 2000-03-03 PL PL350160A patent/PL202169B1/pl not_active IP Right Cessation
- 2000-03-03 CA CA002365288A patent/CA2365288C/en not_active Expired - Lifetime
-
2001
- 2001-07-31 IL IL144674A patent/IL144674A/en not_active IP Right Cessation
Also Published As
Publication number | Publication date |
---|---|
KR100487206B1 (ko) | 2005-05-03 |
KR20010102462A (ko) | 2001-11-15 |
TW459179B (en) | 2001-10-11 |
US6654897B1 (en) | 2003-11-25 |
EP1159687B1 (en) | 2003-05-07 |
CN1181440C (zh) | 2004-12-22 |
PL350160A1 (en) | 2002-11-18 |
PL202169B1 (pl) | 2009-06-30 |
CN1342289A (zh) | 2002-03-27 |
ATE239944T1 (de) | 2003-05-15 |
BR0009251A (pt) | 2001-11-20 |
HUP0105099A2 (hu) | 2002-04-29 |
DE60002567D1 (de) | 2003-06-12 |
JP3725429B2 (ja) | 2005-12-14 |
IL144674A (en) | 2006-04-10 |
CA2365288A1 (en) | 2000-09-14 |
RU2213992C2 (ru) | 2003-10-10 |
DE60002567T2 (de) | 2004-03-25 |
IL144674A0 (en) | 2002-05-23 |
AU2925200A (en) | 2000-09-28 |
BR0009251B1 (pt) | 2013-02-19 |
JP2002539526A (ja) | 2002-11-19 |
CA2365288C (en) | 2009-05-05 |
CZ20013179A3 (cs) | 2002-02-13 |
HUP0105099A3 (en) | 2005-01-28 |
WO2000054164A1 (en) | 2000-09-14 |
EP1159687A1 (en) | 2001-12-05 |
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