ATE367637T1 - Schneller signalweg und verfahren - Google Patents

Schneller signalweg und verfahren

Info

Publication number
ATE367637T1
ATE367637T1 AT02706147T AT02706147T ATE367637T1 AT E367637 T1 ATE367637 T1 AT E367637T1 AT 02706147 T AT02706147 T AT 02706147T AT 02706147 T AT02706147 T AT 02706147T AT E367637 T1 ATE367637 T1 AT E367637T1
Authority
AT
Austria
Prior art keywords
inverters
digital signal
transition
procedure
signal path
Prior art date
Application number
AT02706147T
Other languages
English (en)
Inventor
Greg Blodgett
Original Assignee
Micron Technology Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Micron Technology Inc filed Critical Micron Technology Inc
Application granted granted Critical
Publication of ATE367637T1 publication Critical patent/ATE367637T1/de

Links

Classifications

    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C8/00Arrangements for selecting an address in a digital store
    • G11C8/18Address timing or clocking circuits; Address control signal generation or management, e.g. for row address strobe [RAS] or column address strobe [CAS] signals
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C5/00Details of stores covered by group G11C11/00
    • G11C5/06Arrangements for interconnecting storage elements electrically, e.g. by wiring
    • G11C5/063Voltage and signal distribution in integrated semi-conductor memory access lines, e.g. word-line, bit-line, cross-over resistance, propagation delay
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/10Input/output [I/O] data interface arrangements, e.g. I/O data control circuits, I/O data buffers
    • GPHYSICS
    • G11INFORMATION STORAGE
    • G11CSTATIC STORES
    • G11C7/00Arrangements for writing information into, or reading information out from, a digital store
    • G11C7/22Read-write [R-W] timing or clocking circuits; Read-write [R-W] control signal generators or management 

Landscapes

  • Microelectronics & Electronic Packaging (AREA)
  • Engineering & Computer Science (AREA)
  • Dram (AREA)
  • Static Random-Access Memory (AREA)
  • Logic Circuits (AREA)
  • Semiconductor Integrated Circuits (AREA)
  • Electronic Switches (AREA)
  • Stabilization Of Oscillater, Synchronisation, Frequency Synthesizers (AREA)
  • Burglar Alarm Systems (AREA)
  • Radar Systems Or Details Thereof (AREA)
  • Reduction Or Emphasis Of Bandwidth Of Signals (AREA)
  • Stereo-Broadcasting Methods (AREA)
  • Communication Control (AREA)
AT02706147T 2001-02-05 2002-02-04 Schneller signalweg und verfahren ATE367637T1 (de)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US09/777,835 US6552953B2 (en) 2001-02-05 2001-02-05 High speed signal path and method

Publications (1)

Publication Number Publication Date
ATE367637T1 true ATE367637T1 (de) 2007-08-15

Family

ID=25111450

Family Applications (1)

Application Number Title Priority Date Filing Date
AT02706147T ATE367637T1 (de) 2001-02-05 2002-02-04 Schneller signalweg und verfahren

Country Status (8)

Country Link
US (1) US6552953B2 (de)
EP (1) EP1366495B1 (de)
JP (1) JP4247520B2 (de)
KR (1) KR100854937B1 (de)
CN (1) CN100347784C (de)
AT (1) ATE367637T1 (de)
DE (1) DE60221230T2 (de)
WO (1) WO2002063629A1 (de)

Families Citing this family (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US6535038B2 (en) 2001-03-09 2003-03-18 Micron Technology, Inc. Reduced jitter clock generator circuit and method for applying properly phased clock signals to clocked devices
JP2002313079A (ja) * 2001-04-18 2002-10-25 Seiko Epson Corp 半導体メモリ装置の電源ノイズの抑制化
US6628139B2 (en) * 2001-08-03 2003-09-30 Micron Technology, Inc. Digital logic devices with extremely skewed trip points and reset circuitry for rapidly propagating signal edges
US6738301B2 (en) 2002-08-29 2004-05-18 Micron Technology, Inc. Method and system for accelerating coupling of digital signals
US6847582B2 (en) * 2003-03-11 2005-01-25 Micron Technology, Inc. Low skew clock input buffer and method
US20130076424A1 (en) 2011-09-23 2013-03-28 Qualcomm Incorporated System and method for reducing cross coupling effects
US10283187B2 (en) * 2017-07-19 2019-05-07 Micron Technology, Inc. Apparatuses and methods for providing additional drive to multilevel signals representing data
JP6974549B1 (ja) * 2020-07-17 2021-12-01 華邦電子股▲ふん▼有限公司Winbond Electronics Corp. メモリ装置およびその入出力バッファ制御方法
JP2024048776A (ja) * 2022-09-28 2024-04-09 ラピステクノロジー株式会社 データ受信回路、表示ドライバ及び表示装置

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US4985643A (en) * 1988-06-24 1991-01-15 National Semiconductor Corporation Speed enhancement technique for CMOS circuits
US5519344A (en) * 1994-06-30 1996-05-21 Proebsting; Robert J. Fast propagation technique in CMOS integrated circuits
US5929680A (en) * 1997-05-16 1999-07-27 Tritech Microelectronics International Ltd Short circuit reduced CMOS buffer circuit
US5999481A (en) * 1997-08-22 1999-12-07 Micron Technology, Inc. Method and apparatus for controlling the operation of an integrated circuit responsive to out-of-synchronism control signals
US6137849A (en) 1998-09-09 2000-10-24 Agilent Technologies System and method for communicating data over a high-speed bus
US6331793B1 (en) 1999-12-30 2001-12-18 Intel Corporation Apparatus, method and system for pulse passgate topologies

Also Published As

Publication number Publication date
JP4247520B2 (ja) 2009-04-02
CN1491416A (zh) 2004-04-21
CN100347784C (zh) 2007-11-07
KR100854937B1 (ko) 2008-08-29
KR20030077607A (ko) 2003-10-01
JP2004526351A (ja) 2004-08-26
US20020122346A1 (en) 2002-09-05
EP1366495B1 (de) 2007-07-18
EP1366495A4 (de) 2006-03-22
WO2002063629A1 (en) 2002-08-15
EP1366495A1 (de) 2003-12-03
DE60221230T2 (de) 2008-04-17
DE60221230D1 (de) 2007-08-30
US6552953B2 (en) 2003-04-22

Similar Documents

Publication Publication Date Title
DE60221230D1 (de) Schneller signalweg und verfahren
SE9301546L (sv) Maximalsoekningskrets
WO2008064028A3 (en) High speed serializer apparatus
TW200619936A (en) An apparatus and method for an address generation circuit
DE50202577D1 (de) Verhindern der unerwuenschten externen erfassung von operationen in integrierten digitalschaltungen
WO2005013044A3 (en) Clock generator with skew control
EP3627706A3 (de) Schaltkreis und verfahren zur frequenzdetektion
TW200619901A (en) A high-security semiconductor device
TW200703356A (en) Data output device and method of semiconductor device
TW200740121A (en) Clock-pulse generator and shift register
ES2038075B1 (es) "aparato divisor de frecuencia programable"
ATE541361T1 (de) Schneller programmierbarer frequenzteiler mit synchroner ladung
CA2210211A1 (en) Method of and apparatus for generating a pseudorandom noise sequence
KR950015061A (ko) 동기식 이진 카운터
SE9804605L (sv) Dataskivare
US20150270839A1 (en) Identification Circuit
EP1732226A3 (de) P-Domino Datenregister
KR960026760A (ko) 펄스 신호 정형회로
TW200642276A (en) Fan out buffer and method therefor
WO2003005584A3 (en) Random generator description
JPS6382014A (ja) 擬似ランダム雑音符号発生回路
JPS6070840A (ja) 同期パタ−ン
AU2003300274A8 (en) Apparatus and method for safely handling asynchronous shutdown of pulsewidth modulated output
KR970068163A (ko) 반도체 메모리 소자의 데이터 출력 버퍼
KR100601591B1 (ko) 이븐/오드 플립플롭들을 이용한 고속 카운터 회로

Legal Events

Date Code Title Description
RER Ceased as to paragraph 5 lit. 3 law introducing patent treaties