ES2105301T3 - Metodo de fabricar una placa de circuito impreso de multiples capas. - Google Patents

Metodo de fabricar una placa de circuito impreso de multiples capas.

Info

Publication number
ES2105301T3
ES2105301T3 ES93917736T ES93917736T ES2105301T3 ES 2105301 T3 ES2105301 T3 ES 2105301T3 ES 93917736 T ES93917736 T ES 93917736T ES 93917736 T ES93917736 T ES 93917736T ES 2105301 T3 ES2105301 T3 ES 2105301T3
Authority
ES
Spain
Prior art keywords
substrate
traces
basic
manufacturing
layer printed
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Lifetime
Application number
ES93917736T
Other languages
English (en)
Inventor
Erik Middelman
Pieter Hendrik Zuuring
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Amp Akzo Linlim VOF
Original Assignee
Amp Akzo Linlim VOF
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Amp Akzo Linlim VOF filed Critical Amp Akzo Linlim VOF
Application granted granted Critical
Publication of ES2105301T3 publication Critical patent/ES2105301T3/es
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • B—PERFORMING OPERATIONS; TRANSPORTING
    • B32—LAYERED PRODUCTS
    • B32B—LAYERED PRODUCTS, i.e. PRODUCTS BUILT-UP OF STRATA OF FLAT OR NON-FLAT, e.g. CELLULAR OR HONEYCOMB, FORM
    • B32B37/00—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding
    • B32B37/12—Methods or apparatus for laminating, e.g. by curing or by ultrasonic bonding characterised by using adhesives
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/02—Details
    • H05K1/03—Use of materials for the substrate
    • H05K1/0313—Organic insulating material
    • H05K1/0353—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement
    • H05K1/0366—Organic insulating material consisting of two or more materials, e.g. two or more polymers, polymer + filler, + reinforcement reinforced, e.g. by fibres, fabrics
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/46—Manufacturing multilayer circuits
    • H05K3/4611—Manufacturing multilayer circuits by laminating two or more circuit boards
    • H05K3/4626—Manufacturing multilayer circuits by laminating two or more circuit boards characterised by the insulating layers or materials
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/01—Dielectrics
    • H05K2201/0183—Dielectric layers
    • H05K2201/0195—Dielectric or adhesive layers comprising a plurality of layers, e.g. in a multilayer structure
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K2201/00—Indexing scheme relating to printed circuits covered by H05K1/00
    • H05K2201/02—Fillers; Particles; Fibers; Reinforcement materials
    • H05K2201/0275—Fibers and reinforcement materials
    • H05K2201/0287—Unidirectional or parallel fibers
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/38—Improvement of the adhesion between the insulating substrate and the metal
    • H05K3/386—Improvement of the adhesion between the insulating substrate and the metal by the use of an organic polymeric bonding layer, e.g. adhesive

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Manufacturing & Machinery (AREA)
  • Production Of Multi-Layered Print Wiring Board (AREA)
  • Laminated Bodies (AREA)

Abstract

SE PRESENTA UN PROCESO PARA MANUFACTURAR UNA TARJETA DE CABLEADO, IMPRESA, MULTICAPA, TAMBIEN LLAMADA UNA MULTICAPA, QUE COMPRENDE AL MENOS DOS SUBSTRATOS ELECTRICAMENTE AISLANTES CON TRAZAS O CAPAS CONDUCTORAS DISPUESTAS SOBRE AL MENOS TRES SUPERFICIES DE LAS MISMAS, EN DICHO PROCESO, POR MEDIO DE LA LAMINACION BAJO PRESION, UN SUBSTRATO BASICO ENDURECIDO BASADO EN UN MATERIAL SINTETICO REFORZADO CON UD, PROVISTO SOBRE AMBOS LADOS CON TRAZAS, SE COMBINA Y SE UNE CON UN SUBSTRATO TRASERO, EN DONDE DURANTE EL PROCESO DE LAMINACION EL SUBSTRATO TRASERO SE AÑADE AL SUBSTRATO BASICO, EL SUBSTRATO DE BASE Y EL SUBSTRATO TRASERO COMPRENDEN UNA CAPA DE NUCLEO ENDURECIDA REFORZADA CON UD, EL SUBSTRATO DE BASE HA SIDO PROVISTO EN AL MENOS SOBRE EL LADO QUE MIRA HACIA EL SUBSTRATO TRASERO DE UNA CAPA DE ADHESIVO PLASTICAMENTE DEFORMABLE (FLUIBLE), Y LA PRESION QUE SE EJERCE SOBRE EL LAMINADO UNE DICHO SUBSTRATO TRASERO EN CONTACTO O PARCIALMENTE EN CONTACTO CON LAS TRAZAS CONDUCTORAS DEL SUBSTRATO BASICO, Y EL ESPACIO ENTRE ESTAS TRAZAS SE RELLENA CON EL MATERIAL ADHESIVO, UNIENDO DE ESTA FORMA EL SUBSTRATO BASICO Y EL SUBSTRATO TRASERO.
ES93917736T 1992-08-13 1993-08-03 Metodo de fabricar una placa de circuito impreso de multiples capas. Expired - Lifetime ES2105301T3 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
EP92202492 1992-08-13

Publications (1)

Publication Number Publication Date
ES2105301T3 true ES2105301T3 (es) 1997-10-16

Family

ID=8210849

Family Applications (1)

Application Number Title Priority Date Filing Date
ES93917736T Expired - Lifetime ES2105301T3 (es) 1992-08-13 1993-08-03 Metodo de fabricar una placa de circuito impreso de multiples capas.

Country Status (12)

Country Link
EP (1) EP0655183B1 (es)
JP (1) JP2650072B2 (es)
KR (1) KR950703270A (es)
AT (1) ATE155312T1 (es)
AU (1) AU683846B2 (es)
BR (1) BR9306894A (es)
CA (1) CA2142267A1 (es)
DE (1) DE69312073T2 (es)
ES (1) ES2105301T3 (es)
RU (1) RU2115274C1 (es)
TW (1) TW230864B (es)
WO (1) WO1994005140A1 (es)

Families Citing this family (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3849381B2 (ja) * 1999-12-20 2006-11-22 株式会社日立製作所 絶縁回路基板の製造方法
DE10117994A1 (de) * 2001-04-10 2002-10-24 Orga Kartensysteme Gmbh Trägerfolie für elektronische Bauelemente zur Einlaminierung in Chipkarten
FR2834180B1 (fr) * 2001-12-20 2004-03-12 Org Europeene De Rech Procede de fabrication d'un module multicouches a circuits imprimes a haute densite
US6703114B1 (en) * 2002-10-17 2004-03-09 Arlon Laminate structures, methods for production thereof and uses therefor
FR2924894B1 (fr) * 2007-12-10 2010-12-10 Eads Europ Aeronautic Defence Pieces en materiau composite electro-structural.
CN101911017A (zh) 2007-12-31 2010-12-08 数据逻辑移动公司 用于配置、更新和引导便携式数据读取器上的可替代操作系统的系统和方法
JP5125567B2 (ja) * 2008-02-07 2013-01-23 株式会社デンソー 多層回路基板
JP5956198B2 (ja) * 2012-03-05 2016-07-27 旭化成株式会社 集光型太陽電池用レンズ及び集光型太陽電池用レンズの製造方法

Family Cites Families (6)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US3756891A (en) * 1967-12-26 1973-09-04 Multilayer circuit board techniques
US4606787A (en) * 1982-03-04 1986-08-19 Etd Technology, Inc. Method and apparatus for manufacturing multi layer printed circuit boards
US4943334A (en) * 1986-09-15 1990-07-24 Compositech Ltd. Method for making reinforced plastic laminates for use in the production of circuit boards
JPH01283996A (ja) * 1988-05-11 1989-11-15 Mitsubishi Electric Corp 多層プリント配線板
JPH02237197A (ja) * 1989-03-10 1990-09-19 Hitachi Ltd 多層回路基板及びその製造方法並びにその用途
EP0478051B1 (en) * 1990-09-24 1995-03-15 AMP-Akzo LinLam VOF Method for the manufacture, in a continuous process, of substrates for printed wire boards, and printed wire boards so manufactured

Also Published As

Publication number Publication date
DE69312073D1 (de) 1997-08-14
DE69312073T2 (de) 1998-01-15
AU4706593A (en) 1994-03-15
EP0655183A1 (en) 1995-05-31
RU2115274C1 (ru) 1998-07-10
WO1994005140A1 (en) 1994-03-03
CA2142267A1 (en) 1994-03-03
KR950703270A (ko) 1995-08-23
RU95106822A (ru) 1996-11-27
JPH08500212A (ja) 1996-01-09
BR9306894A (pt) 1998-12-08
ATE155312T1 (de) 1997-07-15
AU683846B2 (en) 1997-11-27
EP0655183B1 (en) 1997-07-09
JP2650072B2 (ja) 1997-09-03
TW230864B (es) 1994-09-21

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