ES2028771T1 - Nvran con circuito nram y nv integrados. - Google Patents

Nvran con circuito nram y nv integrados.

Info

Publication number
ES2028771T1
ES2028771T1 ES199090909888T ES90909888T ES2028771T1 ES 2028771 T1 ES2028771 T1 ES 2028771T1 ES 199090909888 T ES199090909888 T ES 199090909888T ES 90909888 T ES90909888 T ES 90909888T ES 2028771 T1 ES2028771 T1 ES 2028771T1
Authority
ES
Spain
Prior art keywords
data
circuit
programmable
programmable devices
alternation
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
ES199090909888T
Other languages
English (en)
Inventor
Christian E. Herdt
Albert A. Weiner
David A. Kamp
Klaus J. Dimmler
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Agiga Tech Inc
Original Assignee
Agiga Tech Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Agiga Tech Inc filed Critical Agiga Tech Inc
Publication of ES2028771T1 publication Critical patent/ES2028771T1/es
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C14/00—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down
    • G11C14/0054—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell
    • G11C14/0063—Digital stores characterised by arrangements of cells having volatile and non-volatile storage properties for back-up when the power is down in which the volatile element is a SRAM cell and the nonvolatile element is an EEPROM element, e.g. a floating gate or MNOS transistor

Abstract

UNA CELULA DE MEMORIA DE ACCESO AL AZAR NO-VOLATIL (NVRAM) DE TAMAÑO CONDENSADO QUE EMPLEA UN PAR DE DISPOSITIVOS DE VOLTAGE DE UMBRAL PROGRAMABLE (40B, 42B), V.GR. TRANSISTORES DE PUERTA FLOTANTE O MNOS, SNOS, SONOS, EN EL QUE SE ESTABLECEN DISTINTOS NIVELES DE VOLTAGE DE UMBRAL DE ACUERDO CON LOS NIVELES DE SEÑAL DE DATOS EXISTENTES EN LOS NODULOS DE DATOS (DT, DC) DE UN CIRCUITO DE ALTERNANCIA (12), CUANDO LOS DATOS VOLATILES SE ALMACENAN EN LOS DISPOSITIVOS PROGRAMABLES. DURANTE LA LLAMADA DE LOS DATOS NO-VOLATILES ALMACENADOS A LOS NODOS DE DATOS DEL CIRCUITO DE ALTERNANCIA, LOS DISPOSITIVOS PROGRAMABLES (40B, 42B) CONDUCEN ACTIVAMENTE CORRIENTE A LOS NODOS DE DATOS (DT, DC) PARA AJUSTAR EL CIRCUITO DE ALTERNANCIA (12) EN EL MISMO ESTADO QUE EXISTIA CUANDO SE ALMACENARON LOS DATOS. LA CORRIENTE PARA EL CIRCUITO DE ALTERNANCIA SE SUMINISTRA INDEPENDIENTEMENTE DE LA CORRIENTE SUMINISTRADA A LOS DISPOSITIVOS PROGRAMABLES. UN SOLO CONDUCTOR DE POLISILICONA (28) FORMA PUERTAS DE TRANSISTORES (40C, 42C) QUE CONECTAN LOS DISPOSITIVOS PROGRAMABLES (40B, 42B) A LOS NODOS DE DATOS (DT, DC) Y LAS PUERTAS (20, 22) DE LOS TRANSISTORES DEL CIRCUITO DE ALTERNANCIA (16, 18). SE INTEGRA UN DISPOSITIVO DE CARGA (24, 26) PARA CADA NODO DE DATOS EN EL CONDUCTOR DE POLISILICONA UNICO (28). SE CONSIGUE UNA CAPACIDAD DE INHIBICION DE PROGRAMA DINAMICO EN CADA DISPOSITIVO PROGRAMABLE (40B, 42B) DURANTE LA OPERACION DE ALMACENAMIENTO APLICANDO UNA SERIE DE PULSOS DE SEÑAL DE PROGRAMACION.
ES199090909888T 1989-06-02 1990-06-01 Nvran con circuito nram y nv integrados. Pending ES2028771T1 (es)

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
US07/361,033 US5065362A (en) 1989-06-02 1989-06-02 Non-volatile ram with integrated compact static ram load configuration

Publications (1)

Publication Number Publication Date
ES2028771T1 true ES2028771T1 (es) 1992-07-16

Family

ID=23420384

Family Applications (1)

Application Number Title Priority Date Filing Date
ES199090909888T Pending ES2028771T1 (es) 1989-06-02 1990-06-01 Nvran con circuito nram y nv integrados.

Country Status (7)

Country Link
US (1) US5065362A (es)
EP (1) EP0474781A4 (es)
JP (1) JPH04505981A (es)
KR (1) KR0169738B1 (es)
AU (1) AU5859090A (es)
ES (1) ES2028771T1 (es)
WO (1) WO1990015414A1 (es)

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Also Published As

Publication number Publication date
EP0474781A4 (en) 1993-01-07
AU5859090A (en) 1991-01-07
JPH04505981A (ja) 1992-10-15
WO1990015414A1 (en) 1990-12-13
KR920701980A (ko) 1992-08-12
KR0169738B1 (ko) 1999-02-18
EP0474781A1 (en) 1992-03-18
US5065362A (en) 1991-11-12

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