EP3766097A4 - Planarisation pour processus de fabrication de boîtier de dispositif à semi-conducteur - Google Patents

Planarisation pour processus de fabrication de boîtier de dispositif à semi-conducteur Download PDF

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Publication number
EP3766097A4
EP3766097A4 EP19766870.0A EP19766870A EP3766097A4 EP 3766097 A4 EP3766097 A4 EP 3766097A4 EP 19766870 A EP19766870 A EP 19766870A EP 3766097 A4 EP3766097 A4 EP 3766097A4
Authority
EP
European Patent Office
Prior art keywords
planarization
semiconductor device
device package
fabrication processes
package fabrication
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP19766870.0A
Other languages
German (de)
English (en)
Other versions
EP3766097A1 (fr
Inventor
Han-Wen Chen
Steven Verhaverbeke
Roman Gouk
Kyuil CHO
Boyi FU
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Applied Materials Inc
Original Assignee
Applied Materials Inc
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Applied Materials Inc filed Critical Applied Materials Inc
Publication of EP3766097A1 publication Critical patent/EP3766097A1/fr
Publication of EP3766097A4 publication Critical patent/EP3766097A4/fr
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/561—Batch processing
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L21/00—Processes or apparatus adapted for the manufacture or treatment of semiconductor or solid state devices or of parts thereof
    • H01L21/02—Manufacture or treatment of semiconductor devices or of parts thereof
    • H01L21/04—Manufacture or treatment of semiconductor devices or of parts thereof the devices having potential barriers, e.g. a PN junction, depletion layer or carrier concentration layer
    • H01L21/50—Assembly of semiconductor devices using processes or apparatus not provided for in a single one of the subgroups H01L21/06 - H01L21/326, e.g. sealing of a cap to a base of a container
    • H01L21/56—Encapsulations, e.g. encapsulation layers, coatings
    • H01L21/565—Moulds
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/29—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the material, e.g. carbon
    • H01L23/293—Organic, e.g. plastic
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L23/00—Details of semiconductor or other solid state devices
    • H01L23/28—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection
    • H01L23/31—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape
    • H01L23/3107—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed
    • H01L23/3114—Encapsulations, e.g. encapsulating layers, coatings, e.g. for protection characterised by the arrangement or shape the device being completely enclosed the device being a chip scale package, e.g. CSP

Landscapes

  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • General Physics & Mathematics (AREA)
  • Computer Hardware Design (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
  • Exposure Of Semiconductors, Excluding Electron Or Ion Beam Exposure (AREA)
  • Formation Of Insulating Films (AREA)
  • Encapsulation Of And Coatings For Semiconductor Or Solid State Devices (AREA)
EP19766870.0A 2018-03-15 2019-02-15 Planarisation pour processus de fabrication de boîtier de dispositif à semi-conducteur Pending EP3766097A4 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
US201862643222P 2018-03-15 2018-03-15
PCT/US2019/018154 WO2019177742A1 (fr) 2018-03-15 2019-02-15 Planarisation pour processus de fabrication de boîtier de dispositif à semi-conducteur

Publications (2)

Publication Number Publication Date
EP3766097A1 EP3766097A1 (fr) 2021-01-20
EP3766097A4 true EP3766097A4 (fr) 2022-04-13

Family

ID=67908338

Family Applications (1)

Application Number Title Priority Date Filing Date
EP19766870.0A Pending EP3766097A4 (fr) 2018-03-15 2019-02-15 Planarisation pour processus de fabrication de boîtier de dispositif à semi-conducteur

Country Status (6)

Country Link
EP (1) EP3766097A4 (fr)
JP (1) JP7258906B2 (fr)
KR (1) KR102521991B1 (fr)
CN (1) CN111868920A (fr)
TW (1) TWI717690B (fr)
WO (1) WO2019177742A1 (fr)

Families Citing this family (15)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US11342256B2 (en) 2019-01-24 2022-05-24 Applied Materials, Inc. Method of fine redistribution interconnect formation for advanced packaging applications
IT201900006736A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di fabbricazione di package
IT201900006740A1 (it) 2019-05-10 2020-11-10 Applied Materials Inc Procedimenti di strutturazione di substrati
US11931855B2 (en) 2019-06-17 2024-03-19 Applied Materials, Inc. Planarization methods for packaging substrates
US11862546B2 (en) 2019-11-27 2024-01-02 Applied Materials, Inc. Package core assembly and fabrication methods
US11257790B2 (en) 2020-03-10 2022-02-22 Applied Materials, Inc. High connectivity device stacking
US11454884B2 (en) 2020-04-15 2022-09-27 Applied Materials, Inc. Fluoropolymer stamp fabrication method
US11400545B2 (en) 2020-05-11 2022-08-02 Applied Materials, Inc. Laser ablation for package fabrication
US11752519B2 (en) 2020-06-19 2023-09-12 Canon Kabushiki Kaisha Planarization method and photocurable composition
TWI751600B (zh) * 2020-07-03 2022-01-01 財團法人工業技術研究院 封裝結構
US11232951B1 (en) 2020-07-14 2022-01-25 Applied Materials, Inc. Method and apparatus for laser drilling blind vias
US11676832B2 (en) 2020-07-24 2023-06-13 Applied Materials, Inc. Laser ablation system for package fabrication
US11521937B2 (en) 2020-11-16 2022-12-06 Applied Materials, Inc. Package structures with built-in EMI shielding
US11404318B2 (en) 2020-11-20 2022-08-02 Applied Materials, Inc. Methods of forming through-silicon vias in substrates for advanced packaging
US11705365B2 (en) 2021-05-18 2023-07-18 Applied Materials, Inc. Methods of micro-via formation for advanced packaging

Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018229A1 (en) * 2000-02-28 2001-08-30 Nbc Corporation Semiconductor device and method for fabricating same
US20090179317A1 (en) * 2008-01-11 2009-07-16 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
US20090209052A1 (en) * 2006-08-22 2009-08-20 3D Plus Process for the collective fabrication of 3d electronic modules
JP2011032436A (ja) * 2009-08-05 2011-02-17 Nitto Denko Corp 電子部品封止用のシート状エポキシ樹脂組成物およびそれを用いた電子部品装置
US20110115125A1 (en) * 2009-11-13 2011-05-19 Freescale Semiconductor, Inc Method and apparatus for molding substrate
US20120126395A1 (en) * 2010-11-18 2012-05-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die
US20150357256A1 (en) * 2014-06-08 2015-12-10 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods of packaging semiconductor devices
US20160126286A1 (en) * 2012-05-30 2016-05-05 Olympus Corporation Method for producing image pickup apparatus and method for producing semiconductor apparatus
US20160148887A1 (en) * 2014-11-26 2016-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Device Package with Reduced Thickness and Method for Forming Same

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP3420590B2 (ja) * 1996-11-11 2003-06-23 触媒化成工業株式会社 基材の平坦化方法、被膜付基材および半導体装置の製造方法
US20060003600A1 (en) * 2004-06-30 2006-01-05 Barns Chris E Contact planarization for integrated circuit processing
US20070032083A1 (en) * 2005-08-05 2007-02-08 Hynix Semiconductor, Inc. Planarization method for manufacturing semiconductor device
JP2008114195A (ja) * 2006-11-08 2008-05-22 Tokyo Ohka Kogyo Co Ltd 平坦化塗布方法
EP2214204B1 (fr) * 2007-10-17 2013-10-02 Panasonic Corporation Structure de montage
US20120064720A1 (en) * 2010-09-10 2012-03-15 Taiwan Semiconductor Manufacturing Company, Ltd. Planarization control for semiconductor devices
US9349622B2 (en) * 2013-03-12 2016-05-24 Taiwan Semiconductor Manufacturing Company, Ltd. Method and apparatus for planarization of substrate coatings
WO2017203888A1 (fr) * 2016-05-26 2017-11-30 アピックヤマダ株式会社 Procédé d'alimentation en résine, dispositif d'alimentation en résine, dispositif de moulage de résine, procédé de durcissement de résine et procédé de moulage de résine

Patent Citations (9)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
US20010018229A1 (en) * 2000-02-28 2001-08-30 Nbc Corporation Semiconductor device and method for fabricating same
US20090209052A1 (en) * 2006-08-22 2009-08-20 3D Plus Process for the collective fabrication of 3d electronic modules
US20090179317A1 (en) * 2008-01-11 2009-07-16 Kabushiki Kaisha Toshiba Semiconductor device and method for manufacturing the same
JP2011032436A (ja) * 2009-08-05 2011-02-17 Nitto Denko Corp 電子部品封止用のシート状エポキシ樹脂組成物およびそれを用いた電子部品装置
US20110115125A1 (en) * 2009-11-13 2011-05-19 Freescale Semiconductor, Inc Method and apparatus for molding substrate
US20120126395A1 (en) * 2010-11-18 2012-05-24 Stats Chippac, Ltd. Semiconductor Device and Method of Forming Uniform Height Insulating Layer Over Interposer Frame as Standoff for Semiconductor Die
US20160126286A1 (en) * 2012-05-30 2016-05-05 Olympus Corporation Method for producing image pickup apparatus and method for producing semiconductor apparatus
US20150357256A1 (en) * 2014-06-08 2015-12-10 UTAC Headquarters Pte. Ltd. Semiconductor packages and methods of packaging semiconductor devices
US20160148887A1 (en) * 2014-11-26 2016-05-26 Taiwan Semiconductor Manufacturing Company, Ltd. Device Package with Reduced Thickness and Method for Forming Same

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2019177742A1 *

Also Published As

Publication number Publication date
CN111868920A (zh) 2020-10-30
TW201946162A (zh) 2019-12-01
KR20200120766A (ko) 2020-10-21
WO2019177742A1 (fr) 2019-09-19
KR102521991B1 (ko) 2023-04-13
TWI717690B (zh) 2021-02-01
EP3766097A1 (fr) 2021-01-20
JP2021517360A (ja) 2021-07-15
JP7258906B2 (ja) 2023-04-17

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