EP3711051A1 - Schéma de polarisation pour programmation de mots dans une mémoire non volatile et pour inhiber une réduction de perturbation - Google Patents

Schéma de polarisation pour programmation de mots dans une mémoire non volatile et pour inhiber une réduction de perturbation

Info

Publication number
EP3711051A1
EP3711051A1 EP18879309.5A EP18879309A EP3711051A1 EP 3711051 A1 EP3711051 A1 EP 3711051A1 EP 18879309 A EP18879309 A EP 18879309A EP 3711051 A1 EP3711051 A1 EP 3711051A1
Authority
EP
European Patent Office
Prior art keywords
memory
transistor
nvm
eeprom
array
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP18879309.5A
Other languages
German (de)
English (en)
Other versions
EP3711051A4 (fr
Inventor
Gary Menezes
Krishnaswamy Ramkumar
Ali Keshavarzi
Venkatraman Prabhakar
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Longitude Flash Memory Solutions Ltd
Original Assignee
Longitude Flash Memory Solutions Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Longitude Flash Memory Solutions Ltd filed Critical Longitude Flash Memory Solutions Ltd
Publication of EP3711051A1 publication Critical patent/EP3711051A1/fr
Publication of EP3711051A4 publication Critical patent/EP3711051A4/fr
Pending legal-status Critical Current

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    • H—ELECTRICITY
    • H10—SEMICONDUCTOR DEVICES; ELECTRIC SOLID-STATE DEVICES NOT OTHERWISE PROVIDED FOR
    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
    • H10B43/30—EEPROM devices comprising charge-trapping gate insulators characterised by the memory core region
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0408—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors
    • G11C16/0433—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells containing floating gate transistors comprising cells containing a single floating gate transistor and one or more separate select transistors
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0466—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells with charge storage in an insulating layer, e.g. metal-nitride-oxide-silicon [MNOS], silicon-oxide-nitride-oxide-silicon [SONOS]
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/04—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS
    • G11C16/0483—Erasable programmable read-only memories electrically programmable using variable threshold transistors, e.g. FAMOS comprising cells having several storage transistors connected in series
    • G—PHYSICS
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/107—Programming all cells in an array, sector or block to the same state prior to flash erasing
    • G—PHYSICS
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    • G11C16/00—Erasable programmable read-only memories
    • G11C16/02—Erasable programmable read-only memories electrically programmable
    • G11C16/06—Auxiliary circuits, e.g. for writing into memory
    • G11C16/10—Programming or data input circuits
    • G11C16/14—Circuits for erasing electrically, e.g. erase voltage switching circuits
    • G11C16/16—Circuits for erasing electrically, e.g. erase voltage switching circuits for erasing blocks, e.g. arrays, words, groups
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    • H10B—ELECTRONIC MEMORY DEVICES
    • H10B43/00—EEPROM devices comprising charge-trapping gate insulators
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    • G—PHYSICS
    • G11—INFORMATION STORAGE
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    • G11C16/00—Erasable programmable read-only memories
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Definitions

  • the present disclosure relates generally to non-volatile memory devices, and more particularly to biasing scheme for word/byte programming and methods to reduce inhibit disturb.
  • Non-volatile memories are widely used for storing data in computer systems, and typically include a memory array with a large number of memory cells arranged in rows and columns.
  • each of the memory cells may include at least a non-volatile element, such as charge trapping field-effect transistor (FET), floating gate transistor, that is programmed or erased by applying a voltage of the proper polarity, magnitude and duration between a control/memory gate and the substrate.
  • FET charge trapping field-effect transistor
  • a positive gate-to- substrate voltage causes electrons to tunnel from the channel to a charge-trapping dielectric layer raising a threshold voltage (V T ) of the transistor
  • a negative gate-to-channel voltage causes holes to tunnel from the channel to the charge-trapping dielectric layer lowering the threshold voltage
  • SOC ICs system-on-chip integrated circuits
  • CMOS complementary metal -oxide-silicon
  • SONOS has typically been adopted in a flash solution where a page (or row) may be the smallest block that is written to at a time.
  • EEPROM operation requires the capability to write to a smaller block (byte or word) at a time, and may adopt the floating gate memory technology. Due to their differences in structures and fabrication processes, flash memory (e.g. SONOS transistors) and EEPROM (e.g.
  • floating gate transistors memory may be disposed in separate portions on a single IC package or semiconductor die, or even in separate IC packages or dies in a system, and being operated individually.
  • the combined memory array may enable byte and word programming capabilities where a single page may be programmed up to 32 times or more. Moreover, the combined array removes the need for a separate EEPROM area on an embedded system, such as SOC. Programming a single SONOS page multiple times without erasing may cause memory bits to experience elevated levels of inhibit disturb.
  • FIG. 1 A is a block diagram illustrating a cross-sectional side view of a non volatile memory transistor or device
  • FIG. 1B illustrates a corresponding schematic diagram of the non-volatile memory transistor or device depicted in FIG. 1 A;
  • FIG. 2 is a schematic diagram illustrating a non-volatile memory array according to one embodiment of the present disclosure
  • FIG. 3 A is a schematic diagram of a segment of a non-volatile memory array illustrating an embodiment of an erase operation according to the present disclosure
  • FIG. 3B is a schematic diagram of a segment of a non-volatile memory array illustrating an embodiment of a program operation according to the present disclosure
  • FIG. 4 is a graph illustrating the relationship of threshold voltages Vtp
  • FIG. 5 is a graph illustrating distribution of threshold voltages Vtp and Vtpi of memory transistors in a non-volatile memory array according to an embodiment of the present disclosure
  • FIG. 6 is a block diagram illustrating a word/byte write cycle of a row or a page in a non-volatile memory array according to an embodiment of the present disclosure
  • FIG. 7 is a graph illustrating distribution of threshold voltages Vtp, Vtpi (single inhibit), and Vtpi (multiple inhibits) of a memory transistor in a non-volatile memory array according to an embodiment of the present disclosure
  • FIG. 8 is a graph illustrating a relationship between inhibit threshold voltage Vtpi and program pulse width during a flash operation mode and an EEPROM operation mode of a memory transistor in a non-volatile memory array according to an embodiment of the present disclosure
  • FIG. 9 is a block diagram illustrating a cross-sectional side view of one embodiment of a non-volatile memory transistor pair in a non-volatile memory array according to an embodiment of the present disclosure
  • FIG. 10 is a graph illustrating distribution of threshold voltages Vtpi of a memory transistor in a non-volatile memory array operating as EEPROM according to another embodiment of the present disclosure
  • FIG. 11 is a block diagram illustrating a cross-sectional side view of a portion of one embodiment of a non-volatile memory transistor pair according to an embodiment of the present disclosure.
  • FIG. 12 is a schematic diagram illustrating an embedded NVM system including both flash memory and EEPROM memory in accordance with one embodiment of the subject matter. DETATUED DESCRIPTION
  • the memory device includes a non-volatile memory (NVM) array, divided into a flash memory portion and an electrically erasable programmable read-only memory (EEPROM) portion.
  • the NVM array includes charge-trapping memory cells arranged in rows and columns, in which each memory cell includes, a memory transistor including an angled lightly doped drain (LDD) implant in source and drain regions.
  • LDD lightly doped drain
  • the angled LDD implants extend at least partly under an oxide-nitride-oxide (ONO) stack of the memory transistor, and a select transistor including a shared source region with a halo implant.
  • the shared source region may be shared between two adjacent memory cells of a same row of the NVM array.
  • the flash memory portion and the EEPROM portion may be disposed within one single semiconductor die.
  • the memory cells of the NVM array may have a two- transistor (2T) architecture.
  • the memory transistors are silicon-oxide-nitride-oxide- silicon (SONOS) based, each including a charge-trapping oxynitride layer.
  • SONOS silicon-oxide-nitride-oxide- silicon
  • the charge-trapping oxynitride layer of the memory transistor has silicon content in an approximate range of 40 60 % and oxygen content in an approximate range
  • the halo implant may surround at least partly the shared source region of the two adjacent memory cells.
  • the select transistor may be an asymmetric transistor, in which the drain region of the select transistor may not have a halo implant.
  • the angled LDD implants of the memory transistor comprise dopant dose in an approximate range of lel2 - lel4 atoms per cm 2 .
  • the memory cells may be n-type transistors, and disposed at least partly within a p-type well.
  • the p-type well may have dopant dose in an approximate range of lel2 - lel4 atoms per cm 2 .
  • the p-type well may be doped with boron atoms around a junction with the source region of the memory transistor for a graded junction.
  • the shared source region of the select transistor may have a first LDD, wherein the first LDD and the halo implant are implanted with dopants of opposite types.
  • the EEPROM portion of the memory device is configured to perform word programming, in which multiple words may be written to one selected row of the NVM array sequentially using multiple program operations, and no erase operation is performed between each of the multiple program operations.
  • a memory array may have an electrically erasable programmable read-only memory (EEPROM) portion, comprising memory cells arranged in rows and columns.
  • EEPROM electrically erasable programmable read-only memory
  • each memory cell includes a charge-trapping non-volatile memory (NVM) transistor, memory cells in a same row share a SONOS word line, memory cells in a same column share a bit line, and memory cells in two adjacent columns couple to a common source line.
  • NVM non-volatile memory
  • memory cells in a same row share a SONOS word line
  • memory cells in a same column share a bit line
  • memory cells in two adjacent columns couple to a common source line.
  • a positive voltage is applied to a SONOS word line associated with the selected row
  • a high inhibit voltage in an approximate range of 1.5 V - 2.5 V may be applied to bit lines associated with memory cells of the first portion wherein an erased state is to be written, and the high inhibit voltage is further applied to bit lines associated with memory cells in portions of the selected row other than the first portion.
  • the high inhibit voltage may be applied to bit lines associated with memory cells of the second portion wherein the erased state is to be written, and memory cells in portions of the selected row other than the first and second portions.
  • the first and second portions do not overlap.
  • the memory array may also include a flash memory portion.
  • the flash memory portion and the EEPROM portion may be disposed within one single semiconductor die.
  • each of the memory cells of the EEPROM portion further includes an asymmetric select transistor, and the source of the asymmetric select transistor may have a halo implant.
  • an embedded system of the subject matter includes a non-volatile memory (NVM) array divided into a flash portion and an NVM (NVM) array divided into a flash portion and an NVM (NVM) array divided into a flash portion and an NVM (NVM) array divided into a flash portion and an NVM (NVM) array divided into a flash portion and an NVM (NVM) array divided into a flash portion and an
  • each of the flash and EEPROM portions include charge- trapping memory cells arranged in rows and columns.
  • Each memory cell may include a silicon-oxide-nitride-oxide-silicon (SONOS) based memory transistor including an angled lightly doped drain (LDD) implant in its source and drain regions. The drain region may be coupled to a bit line and a control gate to a SONOS word line.
  • the memory cell may further include a select transistor including a shared source region with a halo implant, in which the shared source region may be shared between two adjacent memory cells of a same row of the NVM array.
  • the embedded system may also have a programmable control circuitry coupled to the EEPROM portion. The programmable control circuitry is configured to provide operating voltages to enable word programming of one selected row of the EEPROM portion.
  • the angled LDD implants of the memory transistor may have dopant dose in an approximate range of lel2 - lel4 atoms per cm 2 .
  • the word programming includes writing multiple words sequentially to the selected row using multiple program operations. No erase operation is performed between each of the multiple program operations.
  • the operating voltages may include a first high voltage provided to a SONOS word line associated with memory cells of the selected row and a second high voltage provided to bit lines associated with memory cells to be inhibited.
  • the second high voltage is an inhibit voltage in an approximate range of 1.5 V - 2.5 V to reduce inhibit disturb.
  • FIG. 1 A is a block diagram illustrating a cross-sectional side view of a non volatile memory cell, and its corresponding schematic diagram is depicted in FIG. 1B.
  • a non-volatile memory (NVM) array or device may include NVM cells with a non-volatile memory transistor or device implemented using Silicon-Oxide-Nitride-Oxide-Silicon (SONOS) or floating gate technology, and a regular field-effect transistor (FET) disposed adjacent or couple to one another.
  • SONOS Silicon-Oxide-Nitride-Oxide-Silicon
  • FET regular field-effect transistor
  • the non-volatile memory transistor is a SONOS-type charge trapping non-volatile memory transistor.
  • NVM cell 90 includes a control gate (CG) or memory gate (MG) stack of NV transistor 94 formed over substrate 98.
  • NVM cell 90 further includes source 97/drain 88 regions formed in substrate 98, or optionally within well 93 in substrate 98, on either side of NV transistor 94. In one embodiment, source/drain regions are connected by channel region 91 underneath NV transistor 94.
  • NV transistor 94 includes an oxide tunnel dielectric layer, a nitride or oxynitride charge-trapping layer 92, an oxide top or blocking layer, forming the ONO stack.
  • a poly-silicon (poly) or metal layer disposed overlying the ONO layer, which may serve as a control gate (CG) or memory gate (MG).
  • NVM cell 90 further includes a FET 96 disposed adjacent to NV transistor 94.
  • FET 96 includes a metal or poly select gate (SG) disposed overlying an oxide gate dielectric layer.
  • FET 96 further includes source/drain regions formed in substrate 98, or optionally within well 93 in substrate 98, on either side of FET 96.
  • NVM cell 90 As best shown in FIG. 1 A, FET 96 and NV transistor 94 share source/drain region 97 disposed in between, or referred to as internal node 97. SG is appropriately biased VSG to open or close the channel 95 underneath FET 96.
  • NVM cell 90 as illustrated in FIG. 1 A, is considered having a two-transistor (2T) architecture, wherein NV transistor 94 and FET 96 may be considered the memory transistor and the select or pass transistor, respectively throughout this patent document.
  • FIG. 1B depicts a two-transistor (2T) SONOS NVM cell 90 with non-volatile (NV) transistor 94 connected in series with FET 96.
  • NVM cell 90 is programmed (bit value“1”) when CG is appropriately biased VCG, or by applying a positive pulse on CG with respect to substrate 98 or well 93 that causes electrons to be injected from the inversion layer into charge-trapping layer 92 by Fowler-Nordheim Tunneling (FNT).
  • 2T two-transistor
  • NV non-volatile
  • NVM cell 90 is erased by applying an opposite bias VCG on the CG, or a negative pulse on CG, with respect to substrate 98 or well 93 causing FNT of holes from the accumulated channel 91 into the ONO stack.
  • Programmed and erased threshold voltages are called“Vtp” and“Vte” respectively.
  • NV transistor 94 may also be in an inhibit state (bit value“0”) wherein a previously erased cell (bit value“0”) is inhibited from being programmed (bit value“1”) by applying a positive voltage on the source and drain of NVM cell 90 while control gate (CG) is pulsed positive with respect to substrate 98 or well 93 (as in the program condition).
  • the threshold voltage (referred to as“Vtpi”) of NV transistor 94 becomes slightly more positive due to the disturbing vertical field but it remains erased (or inhibited).
  • Vtpi is also determined by the ability of the charge-trapping layer 92 of the ONO stack to keep the trapped charges (holes for the erased state) in charge-trapping layer 92.
  • the NV transistor 94 may be a floating-gate MOS field- effect transistor (FGMOS) or device.
  • FGMOS floating-gate MOS field- effect transistor
  • a FGMOS includes a poly-silicon (poly) floating gate, which is capacitively coupled to inputs of the device, rather than a nitride or oxynitride charge-trapping layer 92.
  • the FGMOS device can be described with reference to FIGS. 1 A and 1B, and operated in a similar manner.
  • the FGMOS device may be programmed by applying an appropriate bias VCG between the control gate and the source and drain regions, raising the threshold voltage V T necessary to turn on the FGMOS device.
  • the FGMOS device can be erased by applying an opposite bias VCG on the control gate.
  • source/drain region 86 may be considered as the“source” of NVM cell 90, and coupled to VS L , while source/drain region 88 as the“drain”, and coupled to V BL .
  • well 93 is coupled with Vpw.
  • both FET 96 and NV transistor 94 may be n-type or n-channel transistors, wherein source/drain regions 86, 88, 97 are doped with n-type material while well 93 and/or substrate 98 is doped with p-type material.
  • NVM cell 90 may also include, additionally or alternatively, p-type or p-channel transistors, wherein the source/drain regions and well may be doped oppositely, or differently according to the practice of ordinary skill in the art.
  • a memory array is constructed by fabricating a grid of memory cells, such as NVM cells 90, arranged in rows and columns and connected by a number of horizontal and vertical control lines to peripheral circuitry such as address decoders and sense amplifiers.
  • Each memory cell includes at least one non-volatile semiconductor device, such as those described above, and may have a one-transistor (1T), or two-transistor (2T) architecture as described in FIG. 1 A.
  • FIG. 2 is a schematic diagram illustrating an NVM array in accordance with one embodiment of the subject matter.
  • the memory cell 90 has a 2T architecture and includes, in addition to a non-volatile memory transistor, a pass or select transistor, for example, a conventional IGFET sharing a common substrate connection, or internal node, with the memory transistor.
  • NVM array 100 includes NVM cells 90 arranged in N rows or page (horizontal) and M columns (vertical). NVM cells 90 in the same row may be considered to be in the same page. In some embodiments, several rows or pages may be grouped together to form memory sectors.
  • rows are arranged horizontally and columns are arranged vertically.
  • the terms of rows and columns of memory array may be reversed or used in an opposite sense, or arranged in any orientation.
  • a SONOS word line is coupled to all CGs of NVM cells 90 of the same row, a word line (WL) is coupled to all SGs of NVM cells 90 of the same row.
  • a bit lines are coupled to all drain regions 88 of NVM cells 90 of the same column, while a common source line (CSL) or region 86 is coupled or shared among all NVM cells in the array, in one embodiment.
  • a CSL may be shared between two paired NVM cells, such as Tl and T2 as best shown in FIG. 3A, of the same row.
  • An CSL also couples to shared source regions of all NVM pairs of the same two columns.
  • a write operation may consist of a bulk erase operation on a selected row (page) followed by program or inhibit operations on individual cells in the same row.
  • the smallest block of NVM cells that can be erased at a time is a single page (row).
  • the smallest block of cells that can be programmed/inhibited at a time may also be a single page.
  • NVM cells 90 may be arranged in pairs, such as NVM cell pair 200.
  • NVM cell pair 200 includes two NVM cells 90 having a mirrored orientation, such that select transistors of each NVM cell 90 is disposed adjacent to one another.
  • NVM cells 90 of the same NVM cell pair 200 may also share a common source region, receiving the voltage signal VCSL.
  • FIG. 3A illustrates a 2 x 2 array 300 of NVM array 100 to demonstrate an embodiment of an erase operation according to the present disclosure.
  • NVM array 100 may adopt a common source-line (CSL) configuration.
  • one single CSL e.g. CSL0
  • NVM cells e.g. Tl and T2
  • CSLs may be disposed and shared between select transistors of NVM cells 90 of adjacent columns.
  • all of the transistors in NVM array 100 including 2 x 2 array 300 are N- type transistors.
  • FIG. 3 A illustrates an exemplary embodiment of a segment of a NVM array 100, which may be part of a large memory array of memory cells.
  • 2 x 2 memory array 300 includes at least four memory cells Tl, T2, T3, and T4 arranged in two rows and two columns.
  • NVM cells Tl - T4 may be disposed in two adjacent columns (common source line CSL0), they may be disposed in two adjacent rows, or two non-adjacent rows. Each of the NVM cells Tl - T4 may be structurally similar to NVM cell 90 as described above.
  • Each of NVM cells Tl - T4 may include a SONOS based memory transistor and a select transistor.
  • Each of the memory transistors includes a drain coupled to a bit line (e.g. BL0 and BL1), a source coupled to a drain of the select transistor and, through the select transistor, to a single, common source line (e.g. CSL0).
  • Each memory transistor further includes a control gate coupled to a SONOS word line (e.g. WLS0).
  • the select transistors each includes a source coupled to the common source line (e.g. CSL0) and a select gate coupled to a word line (e.g. WL0).
  • page 0 is selected to be erased and page 1 is not (unselected) for an erase operation.
  • a single page may be the smallest block of NVM cells 90 that is erased in one operation. Therefore, all NVM cells including Tl and T2 in a selected row (page 0) are erased at once by applying the appropriate voltages to a SONOS word line (WLS0) shared by all NVM cells in the row, the substrate connection and to all bit lines in NVM array 100.
  • WLS0 SONOS word line
  • a negative voltage VNEG is applied to WLS0, and a positive voltage Vpos is applied to substrate or p-well via SPW of all NVM cells in page 0, all bit lines including BL0 and BL1, and the common source lines including CSL. Therefore, a full erase voltage (VNEG - VPOS) is impressed between CGs and substrate/P -wells of memory transistors in Tl and T2 to erase any previously trapped charge (if any) therein.
  • all word lines including WLO and WL1 are coupled to a supply voltage VPWR.
  • Table I depicts exemplary bias voltages that may be used for a bulk erase operation of page 0 of a non-volatile memory having a 2T-architecture and including memory cells with N-type SONOS transistors and CSLs, resembling 2 x 2 array 300.
  • FIG. 3B illustrates an exemplary embodiment of a segment 2 x 2 array 300 of NVM array 100, during a program operation.
  • NVM cell Tl is the targeted cell to be programmed or written to a logic " 1 " state (i.e., programmed to an OFF state) while NVM cell T2, already erased to a logic "0" state by a preceding erase operation as depicted in FIG. 3A, is maintained in a logic "0" or ON state.
  • Tl and T2 while being illustrated as two adjacent cells for illustrative purposes, may also be two separated NVM cells on the same row, such as row 0.
  • VPOS positive high voltage
  • VNEG negative high voltage
  • VINHIB inhibit voltage
  • the common source line CSLO between Tl and T2 or among all NVM cells 90 may be at a third high voltage or CSL voltage (VCSL), or allowed to float.
  • third high voltage VCSL may have a voltage level or absolute magnitude less than Vpos or VNEG.
  • VCSL may be generated by its own dedicated circuitry including DAC in the memory device (not shown).
  • VCSL may have an approximately same voltage level or absolute magnitude as margin voltage VMARG, which will be discussed in further detail in later sections.
  • This voltage reduces the gate-to- drain/channel voltage on the memory transistor of T2, reducing the programming field so that the shift in threshold voltage from Vte is small.
  • the tunneling of charges that may still occur is known as the inhibit disturb, and is quantified as (Vte - Vtpi).
  • all NVM cells of page 0 including Tl and T2 may attain a binary state of“1” (programmed - Vtp) or“0” (inhibited - Vtpi) based on the bit line voltage the NVM cell receives.
  • NVM cells in unselected pages, such as page 1 may remain the binary state of“0” (erased - Vte).
  • VMARG selected margin voltage
  • WLS1 in an unselected row or page (e.g. page 1) to reduce or substantially eliminate program- state bit line disturb in the unselected NVM cell T4 due to programming of the selected Tl.
  • the absolute voltage level or magnitude of VMARG may be the same as VCSL.
  • Table II depicts exemplary bias voltages that may be used for programming a non-volatile memory having a 2T-architecture and including memory cells with N-type
  • the margin voltage has the same polarity as the second high voltage or VNEG, but is higher or more positive than VNEG by a voltage equal to at least the threshold voltage (VT) of the memory transistors for which program state bit line disturb is reduced.
  • FIG. 4 depicts an embodiment of a set of pulse width curves for the SONOS based NVM cells.
  • the x-axis represents the duration of the pulse applied to the CG
  • the y-axis depicts the mean VT level of several cells in either a programmed, erased, or inhibited state.
  • program pulse time (Tp) 2 ms
  • erase pulse time (Te) 6 ms.
  • Vt window is defined as (Vtp - Vtpi).
  • FIG. 5 shows the Vtp & Vtpi distributions in an exemplary SONOS based NVM array, such as NVM array 100.
  • the Vtp and Vtpi levels depicted in FIG. 4 would correspond to the peaks of these two distributions.
  • the worst case Vt window determines if all the NVM cells in the array may be reliably read. Therefore, it is imperative to improve the worst case Vt window of the NVM array such that minimal number of NVM cells may be read incorrectly due to the close range of Vtp and Vtpi, especially after numerous write cycles.
  • NVM array 100 may be further divided into flash array 150 and EEPROM array 160.
  • NVM cells 90 in either flash array 150 and EEPROM array 160 may be SONOS based and structurally similar to the embodiment depicted in FIGS. 1 and 9.
  • flash array 150 and EEPROM array 160 may be SONOS based and structurally similar to the embodiment depicted in FIGS. 1 and 9.
  • flash array 150 and EEPROM array 160 may be SONOS based and structurally similar to the embodiment depicted in FIGS. 1 and 9.
  • EEPROM array 160 may be disposed adjacent to one another within a single memory array, or a single integrated circuit package, and may be fabricated simultaneously due to the similarity in structural features.
  • NVM array 100 may be configured that certain portion(s) (e.g. page 0 - X) to be functioned as a flash memory device, and other portion(s) (e.g. page X+l - N-l) as an EEPROM device.
  • the configuration may be achieved by connections to outside circuitry, and/or operation parameters including but not limited to voltage signals, signal duration, etc. It will be the understanding that there may be multiple portions of NVM array 100 configured to function as a flash memory or EEPROM device and those portions may or may not be physically adjacent to one another.
  • this particular data structure if this particular data structure is required to be updated frequently, this one page may be subjected to a high number of write cycles.
  • the high number of write cycles may adversely affect the performance of NVM cells of the page, such as the reduction of (Vtp - Vtpi) window as depicted in FIG. 5.
  • a circular buffer is adopted by the flash memory, such as flash memory array 150.
  • the data structure is written to a new page each time it is updated, and circling back to the first page when all available new pages have been written to.
  • unused bits in the pages may be driven into erase saturation.
  • flash memory 150 may be used to store data structures that are less frequently updated, and/or longer in bit length (compared to the page bit length of flash memory 150). For data that is updated frequently and shorter in bit length as previously described, it may be stored in EEPROM memory array 160 instead.
  • FIG. 6 illustrates a write cycle of a word/byte programming based EEPROM emulation on a page containing n words, such as EEPROM memory 160.
  • conventional EEPROM array is a floating gate based memory device.
  • EEPROM array 160 is structurally similar to flash memory 150, as in SONOS based charge-trapping memory instead, and also depicted in FIGS. 1 A and 1B.
  • the operation may be extended to byte programming or multiple byte/word programming. Writing to the page begins with a page erase in EEPROM array 160, the operation may be similar to the embodiment depicted in FIG.
  • n words (I st - n th word) are sequentially written to the same selected page.
  • each of the n words may have the same bit length or different bit lengths.
  • the I st word or program word 1 is written to a first portion of the selected page. It will be the understanding that the first portion, and any subsequent portions of the selected page, may be physically disposed in any column(s) of the selected page (row), and not limited to the first few columns as illustrated in FIG. 6. In one embodiment, the operation is similar to the embodiment depicted in FIG.
  • the first to (i-l)* 11 portions are re-programed with previous data, and the (i+l) th to n th portions are again inhibited.
  • the first to (i-l) th portions could be inhibited instead of being re-programmed for better endurance characteristics. The write cycle will continue until all n words are written into the selected page, or all NVM cells of the page are used.
  • some NVM cells in the selected page may be subjected up to n times of inhibit disturbs without a single erase operation.
  • some NVM cells may be subjected to a total program signal pulse duration of (2 x n) ms, if each program operation lasts 2 ms.
  • Vtpi of NVM cells moves positively (or towards Vtp) as the pulse duration increases.
  • the worst case Vt window as depicted in FIG. 7, will be further reduced, which may adversely affect the accuracy of read operations.
  • T2 is selected to be inhibited such that the binary state“0” is retained.
  • both the CG and drain of the memory transistor of T2 are coupled to a positive voltage, Vpos and VINHIB respectively. Since the memory transistor is in an erased state (channel opened), VINHIB may be transferred to the channel. As a result, the tunneling field across the ONO stack of the memory transistor may be reduced.
  • Vpos is kept approximately constant, a more positive (or greater in magnitude) VINHIB applied at the drain (via BL1) of T2 may lead to a reduced inhibit disturb (shift of Vtpi towards Vtp) of memory transistor in NVM cells that are selected to be inhibited (e.g. T2).
  • FIG. 8 is a graph illustrating a relationship between inhibit threshold voltage Vtpi and program pulse width during a flash operation mode and an EEPROM operation mode.
  • positive shift of Vtpi inhibit disturb
  • the issue may be more pronounced in EEPROM operation mode, such as the word/bype programming as depicted in FIG. 6 due to the potential multiple inhibit operations within a single write cycle (hence longer program pulse width) without an erase operation in between.
  • the rate of increase of Vtpi of the memory transistor is reduced when VINHIB applied to the drain of the NVM cell increases.
  • FIG. 9 is a block diagram illustrating a cross-sectional side view of one embodiment of a NVM transistor pair in a non-volatile memory array, such as NVM pair 200 in FIG. 2 or Tl and T2 in FIG. 3B.
  • Tl is selected to be programmed and T2 inhibited.
  • VINHIB is transferred to channel of the memory transistor and the internal node between the memory transistor and the select transistor.
  • a greater VINHIB e.g. 1.5 - 2.5 V
  • VINHIB is transferred to the channel of the memory transistor and internal node 902.
  • internal node 902 is doped in a similar manner as the source/drain regions of the NVM cell. Therefore, the increased VINHIB (e.g. 1.5 V or above) applied via the bit line BL1, which helps enable byte/word programming in the EEPROM operation mode, may also adversely increase the internal electric fields under SG of T2 which may in turn increase gate-induced drain leakage (GIDL) current at or around internal node 902 of T2 (Event - 1 in FIG. 9). In turn, the GIDL current may become a feed for avalanche multiplication (Event -2 in FIG.
  • GIDL gate-induced drain leakage
  • optimized doping and implant conditions may be performed to reduce the GIDL current at or around internal node 902 and the internal electric fields that lead to Vtpi tailing behavior at elevated VINHIB voltages (as depicted in FIG. 10).
  • FIG. 11 is a block diagram illustrating a cross-sectional side view of a portion of an NVM pair 200 during an embodiment of fabrication. It will be the understanding that the following doping schemes may be applicable or executed to other NVM cells in the NVM array, such as NVM array 100.
  • select transistor of NVM cell may be an asymmetric transistor, wherein its source and drain may have different doping schemes. As discussed previously, two adjacent NVM cells share a source region disposed between the two select transistors. In one embodiment, the shared source region may form a part of or coupled to the CSL. As best shown in FIG. 11, a lightly doped drain region (NLDD) 1106 is formed at or around the shared source region.
  • NLDD lightly doped drain region
  • NLDD 1106 may be formed by implanting n-type ions into the shared source region.
  • the NLDD 1106 implant formation may be part of a baseline fabrication process and use a mask (not shown) or spacers (not shown) as part of the implantation process.
  • the mask of the NLDD implant may be used to form a halo implant 1102 around the shared source region of the select transistor, without forming halo implants in other regions, such as the drain region of the select transistor (internal node 1120).
  • the halo implant 1102 may be high-tilt halo implants that are performed at an angle (see doping material 1104) so the halo implant 1102 is formed at least partially under SG.
  • Halo implant 1102 may encapsulate at least partly the previously formed NLDD 1106 and the shared source region of the select transistor, and be a p-type material 1104.
  • the halo implant 1102 may only be formed in the source region of the select transistor, making it an asymmetric select transistor.
  • asymmetric halo implant of the select transistor may increase SG threshold voltage and manage short-channel effects.
  • the reduced SG channel leakage may help curb the occurrence or degree of GIDL current (Event -1 in FIG. 9), which will contribute charge carriers that get injected into ONO stack of the memory transistor (unintentional soft programming or inhibit disturb) due to possible elevated VINHIB .
  • inhibit disturb may be reduced by controlling the dose, energy and/or implant angle of SONOS LDD implant (SLDD) 1110 at or around the source and drain regions of the memory transistor and/or drain region of select transistor.
  • select transistor may have NLDD 1106 on its source side and SLDD 1110 on its drain side.
  • SLDD 1110 may be formed by angled implant of n-type material 1108, such that SLDD 110 may be disposed at least partly under the ONO and CG stack of the memory transistor.
  • SLDD 1110 implant is formed using low implant dose in an approximate range of lel2 - lel4 atoms per cm 2 , a high energy in an approximate range of 2 keV - 20 keV, and a tilt angle in an approximate range of 0 to 30 degree.
  • the lower dose and higher energy SLDD 1110 at the internal node and drain of the memory transistor may help reduce SG GIDL current which is a feed current for possible SIIHE.
  • the SLDD 1110 may cause Vtp of the memory transistor to be more positive and Vtpi more negative, contributing to a larger worst case (Vtp - Vtpi) window.
  • the lower dose and high energy SLDD 1110 may also increase SG threshold voltage, thus reducing the channel leakage current.
  • inhibit disturb of the memory transistor may also be reduced by a light p-well 93 implant, in an approximate range of lel2 - lel4 atoms per cm 2 (p-type).
  • the lighter p-well 93 doping scheme may help reduce SG threshold voltage.
  • a graded junction at or around the interface of p-well 93 and source region of memory transistor may help reduce SIIHE generation at elevated VINH IB, such as in the range of 1.5 V - 2.5 V.
  • p-well 93 may be doped with boron or other p-type dopants in an approximate range of lel2 - lel4 atoms per cm 2 .
  • a different dose e.g. lower dose of dopant (less than lel2 - lel4 atoms per cm 2 ) and/or with varying energy at or around the interface between p-well 93 and source region (internal node 1120) of the memory transistor may create a graded junction, hence making the less drastic transition from p-well 93 (p-type doping) to internal node 1120 (n-type doping).
  • Inhibit disturb of the memory transistor may also be strongly dependent on the nature of charge traps in charge-trapping layer 92 of the ONO stack.
  • charge-trapping layer 92 may include silicon oxynitride (Si x O y N z ). Inhibit disturb may be reduced by minimizing the number of shallow charge traps by reducing the silicon content and/or increasing the oxygen content of the charge- trapping layer 92.
  • the silicon content may be controlled in an approximate range of 40 % - 60 % and oxygen content in an approximate range of 10 %
  • FIG. 12 is a schematic diagram illustrating an embedded NVM system including both flash memory and EEPROM memory in accordance with one embodiment of the subject matter.
  • FIG. 12 is a block diagram illustrating an embedded NVM system, according to an embodiment.
  • NVM system 1200 may include a processing device 1204 coupled to NVM device 1202 via address bus 1206, data bus 1208, and control bus 1210. It will be appreciated by those skilled in the art that NVM system 1200 has been simplified for the purpose of illustration, and not intended to be a complete description.
  • NVM system 1200 may include all, some, or more components than the embodiment in FIG. 12.
  • processing device 1204 may be the Programmable System on a Chip (PSoC ® ) processing device, developed by Cypress Semiconductor Corporation, San Jose, California.
  • PSoC ® Programmable System on a Chip
  • processing device 1204 may be one or more other processing devices known by those of ordinary skill in the art, such as a microprocessor or central processing unit (“CPU”), a controller, special-purpose processor, digital signal processor (“DSP”), an application specific integrated circuit (“ASIC”), a field programmable gate array (“FPGA”), or the like.
  • CPU central processing unit
  • DSP digital signal processor
  • ASIC application specific integrated circuit
  • FPGA field programmable gate array
  • NVM device 1202 includes memory array 1212, similar to NVM array 200 of FIG. 2, organized as rows and columns of non-volatile memory cells (not shown in FIG. 12) as described below.
  • NVM device 1202 may include various memory cells (not shown) configured to store data values.
  • the memory cells may be implemented with a 2T architecture and common source line to reduce the overall footprint of each memory cell.
  • Each memory cell may also be charge-trapping SONOS based and compatible with Fowler-Nordheim
  • Memory array 1212 may include one or more NVM sectors, such as sector A 1231 though sector N 1232.
  • a portion of sectors, for example sector A - E may be configured to function as flash memory, and another portion of sectors, e.g. sector F - N may be configured to function as EEPROM memory.
  • memory cells of both flash memory and EEPROM memory are structurally alike, charge-trapping SONOS based, and disposed within one single integrated circuit package or semiconductor die.
  • command and control circuitry 1224 may be programmable and configured to provide various operation voltage signals to memory array 1212 via SONOS word lines, word lines, bit lines, etc., including and not limited to VPOS, VNEG, VCSL, VMARG, VINHIB, as depicted in FIGS. 3A and 3B.
  • command and control circuitry 1224 may include a selection circuitry to select whether to write data structures to flash memory or
  • EEPROM memory with the same memory array 1212, depending on the nature of data structures.
  • Data structures with longer bit length or less frequently updated such as codes will be stored in flash memory, such as sector A - E, and data structures with shorter bit length or frequently updated such as Bluetooth pairing information will be selected to be stored in EEPROM memory, such as sector F - N.

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  • Read Only Memory (AREA)

Abstract

L'invention concerne un dispositif de mémoire qui comprend un réseau de mémoire non volatile (NVM), divisé en une partie de mémoire flash et une partie de mémoire morte programmable effaçable électriquement (EEPROM). Le réseau NVM comprend des cellules mémoires à piégeage de charge agencées en rangées et en colonnes, chaque cellule de mémoire comportant un transistor de mémoire comprenant un implant de drain légèrement dopé (LDD) incliné, et un transistor de sélection comprenant une région de source partagée avec un implant en halo. La partie de mémoire flash et la partie EEPROM sont disposées à l'intérieur d'une seule puce semi-conductrice. D'autres modes de réalisation sont également décrits.
EP18879309.5A 2017-11-14 2018-10-26 Schéma de polarisation pour programmation de mots dans une mémoire non volatile et pour inhiber une réduction de perturbation Pending EP3711051A4 (fr)

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US201762585739P 2017-11-14 2017-11-14
US201762591048P 2017-11-27 2017-11-27
US15/918,704 US10332599B2 (en) 2017-11-14 2018-03-12 Bias scheme for word programming in non-volatile memory and inhibit disturb reduction
PCT/US2018/057799 WO2019099169A1 (fr) 2017-11-14 2018-10-26 Schéma de polarisation pour programmation de mots dans une mémoire non volatile et pour inhiber une réduction de perturbation

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JP (1) JP7430138B2 (fr)
KR (1) KR102700213B1 (fr)
CN (1) CN111758129B (fr)
WO (1) WO2019099169A1 (fr)

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WO2019099169A1 (fr) 2019-05-23
US10332599B2 (en) 2019-06-25
CN111758129B (zh) 2024-05-10
TW201931579A (zh) 2019-08-01
JP2021503177A (ja) 2021-02-04
US20190147960A1 (en) 2019-05-16
US20200051642A1 (en) 2020-02-13
KR20200088366A (ko) 2020-07-22
EP3711051A4 (fr) 2021-09-15
KR102700213B1 (ko) 2024-08-29
CN111758129A (zh) 2020-10-09
JP7430138B2 (ja) 2024-02-09

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