EP3075006A1 - Circuit board structure - Google Patents

Circuit board structure

Info

Publication number
EP3075006A1
EP3075006A1 EP14805471.1A EP14805471A EP3075006A1 EP 3075006 A1 EP3075006 A1 EP 3075006A1 EP 14805471 A EP14805471 A EP 14805471A EP 3075006 A1 EP3075006 A1 EP 3075006A1
Authority
EP
European Patent Office
Prior art keywords
layer
circuit board
board structure
printed circuit
component
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
EP14805471.1A
Other languages
German (de)
French (fr)
Inventor
Johannes Stahr
Mike Morianz
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
AT&S Austria Technologie und Systemtechnik AG
Original Assignee
AT&S Austria Technologie und Systemtechnik AG
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by AT&S Austria Technologie und Systemtechnik AG filed Critical AT&S Austria Technologie und Systemtechnik AG
Publication of EP3075006A1 publication Critical patent/EP3075006A1/en
Pending legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K1/00—Printed circuits
    • H05K1/18—Printed circuits structurally associated with non-printed electric components
    • H05K1/182—Printed circuits structurally associated with non-printed electric components associated with components mounted in the printed circuit board, e.g. insert mounted components [IMC]
    • H05K1/185—Components encapsulated in the insulating substrate of the printed circuit or incorporated in internal layers of a multilayer circuit
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    • H01L23/538—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates
    • H01L23/5389—Arrangements for conducting electric current within the device in operation from one component to another, i.e. interconnections, e.g. wires, lead frames the interconnection structure between a plurality of semiconductor chips being formed on, or in, insulating substrates the chips being integrally enclosed by the interconnect and support structures
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    • H05K3/0017—Etching of the substrate by chemical or physical means
    • H05K3/0026—Etching of the substrate by chemical or physical means by laser ablation
    • H05K3/0032—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material
    • H05K3/0038—Etching of the substrate by chemical or physical means by laser ablation of organic insulating material combined with laser drilling through a metal layer
    • H—ELECTRICITY
    • H05—ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05K—PRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00—Apparatus or processes for manufacturing printed circuits
    • H05K3/10—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern
    • H05K3/108—Apparatus or processes for manufacturing printed circuits in which conductive material is applied to the insulating support in such a manner as to form the desired conductive pattern by semi-additive methods; masks therefor

Definitions

  • the invention relates to a printed circuit board structure consisting of at least one insulating layer, at least one conductor layer and at least one embedded component having an outer barrier layer possessing contact pad, wherein at least two interconnects / layers are connected via vias with at least two terminals.
  • the invention further relates to a method for contacting a component embedded in a printed circuit board structure with a printed conductor section by producing plated-through holes from a conductor layer to terminals of the component.
  • the contact pads of the components have copper connection pads, which are constructed on a barrier layer, in particular of nickel.
  • barrier layers are required to prevent diffusion of copper into adjacent layers, in the present case e.g. in an adhesion layer, which consists for example of titanium, titanium-tungsten or chromium.
  • an adhesion layer which consists for example of titanium, titanium-tungsten or chromium.
  • semiconductors e.g. a power MOSFET
  • a contact made of, for example, aluminum for the drain or gate of a MOSFET.
  • An object of the invention is to provide a printed circuit board structure or a method for their production, wherein the production costs can be reduced, the use of extremely thin components, for example, a thickness of the order of 20 m is possible and the use of copper connections to the components to be embedded can be omitted.
  • This object is achieved with a printed circuit board structure of the aforementioned type, in which, according to the invention, each plated-through hole runs from a conductor track / layer directly to the barrier contact layer of the corresponding terminal of the component.
  • the material of the barrier contact layer is selected from the group consisting of nickel, nickel vanadium, platinum, palladium and cobalt.
  • the material of the barrier contact layer is nickel.
  • Cost-effective and technologically easy to control are versions in which the plated through hole is made of copper.
  • an adhesion layer is arranged below the barrier contact layer, wherein the adhesion layer is advantageously selected from the group consisting of titanium, titanium tungsten and chromium.
  • the invention is particularly advantageous when the component is a power component, which may be an IGBT chip / MOSFET or a power diode.
  • the invention advantageously leads to variants in which the printed circuit board structure is at least partially flexible.
  • the object is also achieved with a method of the type mentioned above, in which according to the invention in the region of the terminals of the component in an outer conductor layer at least one opening is made, which extends to a barrier layer of a terminal, and then at least one via from the conductor / Layer is made directly to the barrier layer of the corresponding terminal of the component.
  • electroless copper plating is performed on at least one side of the printed circuit board structure to form a copper layer on the surface and in the openings.
  • the at least one opening is produced by laser cutting.
  • the at least one opening is chemically cleaned before the vias are produced.
  • the chemical cleaning step can usefully reduce the thickness of the barrier layer.
  • a mask is applied to the at least one side of the printed circuit board structure, followed by a galvanic copper plating to produce at least one conductor layer and the completion of plated-through holes and removal of the mask.
  • FIG. 2 shows in a section as a component, for example, a power MOSFET before embedding in a printed circuit board structure and before contacting
  • Fig. 9 shows a variant of a printed circuit board structure according to the invention with a total of four embedded components
  • FIG. 9a shows a section of FIG. 9 with a modified plated through hole in two components.
  • FIGS. 1 a and 1 b which initially explain the principal difference between a contacting of a contact pad of an embedded component according to the prior art on the one hand and according to the invention on the other hand.
  • a component 1a shows in a detailed view a component 1, for example a chip, which, for contacting on its surface, has a flat contact 2, e.g. made of aluminum.
  • a flat contact 2 e.g. made of aluminum.
  • An existing example of titanium, titanium-tungsten or chromium contact adhesion layer 3 is located and this is connected with the interposition of a barrier layer 4 with a contact pad 5, which is usually made of copper.
  • a passivation layer 6 is applied, which consists mostly of silicon nitride.
  • a through-connection is made 9, which, as also explained in more detail below, is prepared by galvanic means.
  • the connection between the conductor track 7 and the terminal 8 of the component 1 thus takes place via a "two-stage" copper connection, namely the plated-through hole 9 and the copper contact pad 5.
  • Fig. Lb shows, in which the same reference numerals as in Fig. 1 a are used for the same parts, that according to the invention, the feedthrough 9 of the conductor 7 extends directly to the barrier layer 4 of the contact pad of the terminal 8.
  • FIG. 2 shows, as an example of a component 1, a power MOSFET which according to the invention is to be embedded in a printed circuit board structure and is contacted on both sides in planar technology.
  • the silicon substrate 1s whose structure is not shown in detail, has on its underside for the drain terminal 8d a flat drain contact 2d made of aluminum, followed by a drain adhesion layer 3 d made of titanium and a drain barrier layer 4d made of nickel.
  • a flat gate contact 2g made of aluminum, above a gate adhesion layer 3g and finally a gate barrier layer 4g are provided for the gate connection 8g.
  • a passivation layer 6 of silicon nitride is also present on the upper side.
  • top refers primarily to the drawings and serve to simplify the description, but not necessarily with any orientation refer to described parts or their orientation in the manufacturing process.
  • FIGS. 3 to 8 wherein the embedding and contacting of the component according to FIG. 2 is shown here with reference to a section of a printed circuit board component.
  • the component 1 is embedded in a printed circuit board, which in the present case consists of an insulating layer 10 with an upper conductor layer 11 and a lower conductor layer 12.
  • the insulating layer 10 may be a commercial prepreg based on an epoxy resin with glass fiber reinforcement, e.g. FR 4 or in other cases e.g. a polyimide with or without reinforcement, the conductor layers are usually copper foils.
  • a window 13 is formed, which frees the underside of the component or the drain terminal 8d.
  • two openings namely a gate opening 14 and a source opening 15 are provided at the top by etching away of copper of the upper conductor layer or laser cutting of the insulating layer 10, up to the gate barrier layer 4g or to the source barrier layer 4s of the gate terminal 8g or of the source terminal 8s.
  • the openings 14, 15 are cleaned with well-known in the field of printed circuit Lochthesesvon, eg by chemical cleaning using potassium permanganate and the thickness of all the barrier layers 4d, 4g, 4s can be reduced by chemical dissolution of the barrier layers.
  • the reduced thickness of the barrier layers 4d, 4g, 4s in FIG. 5 can be seen.
  • the barrier layers 4d, 4g, 4s have a thickness of at least 100 nm or more before cleaning and are reduced by, for example, 50 nm in the cleaning step, for example by up to 500 nm in the case of thicker barrier layers.
  • FIG. 1 An upper copper layer 16 and a lower copper layer 17 are formed, wherein the upper copper layer 16 covers not only the upper conductor layer 11 but also the walls of the openings 14 and 15 and the gate barrier layer 4g and the source barrier layer 4s, respectively. Similarly, the lower copper layer 17 covers the lower conductor layer 12 and the one drain barrier layer 4d.
  • 9 shows by way of example a further embodiment of a printed circuit board structure 22, which is manufactured according to the method described above and contains a total of four components, namely a first MOSFET 23, eg a "high source FET", a second MOSFET 24, eg a "low Source FET ", a drive chip 25 and a capacitor 26, for example of the" Multilayer Cofired Ceramic "type.
  • FIG. 9 also shows two plated-through holes 27, 28 between the upper and lower conductor layers 19, 20, wherein a plated-through hole 28 establishes a connection between source S of the first MOSFET 23 and drain D of the second MOSFET 24.
  • the vias from the bottom conductor layer 20 to the drains of the MOSFETs are split into three and five vias 9, respectively.
  • all plated-through holes of the conductor layers 19, 20 are provided with component reference numbers "9".
  • the drive chip 25 is arranged to the right of the MOSFET 24, and to the right of this the capacitor 26.
  • the structure of the electrode contacting in the MOSFETs 23 and 24 and the drive chip 25 is the same as shown in Fig. 16 and Fig. 2, it thus consists - from the inside to the outside - of a contact layer, a contact adhesion layer and a barrier layer.
  • the two terminals of the capacitor 26 are each internally provided with a contact adhesion layer 26-3 on which a contact barrier layer 26-4 follows.
  • the adhesion layers 26-3 are preferably made of chromium and the barrier layers 26-4 of nickel.
  • the circuit board structure 22 shown in FIG. 9 may contain further components, not shown here, such as power diodes, resistors and inductors.
  • the thickness of the circuit board structure can be kept very low, it is also easily possible to make them at least partially flexible, in which case, for example, offers as a material for the insulating layer polyimide.

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  • Microelectronics & Electronic Packaging (AREA)
  • Computer Hardware Design (AREA)
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  • Manufacturing & Machinery (AREA)
  • Condensed Matter Physics & Semiconductors (AREA)
  • Physics & Mathematics (AREA)
  • General Physics & Mathematics (AREA)
  • Internal Circuitry In Semiconductor Integrated Circuit Devices (AREA)
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Abstract

The invention relates to a circuit board structure (21, 22), comprising at least one insulating layer (10), at least one conducting layer (11, 12), and at least one embedded component (1, 23 - 26) having contact pads (5) having an outer barrier layer (4), wherein at least two conducting tracks/conducting layers (19, 20) are connected to at least two connections (8; 8d, 8g, 8s) by means of vias (9; 9d, 9g, 9s) and each via (9; 9d, 9g, 9s) extends from a conducting track/conducting layer (11, 12) directly to the barrier contact layer (4; 4d, 4g, 4s) of the corresponding connection (8; 8d, 8g, 8s) of the component (1, 23 - 26).

Description

LEITERPLATTENSTRUKTUR  CIRCUIT BOARD STRUCTURE
Die Erfindung bezieht sich auf eine Leiterplattenstruktur bestehend aus zumindest einer Isolierschicht, zumindest einer Leiterschicht und zumindest einer eingebetteten Komponente mit eine äußere Barriereschicht besitzenden Kontaktpads, bei welcher zumindest zwei Leiterbahnen/ -schichten über Durchkontaktierungen mit zumindest zwei Anschlüssen verbunden sind. The invention relates to a printed circuit board structure consisting of at least one insulating layer, at least one conductor layer and at least one embedded component having an outer barrier layer possessing contact pad, wherein at least two interconnects / layers are connected via vias with at least two terminals.
Die Erfindung bezieht sich weiters auf ein Verfahren zum Ankontaktieren einer in einer Leiterplattenstruktur eingebetteten Komponente an einen Leiterbahnabschnitt durch Herstellung von Durchkontaktierungen von einer Leiterschicht zu Anschlüssen der Komponente. The invention further relates to a method for contacting a component embedded in a printed circuit board structure with a printed conductor section by producing plated-through holes from a conductor layer to terminals of the component.
Nach dem Stand der Technik werden Komponenten in Leiterstrukturen eingebettet und über Kupfer-Durchkontaktierungen mit Leiterbahnen verbunden. Dazu weisen die Kontaktpads der Komponenten Kupferanschlusspads auf, die auf einer Barriereschicht, insbesondere aus Nickel, aufgebaut sind. Derartige Barriereschichten sind erforderlich, um ein Diffundieren von Kupfer in angrenzende Schichten zu verhindern, im vorliegenden Fall z.B. in eine Adhäsionsschicht, die beispielsweise aus Titan, Titan-Wolfram oder Chrom besteht. Unterhalb der Adhäsionsschicht liegt im Falle von Halbleitern, wie z.B. einem Leistungs-MOSFET, ein Kontakt aus beispielsweise Aluminium, für den Drain oder das Gate eines MOSFETs. According to the prior art components are embedded in conductor structures and connected via copper vias with interconnects. For this purpose, the contact pads of the components have copper connection pads, which are constructed on a barrier layer, in particular of nickel. Such barrier layers are required to prevent diffusion of copper into adjacent layers, in the present case e.g. in an adhesion layer, which consists for example of titanium, titanium-tungsten or chromium. Below the adhesion layer, in the case of semiconductors, e.g. a power MOSFET, a contact made of, for example, aluminum, for the drain or gate of a MOSFET.
Nach dem Stand der Technik sind metallische Anschlusspads, meist aus Kupfer, an den Anschlüssen der Komponenten erforderlich, um ein einwandfreies Verbinden der Anschlüsse mit Leiterbahnen über Kupferdurchkontaktierungen zu ermöglichen. Es ist bereits möglich, elektronische und elektronische Komponenten äußerst dünn zu gestalten, nämlich in der Größenordnung von 20 m, jedoch ergibt sich durch solche Anschlusspads aus Kupfer eine vergleichsweise große Dicke des gesamten Leiterplattenaufbaus. In the prior art, metal pads, usually made of copper, at the terminals of the components required to allow a perfect connection of the terminals with interconnects on Kupferdurchkontaktierungen. It is already possible to make electronic and electronic components extremely thin, namely in the order of 20 m, but results from such copper pads from a comparatively large thickness of the entire printed circuit board assembly.
Eine Aufgabe der Erfindung liegt in der Schaffung einer Leiterplattenstruktur bzw. eines Verfahrens zu deren Herstellung, wobei die Produktionskosten gesenkt werden können, die Verwendung auch extrem dünner Komponenten, z.B. einer Dicke in der Größenordnung von 20 m ermöglicht ist und die Verwendung von Kupferanschlüssen an den einzubettenden Komponenten entfallen kann. Diese Aufgabe wird mit einer Leiterplattenstruktur der eingangs genannten Art gelöst, bei welcher erfindungsgemäß jede Durchkontaktierung von einer Leiterbahn/ -Schicht unmittelbar zu der Barriere-Kontaktschicht des entsprechenden Anschlusses der Komponente verläuft. An object of the invention is to provide a printed circuit board structure or a method for their production, wherein the production costs can be reduced, the use of extremely thin components, for example, a thickness of the order of 20 m is possible and the use of copper connections to the components to be embedded can be omitted. This object is achieved with a printed circuit board structure of the aforementioned type, in which, according to the invention, each plated-through hole runs from a conductor track / layer directly to the barrier contact layer of the corresponding terminal of the component.
Dank der Erfindung ergibt sich eine vereinfachte Herstellung von Leiterplattenstrukturen, die auch extrem dünn gestaltet werden können. Thanks to the invention results in a simplified production of printed circuit board structures, which can also be made extremely thin.
Bei zweckmäßigen Ausführungsformen ist das Material der Barriere-Kontaktschicht aus der Gruppe Nickel, Nickel-Vanadium, Platin, Palladium und Kobalt gewählt. In expedient embodiments, the material of the barrier contact layer is selected from the group consisting of nickel, nickel vanadium, platinum, palladium and cobalt.
Weiters ist es vorteilhaft, wenn das Material der Barriere-Kontaktschicht Nickel ist. Furthermore, it is advantageous if the material of the barrier contact layer is nickel.
Kostengünstig und technologisch leicht zu beherrschen sind Ausführungen, bei welchen die Durchkontaktierung aus Kupfer besteht. Cost-effective and technologically easy to control are versions in which the plated through hole is made of copper.
Bei zuverlässigen Varianten ist vorgesehen, dass unterhalb der Barriere-Kontaktschicht eine Adhäsionsschicht angeordnet ist, wobei die Adhäsionsschicht mit Vorteil aus der Gruppe Titan, Titan-Wolfram und Chrom ausgewählt ist. In reliable variants, it is provided that an adhesion layer is arranged below the barrier contact layer, wherein the adhesion layer is advantageously selected from the group consisting of titanium, titanium tungsten and chromium.
Die Erfindung zeigt ihre Vorzüge besonders, wenn die Komponente eine Leistungskomponente ist, wobei diese ein IGBT-Chip/MOSFET oder eine Leistungsdiode sein kann. The invention is particularly advantageous when the component is a power component, which may be an IGBT chip / MOSFET or a power diode.
Die Erfindung führt mit Vorteil zu Varianten, bei welchen die Leiterplattenstruktur zumindest abschnittsweise flexibel ausgebildet ist. The invention advantageously leads to variants in which the printed circuit board structure is at least partially flexible.
Die Aufgabe wird auch mit einem Verfahren der eingangs genannten Art gelöst, bei welchem erfindungsgemäß im Bereich der Anschlüsse der Komponente in einer äußeren Leiterschicht zumindest eine Öffnung hergestellt wird, die bis zu einer Barriereschicht eines Anschlusses reicht, und daraufhin zumindest eine Durchkontaktierung von der Leiterbahn/ - schicht unmittelbar zu der Barriereschicht des entsprechenden Anschlusses der Komponente hergestellt wird. Bei einer vorteilhaften Variante ist vorgesehen, dass zur Bildung einer Kupferschicht an der Oberfläche und in den Öffnungen ein stromloses Verkupfern an zumindest einer Seite der Leiterplattenstruktur durchgeführt wird. The object is also achieved with a method of the type mentioned above, in which according to the invention in the region of the terminals of the component in an outer conductor layer at least one opening is made, which extends to a barrier layer of a terminal, and then at least one via from the conductor / Layer is made directly to the barrier layer of the corresponding terminal of the component. In an advantageous variant, it is provided that electroless copper plating is performed on at least one side of the printed circuit board structure to form a copper layer on the surface and in the openings.
Zweckmäßig ist es weiters, wenn die zumindest eine Öffnung durch Laser-Schneiden hergestellt wird. It is expedient if the at least one opening is produced by laser cutting.
Auch ist es empfehlenswert, wenn vor dem Herstellen der Durchkontaktierungen die zumindest eine Öffnung chemisch gereinigt wird. It is also advisable if the at least one opening is chemically cleaned before the vias are produced.
Bei dem Schritt des chemischen Reinigens kann sinnvollerweise die Dicke der Barriereschicht verringert werden. The chemical cleaning step can usefully reduce the thickness of the barrier layer.
Bei einer vorteilhaften Variante des Verfahrens ist vorgesehen, dass nach dem stromlosen Verkupfern eine Maske auf die zumindest eine Seite der Leiterplattenstruktur aufgebracht und darnach ein galvanisches Verkupfern zur Herstellung zumindest einer Leiterschicht und der Fertigstellung Durchkontaktierungen sowie ein Entfernen der Maske erfolgt. Die Erfindung samt weiteren Vorteilen ist im Folgenden an Hand beispielsweiser Ausführungsformen erläutert, die in der Zeichnung veranschaulicht sind. In dieser zeigen In an advantageous variant of the method, it is provided that, after the electroless copper plating, a mask is applied to the at least one side of the printed circuit board structure, followed by a galvanic copper plating to produce at least one conductor layer and the completion of plated-through holes and removal of the mask. The invention together with further advantages is explained below with reference to beispielsweiser embodiments, which are illustrated in the drawing. In this show
Fig. la bzw. lb in einer stark vergrößerten geschnittenen Detailansicht die Kontaktierung eines Kontaktpads in einer Leiterplatte nach dem Stand der Technik bzw. der Erfindung, 1a and 1b in a greatly enlarged sectional detail view the contacting of a contact pad in a printed circuit board according to the prior art or the invention,
Fig. 2 in einem Schnitt als beispielsweise Komponente einen Leistungs-MOSFET vor dem Einbetten in eine Leiterplattenstruktur und vor dem Kontaktieren, 2 shows in a section as a component, for example, a power MOSFET before embedding in a printed circuit board structure and before contacting
Fig. 3 bis 8 je in Schnitten durch eine Leiterplattenstruktur einzelne Schritte eines erfindungsgemäßen Verfahrens zum Einbetten der in Fig. 2 gezeigten Komponente Fig. 9 eine Variante einer erfindungsgemäßen Leiterplattenstruktur mit insgesamt vier eingebetteten Komponenten und 3 to 8 each in sections through a printed circuit board structure individual steps of a method according to the invention for embedding the component shown in Fig. 2 Fig. 9 shows a variant of a printed circuit board structure according to the invention with a total of four embedded components and
Fig. 9a einen Ausschnitt der Fig. 9 mit einer geänderten Durchkontaktierung bei zwei Komponenten. Eingangs wird auf Fig. la und lb Bezug genommen, die zunächst den prinzipiellen Unterschied zwischen einer Kontaktierung eines Kontaktpads einer eingebetteten Komponente nach dem Stand der Technik einerseits und nach der Erfindung andererseits erläutern. 9a shows a section of FIG. 9 with a modified plated through hole in two components. Reference is first made to FIGS. 1 a and 1 b, which initially explain the principal difference between a contacting of a contact pad of an embedded component according to the prior art on the one hand and according to the invention on the other hand.
Fig. la zeigt in einer Detailansicht eine Komponente 1, beispielsweise einen Chip, die zur Kontaktierung an ihrer Oberfläche einen flachen Kontakt 2, z.B. aus Aluminium, aufweist. Darüber ist eine beispielsweise aus Titan, Titan-Wolfram oder Chrom bestehende Kontakt- Adhäsionsschicht 3 gelegen und diese ist unter Zwischenschaltung einer Barriereschicht 4 mit einem Kontaktpad 5, das üblicherweise aus Kupfer besteht, verbunden. An der oberen Oberfläche der Komponente 1 ist außerdem eine Passivierungsschicht 6 aufgebracht, die meist aus Siliziumnitrid besteht. 1a shows in a detailed view a component 1, for example a chip, which, for contacting on its surface, has a flat contact 2, e.g. made of aluminum. An existing example of titanium, titanium-tungsten or chromium contact adhesion layer 3 is located and this is connected with the interposition of a barrier layer 4 with a contact pad 5, which is usually made of copper. On the upper surface of the component 1 also a passivation layer 6 is applied, which consists mostly of silicon nitride.
Zur Verbindung mit einer meist aus Kupfer bestehenden Leiterbahn 7 oder Leiterschicht innerhalb einer erst weiter unten gezeigten Leiterplattenstruktur ist von der Leiterbahn 7 zu dem aus dem Kontakt 2, der Adhäsionsschicht 3, der Barriereschicht 4 und dem Kontaktpad 5 bestehenden Anschluss 8 der Komponente 1 eine Durchkontaktierung 9 vorgesehen, die, wie gleichfalls weiter unten näher erläutert, auf galvanischem Weg hergestellt wird. Die Verbindung zwischen der Leiterbahn 7 und dem Anschluss 8 der Komponente 1 erfolgt somit über eine„zweistufige" Kupfer Verbindung, nämlich die Durchkontaktierung 9 und das Kupfer-Kontaktpad 5. For connection to a conductor track 7 or conductor layer, which usually consists of copper, within a printed circuit board structure shown below, from the conductor track 7 to the connection 8 of the component 1 consisting of the contact 2, the adhesion layer 3, the barrier layer 4 and the contact pad 5, a through-connection is made 9, which, as also explained in more detail below, is prepared by galvanic means. The connection between the conductor track 7 and the terminal 8 of the component 1 thus takes place via a "two-stage" copper connection, namely the plated-through hole 9 and the copper contact pad 5.
Im Gegensatz dazu zeigt Fig. lb, in welcher für gleiche Teile gleiche Bezugszeichen wie in Fig. 1 a verwendet werden, dass erfindungsgemäß die Durchkontaktierung 9 von der Leiterbahn 7 unmittelbar zu der Barriereschicht 4 des Kontaktpads der Anschlusses 8 verläuft. In contrast, Fig. Lb shows, in which the same reference numerals as in Fig. 1 a are used for the same parts, that according to the invention, the feedthrough 9 of the conductor 7 extends directly to the barrier layer 4 of the contact pad of the terminal 8.
In Fig. 2 ist als Beispiel für eine Komponente 1 ein Leistungs-MOSFET gezeigt, der erfindungsgemäße in eine Leiterplattenstruktur eingebettet werden soll und beidseitig kontaktiert in Planartechnik hergestellt ist. Das Siliziumsubstrat ls, dessen Aufbau nicht näher gezeigt ist, besitzt an seiner Unterseite für den Drain-Anschluss 8d einen flacher Drain- Kontakt 2d aus Aluminium, dem eine Drain-Adhäsionsschicht 3 d aus Titan sowie eine Drain-Barriereschicht 4d aus Nickel folgen. An der Oberseite der Komponente 1 sind für den Gate-Anschluss 8g ein flacher Gate-Kontakt 2g aus Aluminium, darüber eine Gate- Adhäsionsschicht 3g und schließlich eine Gate-Barriereschicht 4g vorgesehen und sinnge- maß gleiches gilt für den Source-Anschluss 8s mit einem flachen Source-Kontakt 2s aus Aluminium, einer Source-Adhäsionsschicht 3s und einer Source-Barriereschicht 4s. Wie bereits in Fig. 1 gezeigt, ist an der Oberseite auch eine Passivierungsschicht 6 aus Siliziumnitrid vorhanden. FIG. 2 shows, as an example of a component 1, a power MOSFET which according to the invention is to be embedded in a printed circuit board structure and is contacted on both sides in planar technology. The silicon substrate 1s, whose structure is not shown in detail, has on its underside for the drain terminal 8d a flat drain contact 2d made of aluminum, followed by a drain adhesion layer 3 d made of titanium and a drain barrier layer 4d made of nickel. At the upper side of the component 1, a flat gate contact 2g made of aluminum, above a gate adhesion layer 3g and finally a gate barrier layer 4g are provided for the gate connection 8g. the same applies to the source terminal 8s with a shallow source contact 2s made of aluminum, a source adhesion layer 3s and a source barrier layer 4s. As already shown in FIG. 1, a passivation layer 6 of silicon nitride is also present on the upper side.
An dieser Stelle soll angemerkt werden, dass sich Begriffe wie„oben",„unten",„obere", „untere" und ähnliche in erster Linie auf die Zeichnungen beziehen und der Vereinfachung der Beschreibung dienen, sich jedoch nicht notwendigerweise mit irgendeiner Orientierung der beschriebenen Teile oder deren Ausrichtung bei dem Herstellungsverfahren beziehen. It should be noted at this point that terms such as "top", "bottom", "top", "bottom" and the like refer primarily to the drawings and serve to simplify the description, but not necessarily with any orientation refer to described parts or their orientation in the manufacturing process.
Nachstehend wird unter Bezugnahme auf die Fig. 3 bis 8 die Herstellung einer erfindungsgemäßen Leiterplattenstruktur beschrieben, wobei hier das Einbetten und Kontaktieren der Komponente nach Fig. 2 an Hand eines Ausschnittes einer Leiterplattenkomponente gezeigt wird. The production of a printed circuit board structure according to the invention will now be described with reference to FIGS. 3 to 8, wherein the embedding and contacting of the component according to FIG. 2 is shown here with reference to a section of a printed circuit board component.
In einem ersten Schritt wird gemäß Fig. 3 die Komponente 1 in eine Leiterplatte eingebettet, die im vorliegenden Fall aus einer Isolierschicht 10 mit einer oberen Leiterschicht 11 und einer unteren Leiterschicht 12 besteht. Die Isolierschicht 10 kann ein handelsübliches Prepreg auf Basis eines Epoxidharzes mit Glasfaserverstärkung, z.B. FR 4 sein oder in anderen Fällen z.B. ein Polyimid mit oder ohne Verstärkung sein, die Leiterschichten sind üblicherweise Kupferfolien. In der unteren Leiterschicht 12 ist ein Fenster 13 ausgebildet, welches die Unterseite der Komponente bzw. den Drain- Anschluss 8d freistellt. In a first step, according to FIG. 3, the component 1 is embedded in a printed circuit board, which in the present case consists of an insulating layer 10 with an upper conductor layer 11 and a lower conductor layer 12. The insulating layer 10 may be a commercial prepreg based on an epoxy resin with glass fiber reinforcement, e.g. FR 4 or in other cases e.g. a polyimide with or without reinforcement, the conductor layers are usually copper foils. In the lower conductor layer 12, a window 13 is formed, which frees the underside of the component or the drain terminal 8d.
In einem nächsten Schritt, siehe Fig. 4, werden an der Oberseite durch Wegätzen von Kupfer der oberen Leiterschicht bzw. Laserschneiden der Isolierschicht 10 zwei Öffnungen, nämlich eine Gate-Öffnung 14 und eine Source-Öffnung 15 geschaffen, die bis zur Gate- Barriereschicht 4g bzw. bis zur Source-Barriereschicht 4s des gate- Anschlusses 8g bzw. des Source- Anschlusses 8s reichen. In a next step, see Fig. 4, two openings, namely a gate opening 14 and a source opening 15 are provided at the top by etching away of copper of the upper conductor layer or laser cutting of the insulating layer 10, up to the gate barrier layer 4g or to the source barrier layer 4s of the gate terminal 8g or of the source terminal 8s.
In einem weiteren Schritt werden die Öffnungen 14, 15 gereinigt mit auf dem Gebiet der Leiterplatten bekannten Lochreinigungsprozessen, z.B. durch chemisches reinigen unter Verwendung von Kaliumpermanganat und die Dicke aller Barriereschichten 4d, 4g, 4s kann durch chemische Auflösung der Barriereschichten verringert werden. Man erkennt die verringerte Dicke der Barriereschichten 4d, 4g, 4s in Fig. 5. Die Barriereschichten 4d, 4g, 4s weisen vor dem Reinigen eine Dicke von zumindest 100 nm oder mehr auf und werden im Reinigungsschritt um beispielsweise 50 nm, bei dickeren Barriereschichten um beispielsweise bis 500 nm reduziert. In a further step, the openings 14, 15 are cleaned with well-known in the field of printed circuit Lochreinigungsprozessen, eg by chemical cleaning using potassium permanganate and the thickness of all the barrier layers 4d, 4g, 4s can be reduced by chemical dissolution of the barrier layers. The reduced thickness of the barrier layers 4d, 4g, 4s in FIG. 5 can be seen. The barrier layers 4d, 4g, 4s have a thickness of at least 100 nm or more before cleaning and are reduced by, for example, 50 nm in the cleaning step, for example by up to 500 nm in the case of thicker barrier layers.
Das Ergebnis eines folgenden Schrittes, bei welchem ein stromloses Verkupfern sowohl an der Oberseite als auch an der Unterseite erfolgt, ist in Fig. 6 gezeigt. Es wird eine obere Kupferschicht 16 und eine untere Kupferschicht 17 gebildet, wobei die obere Kupferschicht 16 nicht nur die oberer Leiterschicht 11 bedeckt, sondern auch die Wände der Öffnungen 14 und 15 sowie die Gate-Barriereschicht 4g bzw. die Source-Barriereschicht 4s. Ebenso bedeckt die untere Kupferschicht 17 die untere Leiterschicht 12 sowie die eine Drain-Barriereschicht 4d. The result of a subsequent step in which electroless copper plating occurs both at the top and at the bottom is shown in FIG. An upper copper layer 16 and a lower copper layer 17 are formed, wherein the upper copper layer 16 covers not only the upper conductor layer 11 but also the walls of the openings 14 and 15 and the gate barrier layer 4g and the source barrier layer 4s, respectively. Similarly, the lower copper layer 17 covers the lower conductor layer 12 and the one drain barrier layer 4d.
Wenn in dieser Beschreibung von Kupferschichten, Kupfer-Leiterbahnen und Ähnlichem gesprochen wird, soll dies keineswegs die Verwendung geeigneter anderer leitfähiger Materialien, wie z.B. Gold und Silber ausschließen. When talking about copper layers, copper traces and the like in this description, this is by no means intended to denote the use of suitable other conductive materials, such as e.g. Exclude gold and silver.
Unter Bezugnahme auf Fig. 7 wird der nächste Schritt erörtert, in welchem sowohl an der Unter- als auch an der Oberseite ein galvanisches Verkupfern erfolgt, wobei jene Teile, die nicht verkupfert werden sollen, mit einer Maske 18 („reversemask") abgedeckt werden, die nach dem Verkupfern entfernt wird. Das Ergebnis dieses„semi-additive plating" sind im Vergleich zu den Kupfer schichten 16, 17 dicke äußere Leiter schichten, nämlich eine strukturierte obere Leiterschicht 19 und eine untere Leiterschicht 20, wobei diese Leiterschichten mit Durchkontaktierungen 9d, 9g und 9s zu den Gate-, Drain- und Source-Kontakten der Komponente 1 einstückig sind. Die gesamte Dicke der äußeren Leiterschichten liegt beispielsweise im Bereich von 5 bis 70 m. Im vorliegenden Fall ist zufolge der großen Ausdehnung des Drain-Kontaktes die Durchkontaktierung 9d zu diesem Kontakt kaum als„Durchkontaktie- rung" zu erkennen, vielmehr liegt nur eine geringfügige Eintiefung der unteren Leiterschicht in einem Ausmaß von z.B. weniger als 2 m vor. Referring to Fig. 7, the next step is discussed in which both the bottom and top are electroplated, with those parts that are not to be copper coated covered with a mask 18 ("reverse-mask") The result of this "semi-additive plating" compared to the copper layers 16, 17 thick outer conductor layers, namely a structured upper conductor layer 19 and a lower conductor layer 20, wherein these conductor layers with vias 9d , 9g and 9s are integral with the gate, drain and source contacts of component 1. The total thickness of the outer conductor layers is for example in the range of 5 to 70 m. In the present case, due to the large extent of the drain contact, the via 9d is hardly recognizable as a "via" to this contact, but there is only a slight depression of the lower conductor layer to an extent of, for example, less than 2 m.
Nach dem Entfernen der Maske 18 liegt als Endergebnis die in Fig. 8 gezeigte Leiterplattenstruktur 21 vor, welche die eingebettete Komponente 1 enthält, die mit den Leiterschichten 19, 20 elektrisch verbunden ist, genauer gesagt sind Gate G, Source S und Drain D bzw. die zugehörigen Anschlüsse 8g, 8s und 8d des MOSFETs mit diesen entsprechend strukturierten Leiterschichten 19, 20 verbunden. Fig.9 zeigt als Beispiel eine weitere Ausführungsform einer Leiterplattenstruktur 22, die entsprechend dem oben beschriebenen Verfahren hergestellt ist und insgesamt vier Komponenten enthält, nämlich einen ersten MOSFET 23, z.B. einen„High Source FET", einen zweiten MOSFET 24, z.B. einen„Low Source FET", einen Ansteuerchip 25 sowie einen Kondensator 26, z.B. vom Typ„MultilayerCofiredCeramic". In Fig. 9 werden für vergleichbare Teile gleiche Bezugszeichen wie in den vorangehenden Figuren verwendet, wobei zusätzlich erläutert wird, dass der MOSFET 23 und der MOSFET 24 in gleicher Weise in die Leiterplattenstruktur 22 eingebettet und mit einer oberen bzw. unteren strukturierten Leiterschicht 19 bzw. 20 verbunden sind, wie zuvor in den Fig. 3 bis 8 gezeigt, wobei jedoch die Gate- und Source- Anschlüsse "unten" und die Drain- Anschlüsse "oben" liegen. After removal of the mask 18, the final result is the printed circuit board structure 21 shown in FIG. 8, which contains the embedded component 1, which is electrically connected to the conductor layers 19, 20; more specifically, gate G, source S and drain D or the associated connections 8g, 8s and 8d of the MOSFET are connected to these correspondingly structured conductor layers 19, 20. 9 shows by way of example a further embodiment of a printed circuit board structure 22, which is manufactured according to the method described above and contains a total of four components, namely a first MOSFET 23, eg a "high source FET", a second MOSFET 24, eg a "low Source FET ", a drive chip 25 and a capacitor 26, for example of the" Multilayer Cofired Ceramic "type. In Fig. 9, the same reference numerals are used for comparable parts as in the preceding figures, wherein it is additionally explained that the MOSFET 23 and the MOSFET 24 in embedded in the printed circuit board structure 22 and connected to upper and lower structured conductor layers 19 and 20, respectively, as previously shown in FIGS. 3 to 8, but with the gate and source terminals "down" and the drain Connections "above" are.
In Fig. 9 sind auch zwei Durchkontaktierungen 27, 28 zwischen der oberen und der unteren Leiterschicht 19, 20 ersichtlich, wobei eine Durchkontaktierung 28 eine Verbindung zwischen Source S der ersten MOSFET 23 und Drain D der zweiten MOSFET 24 herstellt. Bei dieser Ausführung sind die Durchkontaktierungen von der unteren Leiterschicht 20 zu den Drains der MOSFETS in drei bzw. fünf Durchkontaktierungen 9 aufgeteilt. Der Einfachheit halber sind in Fig. 9 sämtliche Durchkontaktierungen von den Leiterschichten 19, 20 zu Komponentenanschlüssen mit dem Bezugszeichen "9" versehen. FIG. 9 also shows two plated-through holes 27, 28 between the upper and lower conductor layers 19, 20, wherein a plated-through hole 28 establishes a connection between source S of the first MOSFET 23 and drain D of the second MOSFET 24. In this embodiment, the vias from the bottom conductor layer 20 to the drains of the MOSFETs are split into three and five vias 9, respectively. For the sake of simplicity, in FIG. 9 all plated-through holes of the conductor layers 19, 20 are provided with component reference numbers "9".
In Fig. 9 ist rechts von dem MOSFET 24 der Ansteuerchip 25 angeordnet und wieder rechts von diesem der Kondensator 26. In FIG. 9, the drive chip 25 is arranged to the right of the MOSFET 24, and to the right of this the capacitor 26.
Der Aufbau der Elektroden-Kontaktierung bei den MOSFETS 23 und 24 und dem Ansteuerchip 25 ist der gleiche wie in Fig. 16 bzw. Fig. 2 gezeigt, er besteht somit - von innen nach außen - aus einer Kontaktschicht, einer Kontakt-Adhäsionsschicht und einer Barriereschicht. Hingegen sind die beiden Anschlüsse des Kondensators 26 innen je mit einer Kontakt- Adhäsionsschicht 26-3 versehen, auf welcher eine Kontakt-Barriereschicht 26-4 folgt. Die Adhäsionsschichten 26-3 bestehen bevorzugt aus Chrom und die Barriereschichten 26-4 aus Nickel. Die in Fig. 9 gezeigte Leiterplattenstruktur 22 kann noch weitere, hier nicht dargestellte Komponenten enthalten, wie Leistungsdioden, Widerstände und Induktivitäten. The structure of the electrode contacting in the MOSFETs 23 and 24 and the drive chip 25 is the same as shown in Fig. 16 and Fig. 2, it thus consists - from the inside to the outside - of a contact layer, a contact adhesion layer and a barrier layer. On the other hand, the two terminals of the capacitor 26 are each internally provided with a contact adhesion layer 26-3 on which a contact barrier layer 26-4 follows. The adhesion layers 26-3 are preferably made of chromium and the barrier layers 26-4 of nickel. The circuit board structure 22 shown in FIG. 9 may contain further components, not shown here, such as power diodes, resistors and inductors.
Bei einer in dem Ausschnitt nach Fig. 9a dargestellten Ausführungsform sind zur Erhöhung der Stromtragfähigkeit nicht nur die Drain-Anschlüsse der MOSFETs 23, 24 sondern auch deren Source- Anschlüsse vollflächig kontaktiert, d.h. statt der drei Durchkontaktierungen 9 für die Source S des MOSFET 23 und der fünf Durchkontaktierungen 9 für die Source S des MOSFET 24 ist lediglich eine großflächige, mit 9' bezeichnete Durchkontaktierung ausgebildet. In an embodiment shown in the detail according to FIG. 9a, not only the drain terminals of the MOSFETs 23, 24 but also their source terminals are contacted over the whole area in order to increase the current carrying capacity, ie instead of the three plated-through holes 9 for the source S of the MOSFET 23 and the five vias 9 for the source S of the MOSFET 24, only a large, designated by 9 'via is formed.
Da nicht zuletzt dank der Erfindung die Dicke der Leiterplattenstruktur sehr gering gehalten werden kann, ist es auch leicht möglich, diese zumindest abschnittsweise flexibel zu gestaltet, wobei sich in diesem Fall als Material für die Isolierschicht beispielsweise Polyimid anbietet. Not least thanks to the invention, the thickness of the circuit board structure can be kept very low, it is also easily possible to make them at least partially flexible, in which case, for example, offers as a material for the insulating layer polyimide.

Claims

ANSPRÜCHE
1. Leiterplattenstruktur (21, 22) bestehend aus zumindest einer Isolierschicht (10), zumindest einer Leiterschicht (11, 12) und zumindest einer eingebetteten Komponente (1, 23 - 26) mit eine äußere Barriereschicht (4) besitzenden Kontaktpads (5), bei welcher zumindest zwei Leiterbahnen/ -schichten (19, 20) über Durchkontaktierungen (9; 9d, 9g, 9s) mit zumindest zwei Anschlüssen (8; 8d, 8g, 8s) verbunden sind, dadurch gekennzeichnet, dass jede Durchkontaktierung (9; 9d, 9g, 9s) von einer Leiterbahn/ -Schicht (11, 12) unmittelbar zu der Barriere-Kontaktschicht (4; 4d, 4g, 4s) des entsprechenden Anschlusses (8; 8d, 8g, 8s) der Komponente (1, 23 - 26) verläuft. 1. printed circuit board structure (21, 22) consisting of at least one insulating layer (10), at least one conductor layer (11, 12) and at least one embedded component (1, 23-26) having an outer barrier layer (4) possessing contact pads (5), in which at least two conductor tracks / layers (19, 20) are connected via plated-through holes (9; 9d, 9g, 9s) to at least two terminals (8; 8d, 8g, 8s), characterized in that each through-connection (9; 9d , 9g, 9s) from a track / layer (11, 12) directly to the barrier contact layer (4; 4d, 4g, 4s) of the corresponding terminal (8; 8d, 8g, 8s) of the component (1, 23). 26) runs.
2. Leiterplattenstruktur (21, 22) nach Anspruch 1, dadurch gekennzeichnet, dass das Material der Barriere-Kontaktschicht (4; 4d, 4g, 4s) aus der Gruppe Nickel, Nickel- Vanadium, Platin, Palladium und Kobalt gewählt ist. 2. printed circuit board structure (21, 22) according to claim 1, characterized in that the material of the barrier contact layer (4; 4d, 4g, 4s) from the group nickel, nickel vanadium, platinum, palladium and cobalt is selected.
3. Leiterplattenstruktur (21, 22) nach Anspruch 2, dadurch gekennzeichnet, dass das Material der Barriere-Kontaktschicht (4; 4d, 4g, 4s) Nickel ist. A circuit board structure (21, 22) according to claim 2, characterized in that the material of the barrier contact layer (4; 4d, 4g, 4s) is nickel.
4. Leiterplattenstruktur (21, 22) nach einem der Ansprüche 1 bis 4, dadurch gekennzeichnet, dass die Durchkontaktierung (9) aus Kupfer besteht. 4. printed circuit board structure (21, 22) according to one of claims 1 to 4, characterized in that the through-connection (9) consists of copper.
5. Leiterplattenstruktur (21, 22) nach einem der Ansprüche 1 bis 5, dadurch gekennzeichnet, dass unterhalb der Barriere-Kontaktschicht (4) eine Adhäsionsschicht (3) angeordnet ist. 5. printed circuit board structure (21, 22) according to one of claims 1 to 5, characterized in that below the barrier contact layer (4) an adhesion layer (3) is arranged.
6. Leiterplattenstruktur (21, 22) nach Anspruch 5, dadurch gekennzeichnet, dass die Adhäsionsschicht (3) aus der Gruppe Titan, Titan-Wolfram und Chrom ausgewählt ist. 6. printed circuit board structure (21, 22) according to claim 5, characterized in that the adhesion layer (3) from the group titanium, titanium-tungsten and chromium is selected.
7. Leiterplattenstruktur (21, 22) nach einem der Ansprüche 1 bis 6, dadurch gekennzeichnet, dass die Komponente (1, 23, 24) eine Leistungskomponente ist. 7. printed circuit board structure (21, 22) according to one of claims 1 to 6, characterized in that the component (1, 23, 24) is a power component.
8. Leiterplattenstruktur (21, 22) nach Anspruch 7, dadurch gekennzeichnet, dass die Leistungskomponente ein IGBT-Chip / MOSFET (1, 23, 24) ist. 8. printed circuit board structure (21, 22) according to claim 7, characterized in that the power component is an IGBT chip / MOSFET (1, 23, 24).
9. Leiterplattenstruktur (21, 22) nach Anspruch 7 oder 8, dadurch gekennzeichnet, dass die Komponente eine Leistungsdiode ist. 9. printed circuit board structure (21, 22) according to claim 7 or 8, characterized in that the component is a power diode.
10. Leiterplattenstruktur (21, 22) nach einem der Ansprüche 1 bis 9, dadurch gekennzeichnet, dass sie zumindest abschnittsweise flexibel ausgebildet ist. 10. printed circuit board structure (21, 22) according to one of claims 1 to 9, characterized in that it is formed at least partially flexible.
11. Verfahren zum Ankontaktieren einer in einer Leiterplattenstruktur eingebetteten Komponente (1, 23 - 26) an einen Leiterbahnabschnitt durch Herstellung von Durchkontaktierun- gen (9; 9d, 9g, 9s) von einer Leiterschicht zu Anschlüssen (8; 8d, 8g, 8s) der Komponente, dadurch gekennzeichnet, dass im Bereich der Anschlüsse (8; 8d, 8g, 8s) der Komponente (1, 23 - 26) in einer äußeren Leiterschicht (11, 12) zumindest eine Öffnung (13,14, 15) hergestellt wird, die bis zu einer Barriereschicht (4; 4d, 4g, 4s) eines Anschlusses reicht, und daraufhin zumindest eine Durchkontaktierung (9; 9d, 9g, 9s) von der Leiterbahn/- schicht (11, 12) unmittelbar zu der Barriereschicht (4; 4d, 4g, 4s) des entsprechenden Anschlusses (8; 8d, 8g, 8s) der Komponente (1, 23 - 26) hergestellt wird. 11. A method for contacting a component (1, 23-26) embedded in a printed circuit board structure to a printed conductor section by producing via holes (9, 9d, 9g, 9s) from one conductor layer to terminals (8, 8d, 8g, 8s) the component, characterized in that in the region of the terminals (8; 8d, 8g, 8s) of the component (1, 23 - 26) in an outer conductor layer (11, 12) at least one opening (13,14, 15) is produced which extends to a barrier layer (4; 4d, 4g, 4s) of a terminal, and thereupon at least one via (9; 9d, 9g, 9s) from the conductor track / layer (11, 12) directly to the barrier layer (4 4d, 4g, 4s) of the corresponding terminal (8; 8d, 8g, 8s) of the component (1, 23-26).
12. Verfahren nach Anspruch 11, dadurch gekennzeichnet, dass zur Bildung einer Kupferschicht (16, 17) an der Oberfläche und in den Öffnungen ein stromloses Verkupfern an zumindest einer Seite der Leiterplattenstruktur durchgeführt wird. 12. The method according to claim 11, characterized in that to form a copper layer (16, 17) on the surface and in the openings, an electroless copper plating is performed on at least one side of the printed circuit board structure.
13. Verfahren nach Anspruch 11 oder 12, dass die zumindest eine Öffnung (13, 14, 15) durch Laser-Schneiden hergestellt wird. 13. The method according to claim 11 or 12, that the at least one opening (13, 14, 15) is produced by laser cutting.
14. Verfahren nach einem der Ansprüche 11 bis 13, dadurch gekennzeichnet dass vor dem Herstellen der Durchkontaktierungen die zumindest eine Öffnung (13,14, 15) chemisch gereinigt wird. 14. The method according to any one of claims 11 to 13, characterized in that before the production of the plated-through holes, the at least one opening (13,14, 15) is chemically cleaned.
15. Verfahren nach Anspruch 14, dadurch gekennzeichnet, dass bei dem Schritt des chemischen Reinigens die Dicke der Barriereschicht (4; 4d, 4g, 4s) verringert wird. A method according to claim 14, characterized in that in the step of chemical cleaning the thickness of the barrier layer (4; 4d, 4g, 4s) is reduced.
16. Verfahren nach einem der Ansprüche 11 bis 15 dass nach dem stromlosen Verkupfern eine Maske (18) auf die zumindest eine Seite der Leiterplattenstruktur aufgebracht und darnach ein galvanisches Verkupfern zur Herstellung zumindest einer Leiterschicht (19, 20) und der Fertigstellung Durchkontaktierungen (9; 9d, 9g, 9s) sowie ein Entfernen der Maske erfolgt. 16. The method according to any one of claims 11 to 15 that after the electroless copper plating a mask (18) applied to the at least one side of the printed circuit board structure and then a galvanic copper plating for producing at least one conductor layer (19, 20) and the completion vias (9; 9d, 9g, 9s) and removal of the mask.
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US20190150288A1 (en) 2019-05-16

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