EP2960894B1 - Organic light emitting display for compensating for variations in electrical characteristics of driving element - Google Patents

Organic light emitting display for compensating for variations in electrical characteristics of driving element Download PDF

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Publication number
EP2960894B1
EP2960894B1 EP14195405.7A EP14195405A EP2960894B1 EP 2960894 B1 EP2960894 B1 EP 2960894B1 EP 14195405 A EP14195405 A EP 14195405A EP 2960894 B1 EP2960894 B1 EP 2960894B1
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Prior art keywords
sensing
voltage
current
adc
data
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German (de)
English (en)
French (fr)
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EP2960894A1 (en
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Taegung Kim
Junghyeon Kim
Jinhan Yoon
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LG Display Co Ltd
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LG Display Co Ltd
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    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/22—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources
    • G09G3/30—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels
    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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    • G09G3/32—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters using controlled light sources using electroluminescent panels semiconductive, e.g. using light-emitting diodes [LED]
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Definitions

  • This document relates to an organic light emitting display, and more particularly, to an organic light emitting display which is capable of compensating for variations in electrical characteristics of a driving element.
  • An active matrix-type organic light emitting display comprises a self-emissive organic light emitting diode (hereinafter, referred to as "OLED”), and offers advantages such as fast response speed, high light emission efficiency, high luminance, and wide viewing angle.
  • OLED self-emissive organic light emitting diode
  • An OLED which is a self-emissive element, comprises an anode, a cathode, and organic compound layers HIL, HTL, EML, ETL, and EIL formed between the anode and the cathode.
  • the organic compound layers comprise a hole injection layer HIL, a hole transport layer HTL, an emission layer EML, an electron transport layer ETL, and an electron injection layer EIL.
  • pixels each including an OLED are arranged in a matrix form, and the luminance of the pixels is controlled according to the grayscale of video data.
  • Each pixel comprises a driving element, i.e., driving TFT (thin film transistor), that controls the driving current flowing through the OLED in response to a voltage Vgs applied between its gate electrode and source electrode.
  • driving TFT thin film transistor
  • Electrical characteristics of the driving TFT such as threshold voltage, mobility, etc, may be deteriorated with the passage of driving time, causing variations from pixel to pixel.
  • An internal compensation method and an external compensation method are known to compensate for variations in electrical characteristics of a driving TFT.
  • variations in the threshold voltage of driving TFTs are automatically compensated for within a pixel circuit.
  • the configuration of the pixel circuit is very complicated because the driving current flowing through the OLED has to be determined regardless of the threshold voltage of the driving TFTs for the sake of internal compensation.
  • the internal compensation method is inappropriate to compensate for mobility variations between the driving TFTs.
  • a data driving circuit receives a sensed voltage from each pixel through a sensing line, converts the sensed voltage into a digital sensed value, and then transmits it to a timing controller.
  • the timing controller modulates digital video data based on the digital sensed value and compensates for variations in electrical characteristics of a driving TFT.
  • the driving TFT is a current element
  • its electrical characteristics are represented by the amount of current Ids flowing between a drain and a source in response to a given gate-source voltage Vgs.
  • the data driving circuit of the conventional external compensation method senses a voltage corresponding to the current Ids, rather than sensing the current Ids flowing through the driving TFT, in order to sense the electrical characteristics of the driving TFT.
  • the driving TFT is operated in a source follower manner, and then a voltage (driving TFT's source voltage) stored in the line capacitor (parasitic capacitor) of the sensing line is sensed by the data driving circuit.
  • the source voltage is sensed when the source electrode potential of the driving TFT DT operating in the source follower manner reaches a saturation state (i.e., the current Ids of the driving TFT DT becomes zero), in order to compensate for variations in the threshold voltage of the driving TFT.
  • a linear voltage is sensed before the source electrode potential of the driving TFT DT operating in the source follower manner reaches a saturation state, in order to compensate for variations in the mobility of the driving TFT.
  • WO 2014/174905 A1 describes a display device with a data line drive circuit and controls a drive current through a drive transistor with the help of a threshold voltage correction memory.
  • US 2013/0050292 A1 describes an organic light emitting diode display device in which a current of each pixel is sensed at high speed to compensate for luminance non-uniformity.
  • US 2014/0084932 A1 describes a system and methods for extraction of threshold and mobility parameters from a pixel circuit.
  • US 2004/0246019 A1 describes an inspection method for carrying out a performance test on a fabricated active matrix panel before an OLED is mounted.
  • the conventional external compensation method has the following problems.
  • An aspect of this document is to provide an organic light emitting display which offers shorter sensing time and higher sensing accuracy when sensing variations in electrical characteristics of a driving element.
  • An organic light emitting display according to claim 1 and an organic light emitting display according to claim 2 is provided.
  • the first level may be a voltage level corresponding to either a predetermined region of low grayscale current in the entire grayscale range or a predetermined region of high grayscale current in the entire grayscale range
  • the second level is a voltage level corresponding to the other one.
  • the timing controller may be configured to control the operation of the gate driving circuit to generate the sensing gate pulse in multiple pulses so that two or more of the ON pulse region of the sensing gate pulse are included in one line sensing ON time.
  • the organic light emitting display may further comprise a programmable voltage adjustment IC for adjusting an ADC reference voltage by which the input voltage range of the ADC is determined, wherein the timing controller is configured to control the operation of the programmable voltage adjustment IC based on the result of analysis of the digital sensed values to adjust the ADC reference voltage.
  • FIGS. 1 to 16 An exemplary embodiment of the present invention will be described with reference to FIGS. 1 to 16 .
  • FIG. 1 is a view showing an organic light emitting display according to an exemplary embodiment of the present invention.
  • FIG. 2 is a view showing the configuration of a pixel array formed on the display panel of FIG. 1 .
  • the organic light emitting display according to the exemplary embodiment of the present invention comprises a display panel 10, a timing controller 11, a data driving circuit 12, a gate driving circuit 13, and a memory 16.
  • a plurality of data lines 14A and sensing lines 14B and a plurality of gate lines 15 cross over each other on the display panel 10, and pixels P are arranged in a matrix formed at their crossings.
  • Each pixel P is connected to any one of the data lines 14A, any one of the sensing lines 14B, and any one of the gate lines 15.
  • Each pixel P is electrically connected to a data voltage supply line 14A to receive a data voltage form the data voltage supply line 14A and output a sensing signal through a sensing line 14B, in response to a gate pulse input through a gate line 15.
  • Each pixel P receives a high-potential driving voltage EVDD and a low-potential driving voltage EVSS from a power generator (not shown).
  • a pixel P of this invention may comprise an OLED, a driving TFT, first and second switching TFTs, and a storage capacitor, for the sake of external compensation.
  • the TFTs constituting the pixel P may be implemented as p-type or n-type.
  • a semiconductor layer of the TFTs constituting the pixel P may comprise amorphous silicon, polysilicon, or oxide.
  • Each pixel P may operate differently in a normal driving operation for displaying an image and in a sensing operation for obtaining a sensed value. Sensing may be per formed for a predetermined period of time before normal driving or for vertical blank periods during normal driving.
  • Normal driving may occur when the data driving circuit 12 and the gate driving circuit 13 operate normally under the control of the timing controller 11.
  • Sensing may occur when the data driving circuit 12 and the gate driving circuit 13 perform a sensing operation under the control of the timing controller 11.
  • An operation of deriving compensation data for variation compensation based on a sensing result and an operation of modulating digital video data using compensation data are carried out by the timing controller 11.
  • the data driving circuit 12 comprises at least one data driver IC (integrated circuit) SDIC.
  • the data driver IC SDIC comprises a plurality of digital-to-analog converters (hereinafter, DACs) connected to each data line 14A, a plurality of sensing units connected to each sensing line 14B, and an ADC (analog-to-digital converter) connected commonly to the output terminals of the sensing units.
  • DACs digital-to-analog converters
  • the DAC of the data driver IC SDIC converts digital video data RGB into a data voltage for image display and supplies it to the data lines 14A, in response to a data timing control signal DDC applied from the timing controller 11.
  • the DAC of the data driver IC SDIC generates a sensing data voltage and supplies it to the data lines 14A, in response to a data timing control signal DDC applied from the timing controller 11.
  • Each sensing unit of the data driver IC SDIC comprises a current integrator CI that performs an integration of a sensing signal from a pixel P input through a sensing line 14B, i.e., a source-drain current of the driving TFT, and a sampler SH for sampling and holding the output of the current integrator CI.
  • the ADC of the data driver IC SDIC sequentially digitizes the output of the samplers SH and transmits it to the timing controller 11.
  • the gate driving circuit 13 In the normal driving operation, the gate driving circuit 13 generates a gate pulse for image display based on a gate control signal GDC and then sequentially supplies it to the gate lines 15 in a line sequential manner L#1, L#2, .... In the sensing operation, the gate driving circuit 13 generates a sensing gate pulse based on the gate control signal GDC and then sequentially supplies it to the gate lines 15 in a line sequential manner L#1, L#2, ....
  • the sensing gate pulse may have a larger ON pulse region than the gate pulse for image display.
  • One (see FIG. 6 ) or multiple (see FIG. 7 ) ON pulse regions of the sensing gate pulse may be included within one line sensing ON time.
  • one line sensing ON time denotes the scan time taken to simultaneously sense the pixels of one pixel line L#1, L#2, ...
  • the timing controller 11 generates a data control signal DDC for controlling the operation timing of the data driving circuit 12 and a gate control signal GDC for controlling the operation timing of the gate driving circuit 13, based on timing signals such as a vertical synchronization signal Vsync, a horizontal synchronization signal Hsync, a dot clock signal DCLK, and a data enable signal DE.
  • the timing controller 11 identifies normal driving and sensing based on a predetermined reference signal (driving power enable signal, vertical synchronization signal, data enable signal, etc), and generates the data control signal DDC and the gate control signal GDC depending on each driving operation.
  • the timing controller 11 may generate additional control signals (RST, SAM, HOLD, etc of FIG. 3 ) required for sensing.
  • the timing controller 11 may transmit digital data corresponding to a sensing data voltage to the data driving circuit 12.
  • the timing controller 11 applies a digital sensed value SD transmitted from the data driving circuit 12 to a pre-stored compensation algorithm to derive a threshold voltage variation ⁇ Vth and a mobility variation ⁇ K, and then stores compensation data in a memory 16 to compensate for these variations.
  • the timing controller 11 modulates digital video data RGB for image display with reference to the compensation data stored in the memory 16 and then transmits it to the data driving circuit 12.
  • FIGS. 3 and 4 show a connection structure of a pixel P and a sensing unit to which a current sensing method of the present invention is applied and a sensing principle for the same.
  • FIGS. 3 and 4 are only an example for helping understanding of driving of the current sensing method.
  • a pixel structure using the current sensing method of this invention and the timing for driving it can be altered in various ways.
  • a pixel PIX of the present invention may comprise an OLED, a driving TFT (thin film transistor) DT, a storage capacitor Cst, a first switching TFT ST1, and a second switching TFT ST2.
  • the OLED comprises an anode connected to a second node N2, a cathode connected to the input terminal of a low-potential driving voltage EVSS, and an organic compound layer located between the anode and the cathode.
  • the driving TFT DT controls the amount of current going into the OLED according to a gate-source voltage Vgs.
  • the driving TFT DT comprises a gate electrode connected to a first node N1, a drain electrode connected to the input terminal of a high-potential driving voltage EVDD, and a source electrode connected to the second node N2.
  • the storage capacitor Cst is connected between the first node N1 and the second node N2.
  • the first switching TFT ST1 applies a data voltage Vdata on a data voltage supply line 14A to the first node N1 in response to a gate pulse SCAN.
  • the first switching TFT ST1 comprises a gate electrode connected to a gate line 15, a drain electrode connected to the data voltage supply line 14A, and a source electrode connected to the first node N1.
  • the second switching TFT ST2 switches the flow of current between the second node N2 and a sensing line 14B in response to a gate pulse SCAN.
  • the second switching TFT ST2 comprises a gate electrode connected to a second gate line 15D, a drain electrode connected to the sensing line 14B, and a source electrode connected to the second node N2.
  • a current integrator CI included in a sensing unit of this invention comprises an amplifier AMP comprising an inverting input terminal (-) connected to the sensing line 14B and receiving the source-drain current Ids of the driving TFT from the sensing line 14B, an non-inverting input terminal (+) receiving a reference voltage Vpre, and an output terminal for outputting an integrated value Vsen, an integration capacitor Cfb connected between the inverting input terminal (-) and output terminal of the amplifier AMP, and a first switch SW1 connected to both ends of the integration capacitor Cfb.
  • a sampler SH included in the sensing unit of this invention comprises a second switch SW2 that is switched on in response to a sampling signal SAM, a third switch SW3 that is switched on in response to a holding signal HOLD, and a holding capacitor Ch whose one end is connected between the second switch SW2 and the third switch SW3 and whose the other end is connected to a ground voltage source GND.
  • FIG. 4 depicts the waveform of one sensing operation for each of the pixels arranged on the same line within one line sensing ON time defined by the ON pulse region of a sensing gate pulse SCAN.
  • the sensing operation is performed in several periods including an initialization period Tinit, a sensing period Tsen, and a sampling period Tsam.
  • the amplifier AMP operates as a unit gain buffer with a gain of 1 by the turn-on of the first switch SW1.
  • the input terminals (+,-) and output terminal of the amplifier AMP, the sensing line 14B, and the second node N2 are all initialized to the reference voltage Vpre.
  • a sensing data voltage Vdata-SEN is applied to the first node N1 through the DAC of the data driver IC SDIC. Accordingly, a source-drain current Ids corresponding to a potential difference ⁇ (Vdata-SEN)-Vpre ⁇ between the first node N1 and the second node N2 is stabilized as it flows to the driving TFT DT. However, since the amplifier AMP continues to act as the unit gain buffer during the initialization period, the potential of the output terminal is maintained at the reference voltage Vpre.
  • the amplifier AMP operates as the current integrator CI by the turn-off of the first switch SW1 to perform an integration of the source-drain current Ids flowing through the driving TFT DT.
  • the potential difference between both ends of the integration capacitor Cfb increases due the current Ids entering the inverting input terminal (-) of the amplifier AMP as the sensing time passes, i.e., the value of stored current Ids increases.
  • the inverting input terminal (-) and the non-inverting input terminal (+) are shorted through a virtual ground due to the nature of the amplifier AMP, and the potential difference between the inverting input terminal (-) and the non-inverting input terminal (+) is zero.
  • the potential of the inverting input terminal (-) is maintained at the reference voltage Vpre in the sensing period Tsen, regardless of whether the potential difference across the integration capacitor Cfb has increased or not. Instead, the output terminal potential of the amplifier AMP decreases in response to the potential difference between both ends of the integration capacitor Cfb.
  • the current Ids entering through the sensing line 14B in the sensing period 2 is converted to an integrated value Vsen, which is a voltage value, through the integration capacitor Cfb.
  • the falling slope of the output Vout of the current integrator CI increases as the amount of current Ids entering through the sensing line 14B becomes larger. Therefore, the larger the amount of current Ids, the smaller the integrated value Vsen.
  • the integrated value Vsen passes through the second switch SW2 and is stored in the holding capacitor Ch.
  • the integrated value Vsen stored in the holding capacitor Ch passes through the third switch SW3 and is input into the ADC.
  • the integrated value Vsen is converted into a digital sensed value SD by the ADC and then transmitted to the timing controller 11.
  • the digital sensed value SD is used for the timing controller 11 to derive a threshold voltage variation ⁇ Vth of the driving TFT and a mobility variation ⁇ K of the driving TFT.
  • the timing controller 11 stores the capacitance of the integration capacitor Cfb, the reference voltage Vpre, and the sensing time Tsen are pre-stored in digital code.
  • the timing controller 11 applies the source-drain current Ids flowing through the driving TFT DT to a compensation algorithm to derive variations (a threshold voltage variation ⁇ Vth and a mobility variation ⁇ K) and compensation data (Vth+ ⁇ Vth and K+ ⁇ K).
  • the compensation algorithm may be implemented as a look-up table or a calculational logic.
  • the capacitance of the integration capacitor Cfb included in the current integrator CI of this invention is only one-several hundredths of the parasitic capacitance existing across the sensing line.
  • the current sensing method of this invention can drastically reduce the time taken to draw enough current Ids to meet the integrated value Vsen with which sensing is enabled, as compared to a conventional voltage sensing method.
  • the conventional voltage sensing method it takes quite a long time to sense a threshold voltage because the source voltage of the driving TFT is sampled as a sensed voltage after it is saturated; whereas, in the current sensing method, it takes much less time to sense a threshold voltage and mobility because an integration of the source-drain current of the driving TFT and sampling of the integration value can be performed within a short time by means of current sensing.
  • the integration capacitor Cfb included in the current integrator CI of this invention is able to obtain an accurate sensed value because its stored values do not change with display load but can be easily calibrated, unlike the parasitic capacitor of the sensing line.
  • the current sensing method of this invention has advantages over the conventional voltage sensing method because it is capable of low current sensing and high-speed sensing. For this reason, the current sensing method of this invention allows performing sensing on each pixel multiple times within one line sensing ON time in order to improve sensing performance.
  • FIGS. 5 and 6 show one driving waveform of a multi-time current sensing method proposed in the present invention to improve sensing performance and the driving procedure of this device.
  • FIG. 7 shows another driving waveform of the multi-time sensing method proposed in the present invention.
  • FIGS. 5 to 7 illustrate the multi-time current sensing of this invention by taking an example where current sensing is performed twice, the technical spirit of the present invention is also applicable when current sensing is performed three times or more.
  • sensing and sampling can be performed on the same pixel twice within one line sensing ON time corresponding to 1 ON pulse region of a sensing gate pulse SCAN.
  • the timing controller 11 may control the operations of the driving circuits 12 and 13 so that one line sensing ON time comprises a first sensing and sampling period S&S1 for performing an integration of a first source-drain current Ids1 caused by a sensing data voltage VData-SEN of a first level LV1 and a second sensing and sampling period S&S2 for performing an integration of a second source-drain current Ids2 caused by a sensing data voltage VData-SEN of a second level LV2.
  • the timing controller 11 may place initialization periods Tinit prior to the first and second sensing & sampling periods S&S1 and S&S2, respectively.
  • the sensing data voltages VData-SEN of the first level LV1 and second level LV2 may be the same but preferably differ in order to increase sensing performance.
  • the first level LV1 corresponds to a predetermined region of low grayscale current Ids1 in the entire grayscale range and the second level LV2 corresponds to a predetermined region of high grayscale current Ids2 in the entire grayscale range, or vice versa. That is, the first level LV1 may be a voltage level corresponding to either a predetermined region of low grayscale current Ids1 in the entire grayscale range or a predetermined region of high grayscale current Ids2 in the entire grayscale range, and the second level LV2 may be a voltage level corresponding to the other one.
  • the same operations as in the initialization period Tinit of FIG. 4 that is, an initialization operation and a source-drain current stabilization operation are firstly performed.
  • the same operations as in the sensing period Tsen and sampling period Tsam of FIG. 4 are performed; the first source-drain current Ids1 is sensed and firstly integrated, a first integrated value Vsen1 is sampled and firstly analog-to-digital converted, and then a first digital sensed value is stored in an internal latch.
  • the same operations as in the initialization period Tinit of FIG. 4 that is, an initialization operation and a source-drain current stabilization operation are secondly performed.
  • the same operations as in the sensing period Tsen and sampling period Tsam of FIG. 4 are performed; the second source-drain current Ids2 is sensed and secondly integrated, a second integrated value Vsen1 is sampled and secondly analog-to-digital converted, and then a second digital sensed value is stored in an internal latch.
  • the sensing periods Tsen included in the first and second sensing & sampling periods S&S1 and S&S2, respectively, are equal in length.
  • the timing controller 11 calculates the first and second source-drain currents Ids1 and Ids2 based on the first and second digital sensed values, and derives variations ⁇ Vth and ⁇ K by using a calaculational logic or look-up table.
  • the timing controller 11 calculates first and second current deviations by comparing the calculated threshold voltage Vth and mobility K with pre-stored reference values, and derives a threshold variation ⁇ Vth and a mobility variation ⁇ K by using the first and second current variations as read addresses. It is commonly known that the source-drain current of the driving TFT is affected much by changes in threshold voltage changes in a low grayscale region and by changes in mobility in a high grayscale region. Accordingly, as shown in FIG.
  • the timing controller 11 is able to derive the threshold voltage variation Vth based on the first source-drain current Idsd1, which is the higher of the two, and the mobility variation ⁇ K based on the second source-drain current Ids2, which is the lower of the two.
  • the timing controller 11 may control the operation of the gate driving circuit 13 to generate the sensing gate pulse SCAN in multiple pulses so that two or more of the ON pulse region of the gate sensing pulse SCAN are included in one line sensing ON time.
  • the stabilization condition may comprise gate delay, data charging delay, etc.
  • FIG. 8 shows a flow of compensation while the power is on.
  • FIG. 9 shows a flow of compensation during a real-time driving operation.
  • FIGS. 10A and 10B show a predetermined initial non-display period, active periods, and vertical blank periods while the power is on.
  • the flow of compensation of FIG. 8 involves a sensing operation performed on all pixels during a predetermined initial non-display period X1 preceding a normal driving operation.
  • the flow of compensation of FIG. 9 involves a sensing operation performed on one pixel line in vertical blank periods BP of the normal driving operation.
  • the initial non-display period X1 may be defined by a non-display period that lasts for several tens or hundreds of frames after the point of application of a driving power enable signal PON.
  • the vertical blank periods BP may be defined by non-display periods between active periods AP during which an image is displayed. No data enable signal DE is generated in the initial non-display period X1 and the vertical blank periods BP, and accordingly no image display data voltage is supplied to the pixels in the vertical blank periods BP.
  • the flow of compensation during the initial non-display period X1 will be schematically explained again.
  • the threshold voltage Vth and mobility K stored in the previous compensation period are read out from the memory when the power is on.
  • the aforementioned multi-time current sensing method is applied to each pixel line in a line sequential manner to obtain multiple digital sensed values, and the current threshold voltage Vth and mobility K are derived based on these digital sensed values.
  • the derived current threshold voltage Vth and mobility K are compared with the threshold voltage Vth and mobility K input from the memory to derive a threshold variation ⁇ Vth and a mobility variation ⁇ K, and then compensation data Vth+AVth and K+ ⁇ K for compensating the variations is stored in the memory.
  • the flow of compensation for each pixel line during the vertical blank periods BP of the normal driving operation will be schematically explained again.
  • the threshold voltage Vth and mobility K stored in the previous compensation period are read out from the memory in the vertical blank periods BP.
  • the aforementioned multi-time current sensing method is applied to each pixel line in a line sequential manner to obtain multiple digital sensed values, and the current threshold voltage Vth and mobility K are derived based on these digital sensed values.
  • the derived current threshold voltage Vth and mobility K are compared with the threshold voltage Vth(n-1) and mobility K(n-1) input from the memory to derive a threshold variation ⁇ Vth and a mobility variation ⁇ K, and then compensation data Vth+ ⁇ Vth and K+ ⁇ K for compensating the variations is stored in the memory.
  • FIG. 11 shows ADC over-range observed in the multi-time current sensing method of the present invention.
  • An ADC is a special encoder which converts an analog signal into data in the form of a digital signal.
  • the ADC has a fixed input voltage range, i.e., fixed sensing range.
  • the voltage range of the ADC may differ depending on the resolution of AD conversion, it is usually set to Evref (ADC reference voltage) to Evref+3V.
  • the resolution of AD conversion is the number of bits that are used to convert an analog input voltage into a digital value. If an analog signal input into the ADC is out of the input range of the ADC, underflow occurs where the ADC's output is smaller than the smallest value of the input voltage range, or overflow occurs where the ADC's output is larger than the largest value of the input voltage range.
  • different analog integrated values Vsen are generated by performing sensing on each pixel at least twice according to the multi-time current sensing method.
  • a first integrated value Vsen1 corresponding to a first current Ids1 is 4V and a second integrated value corresponding to a second current Ids2, larger than the first current Ids1, is 1.5V.
  • the second integrated value Vsen2 of 1.5V is out of the input range (2V to 5V) of the ADC and thus underflows because it is smaller than the smallest value 2V of the input voltage range of 2V to 5V.
  • FIG. 12 shows one solution to prevent ADC over-range.
  • the first integrated value Vsen1 will underflow more likely in the first sensing & sampling period S&S1, in which the falling slope of the output Vout of the current integrator CI is larger, than in the second sensing & sampling period S&S2, in which the falling slope of the output Vout of the current integrator CI is smaller.
  • the first integrated value Vsen1 can be adjusted upward from 2V to 3.5V for correction to satisfy the input voltage range (2V to 5V) of the ADC by making the sensing period Tsen1 of the first sensing & sampling period S&S1 shorter than the sensing period Tsen2 of the second sensing & sampling period S&S2.
  • FIGS. 13 to 15 show other solutions to prevent ADC over-range.
  • the organic light emitting display of this invention may further comprise a capacitance controller 22 for adjusting the capacitance of the integration capacitor Cfb included in the current integrator CI under the control of the timing controller 11.
  • the integration capacitor Cfb comprises a plurality of capacitors Cfb1, Cfb2, and Cfb2 connected in parallel to the inverting input terminal (-) of the amplifier AMP.
  • the other end of each of the capacitors Cfb1, Cfb2, and Cfb2 may be connected to the output terminal of the amplifier AMP through different capacitance adjustment switches S1, S2, and S3.
  • the coupling capacitance of the integration capacitor Cfb is determined depending on the number of turned-on capacitance adjustment switches S1, S2, and S3.
  • the timing controller 11 analyzes digital sensed values SD, and controls the operation of the capacitance controller 22 according to the ratio of digital sensed values SD equal to the smallest and largest values from the ADC among all the digital sensed values SD to generate a proper switching control signal.
  • the capacitance adjustment switches S1, S2, and S3 are turned on/off in response to the switching control signal from the capacitance controller 22.
  • the larger the coupling capacitance of the integration capacitor Cfb the gentler the falling slope of the output Vout of the current integrator CI.
  • the smaller the coupling capacitance of the integration capacitor Cfb the steeper the falling slope of the output Vout of the current integrator CI.
  • the timing controller 11 controls the number of capacitance adjustment switches S1, S2, and S3 turned on by the capacitance controller 22 to increase the coupling capacitance of the integration capacitor Cfb if underflow occurs where the ADC's output is smaller than the smallest value of the input voltage range and on the contrary decrease the coupling capacitance of the integration capacitor Cfb if overflow occurs where the ADC's output is larger than the largest value of the input voltage range.
  • FIG. 14 depicts an example of preventing ADC over-range by controlling the coupling capacitance of the integration capacitor Cfb.
  • the second integrated value Vsen2 will overflow more likely in the second sensing & sampling period S&S2, in which the falling slope of the output Vout of the current integrator CI is larger, than in the first sensing & sampling period S&S1, in which the falling slope of the output Vout of the current integrator CI is smaller.
  • the second integrated value Vsen2 can be adjusted upward from 2V to 4V for correction to satisfy the input voltage range (2V to 5V) of the ADC by increasing the coupling capacitance 3pF of the integration capacitor Cfb operating during the second sensing & sampling period by two times the coupling capacitance 1.5pF of the integration capacitor Cfb operating during the first sensing & sampling period.
  • the organic light emitting display of this invention may further comprise a programmable voltage adjustment IC 24 for adjusting ADC reference voltage Evref under the control of the timing controller 11.
  • the timing controller 11 analyzes digital sensed values SD, and controls the operation of the programmable voltage adjustment IC 24 according to the percentage of digital sensed values SD equal to the smallest and largest values from the ADC to adjust the ADC reference voltage Evref.
  • FIG. 15 depicts an example of preventing ADC over-range by adjusting ADC reference voltage Evref.
  • the second integrated value Vsen2 will underflow more likely in the second sensing & sampling period S&S2, in which the falling slope of the output Vout of the current integrator CI is larger, than in the first sensing & sampling period S&S1, in which the falling slope of the output Vout of the current integrator CI is smaller.
  • the ADC reference voltage Evref used to digitize the first integration value Vsen1 of 4V is maintained at the original level of 2V, and the ADC reference voltage Evref used to digitize the second integrated value Vsen2 of 2V is adjusted downward from the original level of 2V to 0V. By this downward adjustment, the second integrated value Vsen2 will be sufficient to satisfy the input voltage range (0V to 3V) of the ADC.
  • the present invention can greatly reduce the sensing time required to sense variations in electrical characteristics of a driving element by implementing low-current sensing and high-speed sensing by a current sensing method using a current integrator. Moreover, the present invention can greatly increase sensing accuracy by performing multi-time sensing on each pixel within one line sensing ON time.
EP14195405.7A 2014-06-26 2014-11-28 Organic light emitting display for compensating for variations in electrical characteristics of driving element Active EP2960894B1 (en)

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