EP2847787A1 - Procédé à deux niveaux pour assembler un semi-conducteur sur un substrat avec un matériau de l'iaison à base d'argent - Google Patents

Procédé à deux niveaux pour assembler un semi-conducteur sur un substrat avec un matériau de l'iaison à base d'argent

Info

Publication number
EP2847787A1
EP2847787A1 EP13715652.7A EP13715652A EP2847787A1 EP 2847787 A1 EP2847787 A1 EP 2847787A1 EP 13715652 A EP13715652 A EP 13715652A EP 2847787 A1 EP2847787 A1 EP 2847787A1
Authority
EP
European Patent Office
Prior art keywords
layer
sintered
paste
semiconductor
substrate
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Withdrawn
Application number
EP13715652.7A
Other languages
German (de)
English (en)
Inventor
Christiane FRUEH
Michael Guenther
Thomas HERBOTH
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Robert Bosch GmbH
Original Assignee
Robert Bosch GmbH
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Robert Bosch GmbH filed Critical Robert Bosch GmbH
Publication of EP2847787A1 publication Critical patent/EP2847787A1/fr
Withdrawn legal-status Critical Current

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    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20104—Temperature range 100 C=<T<150 C, 373.15 K =< T < 423.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20105—Temperature range 150 C=<T<200 C, 423.15 K =< T < 473.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20106—Temperature range 200 C=<T<250 C, 473.15 K =<T < 523.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20107—Temperature range 250 C=<T<300 C, 523.15K =<T< 573.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20108—Temperature range 300 C=<T<350 C, 573.15K =<T< 623.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20109—Temperature range 350 C=<T<400 C, 623.15K =<T< 673.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/2011—Temperature range 400 C=<T<450 C, 673.15K =<T< 723.15K
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
    • H01L2924/20—Parameters
    • H01L2924/201—Temperature ranges
    • H01L2924/20111—Temperature range 450 C=<T<500 C, 723.15K =<T< 773.15K

Definitions

  • the invention relates to a method for joining a semiconductor to a substrate.
  • soldering The standard method for joining joints in electronics is soldering.
  • high-temperature-stable solders that can be used up to 240 ° C are lead-based and can no longer be used due to the toxicity of lead in the future.
  • Lead-free solders are tin-based.
  • the operating temperature range at about 150 ° C is limited upwards.
  • An alternative for solder joints, in particular for the use of electronic connection technology in the high temperature range above 150 ° C represent sintered bonds on the basis of silver.
  • an advantage of these compounds is the high thermal shock resistance compared to solders.
  • the mentioned silver-based sintered compounds are produced by compressing a paste with silver-based microparticles or nanoparticles, whereby the individual particles assemble to form a mechanically stable sintered layer and a stable mechanical bond between the two adjacent to the sintered layer Components, the substrate and the semiconductor device generated.
  • silver paste is applied to a substrate with a metal surface.
  • a semiconductor in particular a power diode or the like, is applied to the wet layer, with subsequent drying and removal of the solvent at typically temperatures below 200 ° C.
  • An alternative variant consists in loading a semiconductor onto the dried layer and producing it the sintered compound under pressure with an increased pressure.
  • the basic idea is thus to produce a first sintered layer under high pressure and / or high temperature on the substrate and subsequently a further classical sintering process, by means of which a further layer with application of the semiconductor to the first sintered layer is applied, wherein both sintered layers connect to a bonding layer between the semiconductor and substrate. Due to the high self-diffusion of micro- and nanocrystalline silver layers, the two separately produced sintered layers combine to form a dense connection layer, wherein an interface failure due to the diffusion processes between the two sinter layers does not occur.
  • the paste layer is a layer of a sintering paste or suspension applied, for example, by screen printing or mask printing, which can be sintered under pressure and temperature to form a solid sintered layer.
  • the sintering paste or suspension is preferably a sintering paste or suspension comprising silver particles for producing an electrically conductive and temperature-conductive silver-based sintered layer.
  • the first sintered layer is applied without the semiconductor, sintering can take place at significantly higher pressures and higher temperatures than would be possible with an applied semiconductor since, as described above, there is a risk that the semiconductor will be destroyed if the pressures are too high Temperatures significantly above, for example, 300 ° C, the semiconductor could lose its electronic functionality. Since the first sintered layer is formed without the semiconductor, this can be done at significantly higher pressures and temperatures, thereby creating a high strength bond between the first sintered layer and the substrate, thereby overcoming the potential for interfacial failure at the interface with the substrate.
  • the paste layer prior to heating and compressing the first and / or the second paste layer, is dried at a temperature of up to 200 ° C.
  • an open drying of the paste layer can be carried out.
  • the heating and compression of the first paste layer occurs at a higher pressure and / or higher temperature than heating and compressing the second paste layer.
  • the core of the invention is thus a two-stage sintering process, wherein in the first stage, a sintered layer with low porosity and high mechanical strength and thermomechanical change resistance is produced by a sintered paste layer is applied to a substrate, for example by mask printing or screen printing.
  • a drying step for expelling solvents in particular at temperatures below 200 ° C., in particular an open drying of the sintered paste layer, may be carried out, in which case a sintering of the paste layer to a first sintered layer is carried out with application of temperature and pressure in order to form a mechanically stable connection to get between sintered layer and substrate.
  • the semiconductor is connected via a second sintered layer.
  • a sintered paste layer is applied to the first sintered layer, for example via mask printing or screen printing, and the semiconductor is then applied to the second sintered paste layer with a subsequent sintering of the paste layer to form a second sintered layer under temperature and pressure to produce a mechanically stable electrically and thermally conductive Connection between the first sintered layer and the second sintered layer and between the second sintered layer and the semiconductor component to be connected.
  • the sintering of the second paste layer to the second sintered layer while the temperature and pressure range is chosen so that the semiconductor device is not damaged.
  • a drying step for expelling solvents in particular at temperatures below 200 ° C can be performed.
  • the heating and compression of the first paste layer may be carried out at a temperature in the range of 200 ° C up to 600 ° C and / or at a pressure in the range of 5 MPa up to 120 MPa.
  • the duration of the temperature and / or pressure in the sintering of the first paste layer to the first sintered layer may be in the range of 10 seconds to 60 minutes.
  • the heating and compression of the second paste layer may be carried out at a temperature of 150 ° C up to 400 ° C and / or at a pressure of 5 MPa up to 40 MPa, especially for a period of 10 seconds to 60 minutes. It should be noted that the heating and compression of the second paste layer to the second sintered layer with the assembled semiconductor device takes place in a pressure and temperature range in which damage to the semiconductor device can be excluded.
  • the particular advantage of the invention is that in the production of the first sintered layer no consideration and compliance with maximum pressurization or temperature due to an applied semiconductor device must be considered, since only a first sintered layer with low porosity and high mechanical quality must be generated on the substrate ,
  • the maximum stresses occurring in the connecting layer are displaced from the edge region of the connection sintered layer to the substrate in the middle region of the sintered layers and a high-strength connection of sintered layer to substrate is produced by a high temperature and / or pressure in the first sintering step. whereby a failure of the sintered layer in the boundary region of sintered layer to substrate can be excluded.
  • the weak point of the sintered layer compound dominating in the prior art has been eliminated.
  • the first sintered layer has a lower porosity than the second sintered layer.
  • a paste layer of a sintering paste to the lower sintered layer and then heating and compressing the paste layer, more than two sintered layers can be formed, with the semiconductor applied to the uppermost paste layer and then heating and compressing the uppermost paste layer to the uppermost sintered layer.
  • three sintered layers can be produced, wherein the middle sintered layer can be structured. Layers of different thicknesses, porosities and specific compositions and / or different lateral dimensions can be produced.
  • Substrate and semiconductor of more than two printed sintered paste layers or sintered layers to produce, in particular comprising three sintered layers, wherein one or more sintered layers may be structured and wherein on the top layer of the sintering paste of the semiconductor is applied.
  • the sintering pastes of the various paste layers may have different compositions, in particular different additives.
  • one or more sintered layers may be designed such that the sintered layer has a higher surface coverage density of the sintering elements in the middle of the contact surface, wherein at the edge of the contact surface, the surface occupation density of the sintering elements may be lower than in the middle, whereby the reliability of the sintered connection in the edge region further increased. Due to the high surface occupation density of the sintered elements in the middle of the contact surface, good thermal and electrical conductivity in turn is ensured in the regions in which a high temperature development typically occurs during operation of the semiconductor component.
  • the surface occupation density of the sintered elements on the substrate may also be designed in such a way that from the center region of the contact surface to the edge region the surface occupation density is increased in the direction of the edge region, in particular to strengthen the edge region of the sintered connection and to counteract cracking. It is thus possible, by means of a specific specification of the particle distribution within the applied sintered paste layer, to specify different porosities and structural properties within each sintered layer.
  • FIG. 1 The application of a first layer on the substrate;
  • FIG. 2 The application of a second layer of a sintering paste to the first sintered layer and the placement of a semiconductor on the second paste layer to produce the connection of the semiconductor to the substrate.
  • FIG. 1 The application of a first layer on the substrate;
  • FIG. 2 The application of a second layer of a sintering paste to the first sintered layer and the placement of a semiconductor on the second paste layer to produce the connection of the semiconductor to the substrate.
  • FIG. 1 shows a substrate 10.
  • the substrate 10 may be a metal substrate, in particular a copper substrate or a metal-coated substrate. This substrate may in particular have a precious metal surface, for example by a nickel-gold metallization.
  • a first layer of a silver paste 1 is applied by mask printing or screen printing. Subsequently, an open drying of the silver paste layer 1 to drive off the solvent. This open drying takes place at temperatures below 200 ° C.
  • the first sintered layer 1 Upon application of the paste layer 1 at a pressure in the range of 5 to 120 MPa and at a temperature of 200 ° C to 600 ° C for a period of 10 seconds to 60 minutes, the first sintered layer 1 is produced.
  • the pressing tool 30 is used to compress and sinter the layer.
  • the pressurization of the sintered paste layer 1 in the sintering to the first sintered layer 1 is characterized by the arrows 40. Due to the very high pressure and temperature of the first layer 1, a stable connection between the sinter layer 1 and substrate 10 is generated.
  • the sintering paste consists of micro- and / or nanoparticles with the main component silver.
  • FIG. 2 shows the further step of producing the compound of the semiconductor 20 with the substrate 10 via the sintered layers 1 and 2.
  • a silver paste is produced on the first sintered layer 1 by mask printing or screen printing to produce a second layer 2 applied.
  • the loading of the semiconductor 20 may be, for example, a power transistor, a power diode or another power device.
  • the semiconductor 20 may be a MOSFET, an IGBT, a JFET, a BJT, a switchable thyristor, or a similar device, or may comprise such a device.
  • sintering of the second paste layer to a second sintered layer 2 Prior to sintering the second paste layer to a second sintered layer 2, drying of the second layer to drive off the solvent can take place. Subsequently, sintering of the second paste layer to the second sintered layer 2 is carried out under pressure and temperature for a period of 10 seconds to 60 minutes as required, wherein the pressure and temperature is chosen so that the semiconductor 20 is not damaged.
  • a pressure range can be provided here a pressure of up to 40 MPa and a temperature in the range of 150 ° C up to 400 ° C, depending on the compatibility of the semiconductor 20.
  • the sintering of the second sintered layer 2 takes place at the same or lower pressure and / or at the same or lower temperature than the sintering of the first sintered layer 1, so that the first and the second sintered layer may have different grain sizes due to the grain growth under the influence of temperature.
  • the semiconductor 20 is then connected in a second step, as explained with reference to Figure 2, via a second sintered layer 2 with the first sintered layer 1 and thus added to the substrate 10. Due to the very high pressure and the very high temperature in the sintering process for producing the first sintered layer 1, the adhesion strength of the first sintered layer 1 to the substrate 10 is increased by increasing the effective contact area between the silver particles of the first sintered layer 1 and the surface of the substrate 10 clearly increased. Due to the high self-diffusion of the microcrystalline or nanocrystalline sintered layers 1, 2 based on silver, an interface failure between the two sintered layers 1, 2 is excluded and a reliable connection between the two sintered layers 1, 2 results for the connection of the semiconductor 20 to the substrate 10.
  • the semiconductor components produced by the method according to the invention, d. H. the semiconductor devices in which the semiconductor 20 has been added to the substrate 10 with the multi-stage method according to the invention is particularly suitable for use in high-temperature-loaded, high-current-load or temperature-cycled components, wherein a variety of electronic and power electronic components can be added to a substrate. It is also possible to join large-area connections of semiconductors 20 onto a substrate 10, in particular for heat dissipation, when a substrate 10 is arranged on a heat dissipation sheet.

Landscapes

  • Engineering & Computer Science (AREA)
  • Computer Hardware Design (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Power Engineering (AREA)
  • Manufacturing & Machinery (AREA)
  • Die Bonding (AREA)

Abstract

L'invention concerne un procédé pour assembler un semi-conducteur (20) sur un substrat (10), qui comprend les étapes suivantes : •. appliquer une première couche (1) de pâte de frittage sur le substrat; •.chauffer et comprimer la première couche de pâte en une première couche frittée; •.appliquer une deuxième couche (2) de pâte de frittage sur la première couche frittée et disposer un semi-conducteur (20) sur ladite deuxième couche de pâte; •.chauffer et comprimer la deuxième couche de pâte (2) en une deuxième couche frittée. L'invention concerne en outre un composant semi-conducteur produit au moyen dudit procédé.
EP13715652.7A 2012-05-08 2013-04-02 Procédé à deux niveaux pour assembler un semi-conducteur sur un substrat avec un matériau de l'iaison à base d'argent Withdrawn EP2847787A1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE201210207652 DE102012207652A1 (de) 2012-05-08 2012-05-08 Zweistufiges Verfahren zum Fügen eines Halbleiters auf ein Substrat mit Verbindungsmaterial auf Silberbasis
PCT/EP2013/056951 WO2013167321A1 (fr) 2012-05-08 2013-04-02 Procédé à deux niveaux pour assembler un semi-conducteur sur un substrat avec un matériau de l'iaison à base d'argent

Publications (1)

Publication Number Publication Date
EP2847787A1 true EP2847787A1 (fr) 2015-03-18

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US (1) US20150123263A1 (fr)
EP (1) EP2847787A1 (fr)
DE (1) DE102012207652A1 (fr)
WO (1) WO2013167321A1 (fr)

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DE102014104272A1 (de) 2014-03-26 2015-10-01 Heraeus Deutschland GmbH & Co. KG Träger und Clip jeweils für ein Halbleiterelement, Verfahren zur Herstellung, Verwendung und Sinterpaste
DE102014209690B4 (de) * 2014-05-21 2020-02-20 Robert Bosch Gmbh Kommutierungszelle
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US9941194B1 (en) 2017-02-21 2018-04-10 Texas Instruments Incorporated Packaged semiconductor device having patterned conductance dual-material nanoparticle adhesion layer
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US20150123263A1 (en) 2015-05-07
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