EP2722710B1 - Substrat de réseau, dispositif d'affichage à cristaux liquides et procédé de commande - Google Patents

Substrat de réseau, dispositif d'affichage à cristaux liquides et procédé de commande Download PDF

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EP2722710B1
EP2722710B1 EP13189737.3A EP13189737A EP2722710B1 EP 2722710 B1 EP2722710 B1 EP 2722710B1 EP 13189737 A EP13189737 A EP 13189737A EP 2722710 B1 EP2722710 B1 EP 2722710B1
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pixel electrode
pixel
electrode
tft
voltage
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German (de)
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EP2722710A1 (fr
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Yaohu Liu
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BOE Technology Group Co Ltd
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BOE Technology Group Co Ltd
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    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/1333—Constructional arrangements; Manufacturing methods
    • G02F1/1343—Electrodes
    • G02F1/134309—Electrodes characterised by their geometrical arrangement
    • G02F1/134363—Electrodes characterised by their geometrical arrangement for applying an electric field parallel to the substrate, i.e. in-plane switching [IPS]
    • G—PHYSICS
    • G02—OPTICS
    • G02F—OPTICAL DEVICES OR ARRANGEMENTS FOR THE CONTROL OF LIGHT BY MODIFICATION OF THE OPTICAL PROPERTIES OF THE MEDIA OF THE ELEMENTS INVOLVED THEREIN; NON-LINEAR OPTICS; FREQUENCY-CHANGING OF LIGHT; OPTICAL LOGIC ELEMENTS; OPTICAL ANALOGUE/DIGITAL CONVERTERS
    • G02F1/00—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics
    • G02F1/01—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour 
    • G02F1/13—Devices or arrangements for the control of the intensity, colour, phase, polarisation or direction of light arriving from an independent light source, e.g. switching, gating or modulating; Non-linear optics for the control of the intensity, phase, polarisation or colour  based on liquid crystals, e.g. single liquid crystal display cells
    • G02F1/133—Constructional arrangements; Operation of liquid crystal cells; Circuit arrangements
    • G02F1/136—Liquid crystal cells structurally associated with a semi-conducting layer or substrate, e.g. cells forming part of an integrated circuit
    • G02F1/1362—Active matrix addressed cells
    • G02F1/13624—Active matrix addressed cells having more than one switching element per pixel
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G3/00—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes
    • G09G3/20—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters
    • G09G3/34—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source
    • G09G3/36—Control arrangements or circuits, of interest only in connection with visual indicators other than cathode-ray tubes for presentation of an assembly of a number of characters, e.g. a page, by composing the assembly by combination of individual elements arranged in a matrix no fixed position being assigned to or needed to be assigned to the individual characters or partial characters by control of light from an independent source using liquid crystals
    • G09G3/3611—Control of matrices with row and column drivers
    • G09G3/3648—Control of matrices with row and column drivers using an active matrix
    • G09G3/3659—Control of matrices with row and column drivers using an active matrix the addressing of the pixel involving the control of two or more scan electrodes or two or more data electrodes, e.g. pixel voltage dependant on signal of two data electrodes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1255—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs integrated with passive devices, e.g. auxiliary capacitors
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2300/00—Aspects of the constitution of display devices
    • G09G2300/08—Active matrix structure, i.e. with use of active elements, inclusive of non-linear two terminal elements, in the pixels together with light emitting or modulating elements
    • G09G2300/0809—Several active elements per pixel in active matrix panels
    • G09G2300/0842—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor
    • G09G2300/0847—Several active elements per pixel in active matrix panels forming a memory circuit, e.g. a dynamic memory with one capacitor being a dynamic memory without any storage capacitor, i.e. with use of parasitic capacitances as storage elements
    • G—PHYSICS
    • G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
    • G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
    • G09G2320/00—Control of display operating conditions
    • G09G2320/02—Improving the quality of display appearance
    • G09G2320/0247—Flicker reduction other than flicker reduction circuits used for single beam cathode-ray tubes
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L27/00—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate
    • H01L27/02—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier
    • H01L27/12—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body
    • H01L27/1214—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs
    • H01L27/1251—Devices consisting of a plurality of semiconductor or other solid-state components formed in or on a common substrate including semiconductor components specially adapted for rectifying, oscillating, amplifying or switching and having at least one potential-jump barrier or surface barrier; including integrated passive circuit elements with at least one potential-jump barrier or surface barrier the substrate being other than a semiconductor body, e.g. an insulating body comprising a plurality of TFTs formed on a non-semiconducting substrate, e.g. driving circuits for AMLCDs comprising TFTs having a different architecture, e.g. top- and bottom gate TFTs

Definitions

  • the present invention relates to the technical field of liquid crystal display (LCD), and more particularly to an array substrate, an LCD device and a driving method.
  • LCD liquid crystal display
  • the driving for each pixel unit in an array substrate of an LCD device may be achieved by: a voltage is applied on a pixel electrode which covers the pixel unit, so that an electric field is generated between a pixel electrode and a common electrode, and thus liquid crystal molecules in the pixel rotate for a certain angle, so as to transmit or block off lights.
  • the common electrode is configured for supplying a uniform common voltage V -com to all pixel units; the pixel electrode is configured for supplying a pixel voltage V -pixel to a corresponding pixel unit; and the voltage is configured for controlling an amount of light that transmits the pixel unit.
  • a mode of line scanning i.e. pixel units are turned on line by line, and the pixel units in a current line are turned off when the pixel units in a next line are about to be turned on
  • the pixel voltage is applied on the pixel electrodes when the pixel units are turned on, so that the display of the image is implemented.
  • the pixel electrode is generally coupled to a drain electrode of a thin film transistor (TFT) in the corresponding pixel unit.
  • TFT thin film transistor
  • the TFT is also turned off when the pixel unit is turned off.
  • the pixel voltage on the pixel electrode gradually decreases as time elapses because of a leakage current and a parasitic capacitor, so that the voltage difference between the pixel electrode and the common electrode varies, which results in a flicker phenomenon.
  • US 2010/245700A1 relates to a TFT-LCD array substrate which comprises a plurality of first gate lines and a plurality of first data lines. And a plurality of pixel regions are defined by intersecting the first gate lines and the first data lines with each other.
  • US 2007/080370A1 relates to a plurality of display elements each of which includes two signal lines.
  • An electrode which is one of the electrodes constituting an element capacitor, is connected to the signal line via a switching element TFT, while the other electrode is connected to the signal line via a switching element.
  • US 2010/103085A1 relates to a horizontal electric field liquid crystal display, which includes a first liquid crystal cell, a second liquid crystal cell, a first data line, a second data line, a third data line, a first gate line, a second gate line.
  • Embodiments of the present invention provide a pixel unit, an array substrate, an LCD panel, an LCD device and a driving method for solving the problem of greenish phenomenon and image flickering phenomenon which appear when a conventional LCD device displays an image.
  • an array substrate for a liquid crystal device comprises a plurality of pixel units arranged in form of matrix, each pixel unit comprising: a first thin film transistor (TFT), a second TFT, a first pixel electrode and a second pixel electrode.
  • a drain electrode of the first TFT is electrically coupled to the first pixel electrode.
  • a drain electrode of the second TFT is electrically coupled to the second pixel electrode.
  • the first pixel electrode is electrically insulated from the second pixel electrode, so that when an electric potential difference exists between the first pixel electrode and the second pixel electrode, an electrical field is generated between the first pixel electrode and the second pixel electrode.
  • Each pixel unit further comprises two gate lines and one data line.
  • a gate electrode of the first TFT is electrically coupled to a first gate line of the two gate lines.
  • a gate electrode of the second TFT is electrically coupled to a second gate line of the two gate lines; and source electrodes of the first and second TFTs are electrically coupled to the data line.
  • an LCD device comprises the array substrate as described above.
  • a method for driving an array substrate for a liquid crystal device comprises a plurality of pixel units arranged in form of matrix, each pixel unit comprises a first TFT, a second TFT, a first pixel electrode and a second pixel electrode.
  • a drain electrode of the first TFT is electrically coupled to the first pixel electrode.
  • a drain electrode of the second TFT is electrically coupled to the second pixel electrode.
  • the first pixel electrode is electrically insulated from the second pixel electrode.
  • the step of providing the second voltage to the second pixel electrode (PB) of the pixel unit comprises:
  • the rotation direction of the liquid crystal molecules may be controlled by the voltage difference between the two pixel electrodes, while the voltages on the pixel electrodes of other pixel units in the array substrate is not affected, so that the greenish phenomenon can be avoided.
  • the two TFTs for controlling the two pixel electrodes respectively may have same parasitic capacitor when the pixel unit is turned off, the voltage difference between the two pixel electrodes is kept unchanged, so that the occurrence of the image flickering phenomenon can be avoided.
  • an embodiment of the present invention provides a kind of pixel unit, comprising: a first TFT T 1, a second TFT T2, a first pixel electrode P and a second pixel electrode PB; the drain electrode 15 of the first TFT T1 is electrically coupled to the first pixel electrode P; the drain electrode 16 of the second TFT T2 is electrically coupled to the second pixel electrode PB; and the first pixel electrode P is electrically insulated from the second pixel electrode PB, so that when a voltage difference exists between the first pixel electrode P and the second pixel electrode PB, an electrical field is generated between the first pixel electrode P and the second pixel electrode PB for controlling the rotation direction of liquid crystal molecules.
  • the feature of the pixel unit lies in that: both electrodes for generating the electrical field are provided on an array substrate, and these two electrodes are insulated from each other.
  • the pixel unit having such a structure is widely used in ADS (or AD-SDS, Advanced Super Dimension Switch) LCD panel and IPS (In-Plane Switching) LCD panel.
  • ADS or AD-SDS, Advanced Super Dimension Switch
  • IPS In-Plane Switching
  • the LCD device with the ADS/IPS LCD panel has a wider viewing angle.
  • the ADS may form a multi-dimensional electric field from an electric field generated by a slit electrode edge on a same plane and an electric field generated between a slit electrode layer and a plate electrode layer, so that each of all oriented liquid crystal molecules between the slit electrodes in a liquid crystal cell and just over the electrodes may result in a rotation, and thus the operation efficiency of the liquid crystals is improved and the light transmission efficiency is increased.
  • the ADS may improve the image quality of a TFT-LCD product, and have the advantages of high resolution, high transmittance, low power consumption, wide viewing angle, high aperture ratio, low chromatic aberration, push Mura free, and etc.
  • IPS may form a horizontal electrical field by a plurality of strip-shaped pixel electrodes and a plurality of strip-shaped common electrodes that are in parallel and arranged alternately.
  • the electrical field direction of this horizontal electrical field is parallel to the substrate on which the pixel unit is formed, and this horizontal electrical field is configured for activating the rotation of the liquid crystal molecules in the pixel unit, so as to implement the image display.
  • the pixel unit according to the embodiment of the present invention is mainly different from the pixel unit in the conventional ADS/IPS LCD panel in comprising two TFTs that are configured for controlling two electrodes (pixel electrodes) respectively.
  • the pixel unit substitutes for the conventional common electrode by arranging two pixel electrodes which are insulated from each other. And these two pixel electrodes are controlled respectively by two TFTs in the pixel unit. Therefore, when the pixel unit is turned on, the rotation direction of the liquid crystal molecules are controlled by two electrodes (pixel electrodes) in the pixel unit which are independent from other pixel units, and the other pixel units are not affected at all. Therefore, the greenish phenomenon can be avoided.
  • the first and second TFTs may have exactly same parameters. Specifically speaking, the first and second TFTs may have the same parasitic capacitor.
  • the parasitic capacitor includes the parasitic capacitor between a gate electrode and a source electrode of the TFT, the parasitic capacitor between the gate electrode and a drain electrode of the TFT, or the parasitic capacitor between the source electrode and the drain electrode of the TFT.
  • the pixel unit when the pixel unit is turned on, an electrical field is generated between the two pixel electrodes, and then the pixel unit is turned off, i.e. the TFTs for controlling the two pixel electrodes respectively are turned off.
  • the TFTs for controlling the two pixel electrodes respectively are turned off.
  • the voltages on both pixel electrodes will drop simultaneously.
  • two parasitic capacitors between gate electrodes of the two TFTs and source electrodes or drain electrodes may become equivalent by controlling processing parameters.
  • the two parasitic capacitors are the same, the voltage drop capabilities of the two pixel electrodes are kept unchanged, so that the voltage difference between the two pixel electrodes is stable, and thus the occurrence of image flickering can be avoided.
  • the pixel unit further comprises two gate lines and a data line.
  • Each gate line is coupled to the gate electrode of a TFT, and is configured for supplying voltage to the gate electrode of the TFT, so as to turn on the TFT.
  • the data line is coupled to the source electrode of the TFT, and is configured for supplying voltage to the pixel electrode being coupled to the drain electrode of the TFT.
  • a storage capacitance (not shown) is also arranged in the above pixel unit, and is configured for maintaining the voltages of the first pixel electrode and the second pixel electrode. The storage capacitance may be generated between the pixel electrode and the common line, or may be generated between the pixel electrode and the gate line.
  • Figs. 6a-6c each illustrates three connection modes of the gate line and the data line and the TFT, and the same components in Figs. 6a-6c may have same reference signs.
  • connection mode in Fig. 6a is same as the connection mode of the gate line and the data line and the TFT shown in Fig. 1
  • Fig. 6a is a simplified illustration of Fig. 1
  • the same components in Figs. 1 and 6a may have same reference signs.
  • the pixel unit comprises two gate lines G1, G2 and one data line D2.
  • a gate electrode 11 of a first TFT T1 is electrically coupled to the first gate line G1 of the two gate lines; a gate electrode 12 of a second TFT T2 is electrically coupled to the second gate line G2 of the two gate lines; and a source electrode 13 of the first TFT T1 and a source electrode 14 of the second TFT T2 are electrically coupled to the data line D2.
  • the pixel unit comprises two gate lines G1, G2 and two data lines D1,
  • a gate electrode 11 of a first TFT T1 is electrically coupled to a first gate line G1 of the two gate lines; a gate electrode 12 of a second TFT T2 is electrically coupled to a second gate line G2 of the two gate lines; a source electrode 13 of the first TFT T1 is electrically coupled to a first data line D1 of the two data lines; and a source electrode 14 of the second TFT T2 is electrically coupled to a second data line D2 of the two data lines.
  • the pixel unit may comprise one gate line G1 and two data lines D1, D2; a gate electrode 11 of a first TFT T1 and a gate electrode 12 of a second TFT T2 are electrically coupled to the gate line G1; a source electrode 13 of the first TFT T1 is electrically coupled to a first data line D1 of the two data lines; a source electrode 14 of the second TFT T2 is electrically coupled to a second data line D2 of the two data lines.
  • the pixel unit as illustrated in Fig. 1 is a pixel unit in ADS display panel, wherein a second pixel electrode PB is a whole layer coated electrode (which may be regarded as a plate electrode), a first pixel electrode P is a strip-shaped electrode (which may be regarded as a slit electrode), the first pixel electrode P is arranged on the second pixel electrode PB, there is an insulation layer (not shown) sandwiching between the first pixel electrode P and the second pixel electrode PB.
  • the shapes of the first pixel electrode P and the second pixel electrode PB, and the relative position relations of the first pixel electrode P and the second pixel electrode PB are not limited to the illustration of Fig. 1 , and may be other implementations that may achieve the formation of the multi-dimensional electrical field between the first pixel electrode P and the second pixel electrode PB.
  • the two TFTs T1, T2 are formed simultaneously, and the second pixel electrode PB and the data line D2 are formed on a same layer, so that a drain electrode of the second TFT T2 is directly and electrically coupled to the second pixel electrode PB. Since the first pixel electrode P covers the second pixel electrode PB using the insulation layer, a drain electrode of the first TFT T1 is electrically coupled to the first pixel electrode P via a via-hole Y, as illustrated in Figs. 2a-2b .
  • Fig. 2a is a sectional schematic diagram of the first TFT T1 along A-A' of Fig. 1 , and comprises the substrate 21, the gate electrode 11, the gate insulation layer 22, the semiconductor layer 23, the source electrode/drain electrode contact layer 24 from bottom to top in order.
  • the gate electrode 11 of the first TFT is electrically coupled to the gate line G1.
  • the source electrode 13 of the first TFT covers the source electrode contact layer 24a, and is electrically coupled to the data line D2.
  • the drain electrode 15 of the first TFT covers the drain electrode contact layer 24b.
  • the insulation layer 25 is covered on top of the drain electrode 15, the source electrode 13, and the partially exposed semiconductor layer 23.
  • a via-hole 28 is arranged on the insulation layer 25.
  • the first pixel electrode P being formed on the insulation layer is electrically coupled to the drain electrode 15 via the via-hole 28.
  • Fig. 2b is a sectional schematic diagram of the second TFT T2 along B-B' of Fig. 1 , and comprises the substrate 21, the gate electrode 12, the gate insulation layer 22, the semiconductor layer 26, the source electrode/drain electrode contact layer 27 from bottom to top in order.
  • the gate electrode 12 of the second TFT is electrically coupled to the gate line G2.
  • the source electrode 14 of the second TFT T2 covers the source electrode contact layer 27a, and is electrically coupled to the data line D2.
  • the drain electrode 16 of the second TFT T2 covers the drain electrode contact layer 27b, and an extension part of the drain electrode 16 is being used as the second pixel electrode PB.
  • the structures as illustrated in Figs. 2a and 2b are preferred structures under a condition of simplified processing, i.e. the two TFTs are formed simultaneously, so as to reduce the process of forming the pixel unit. It should be noted that the two TFTs may also not be formed simultaneously, and the two TFTs are not limited to the bottom gate structure. Alternatively, one of the two TFTs may be of the bottom gate structure, and the other TFT may be of the top gate structure; or both TFTs are of the top gate structure. As a result, the electrical connection between the pixel electrode and the drain electrode of the TFT is not limited to the connection as illustrated in Figs. 2a and 2b .
  • the specific connection may be determined based on the structure of the TFT and the relative position relation between the pixel electrode and the TFT. For example, when the pixel electrode is above or below the drain electrode of the TFT, i.e. the pixel electrode is not formed in a same layer as the drain electrode of the TFT, the pixel electrode is electrically coupled to the drain electrode of the TFT by the via hole; when the pixel electrode is formed in a same layer as the drain electrode of the TFT, the pixel electrode is directly and electrically coupled to the drain electrode of the TFT, or the pixel electrode extends for forming the drain electrode of the TFT, or the drain electrode of the TFT extends for forming the pixel electrode.
  • the pixel unit as illustrated in Fig. 3 is a pixel unit in the IPS display panel, which is different from the pixel unit as illustrated in Fig. 1 in term of the structure and the position of the two pixel electrodes.
  • a first pixel electrode P' and a second pixel electrode PB' are formed on a same layer, and both of the first pixel electrode P' and the second pixel electrode PB' are strip-shaped electrodes.
  • the first pixel electrode P' and the second pixel electrode PB' are arranged alternately.
  • the two TFTs T1, T2 are formed simultaneously, and the first pixel electrode P', the second pixel electrode PB' and the data lines D1, D2 are formed on a same layer, so that the drain electrode 15 of the first TFT T1 is directly and electrically coupled to the first pixel electrode P', and the drain electrode 16 of the second TFT T2 is directly and electrically coupled to the second pixel electrode PB'.
  • the two TFTs shown in Fig. 3 are formed simultaneously, so as to reduce the processes for forming the pixel unit. It should be noted that the two TFTs may also not be formed simultaneously. Moreover, one of the two TFTs may be of the bottom gate structure, and the other TFT may be of the top gate structure; or both TFTs are of the top gate structure; or both TFTs are of the bottom gate structure.
  • the electrical connection between the pixel electrode and the drain electrode of the TFT is not limited to the direct electrical connection as described above. The specific connection may be determined based on the structure of the TFT and the relative position relation between the pixel electrode and the TFT.
  • Fig. 1 and Fig. 3 are only schematic diagram of the pixel unit.
  • the first pixel electrode P as illustrated in Fig. 1 comprises three slits in the vertical direction; and the first pixel electrode P' and the second pixel electrode PB' as illustrated in Fig. 3 only comprise two branches.
  • the shape of the two pixel electrodes may be any shape that may cause the generation of a multi-dimensional electrical field or horizontal field being parallel to the surface of the pixel unit between the two pixel electrodes, and may cause the electrical insulation between the two pixel electrodes.
  • the embodiments of the present invention also provide an array substrate, which includes a plurality of the above pixel units that are arranged in form of matrix.
  • Fig. 4 illustrates four pixel units C that are neighboring in the array substrate. The structures of these four pixel units C are same as the structure of the pixel unit as illustrated in Fig. 3 .
  • one pixel unit C shares a gate line with a pixel unit in the same column and neighboring row.
  • the present invention is not limited thereto. It is seen from Fig.
  • a gate line G i is arranged at the intersection by two neighboring pixel units C in the same column, and the gate electrodes of the TFTs that are respectively in the two neighboring pixel units C and are near the gate line G i are coupled to the gate line G i .
  • i indicates the sequence number of the gate line
  • G i indicates the i th gate line. It is assumed that the array substrate has pixel units in n rows and m columns, and then the number of the gate lines of the array substrate is n+1.
  • the character j in Fig. 4 indicates the sequence number of the pixel unit, i.e. the pixel units in the column that correspond to the character j are the pixel units in the j th column.
  • the source electrodes of the TFTs in the pixel units in the j th column are coupled to the data line D j .
  • the source electrodes of the TFTs in the pixel units in the j-1 th column are coupled to the data line D j-1
  • the source electrodes of the TFTs in the pixel units in the j+1 th column are coupled to the data line D j+1 .
  • the array substrate as illustrated in Fig. 4 adopts the structure of the pixel units as illustrated in Fig. 3 . Naturally it may also adopt other structures of the pixel units which are not applicable to the present invention and known by those skilled in the art.
  • the embodiments of the present invention also provide an LCD device comprising the array substrate.
  • the LCD device may be a LCD panel, a mobile phone, a computer or a TV set. Since the bipolar pixel unit with two pixel electrodes respectively controlled by independent TFTs provided by the above embodiments are adopted in the LCD device, the occurrence of greenish phenomenon and image flickering in prior art can be avoided.
  • each pixel unit comprises a first TFT T1, a second TFT T2, a first pixel electrode P and a second pixel electrode PB.
  • the drain electrode of the first TFT T1 is electrically coupled to the first pixel electrode P; the drain electrode of the second TFT T2 is electrically coupled to the second pixel electrode PB; and the first pixel electrode is electrically insulated from the second pixel electrode.
  • the driving method comprises:
  • the conventional common electrode is replaced by arranging two pixel electrodes which are insulated from each other in the pixel unit, and these two pixel electrodes are controlled respectively by two TFTs in the pixel unit. Therefore, when the pixel unit is turned on, the voltages are respectively applied to two electrodes (pixel electrodes) which are independent from other pixel units by two TFTs to control the rotation of the liquid crystal molecules, and the other pixel units are not affected at all. As a result, the occurrence of the greenish phenomenon can be avoided.
  • the pixel unit when the pixel unit is turned on, an electrical field is generated between the two pixel electrodes. Subsequently, the pixel unit is turned off, i.e. the TFTs for controlling the two pixel electrodes respectively are turned off. At this point, since a drain electrode current exists in both TFTs, the voltages on both pixel electrodes will drop simultaneously and the electricity leakage capabilities of the two TFTs may be same by controlling processing parameters. As a result, the voltage drop capabilities of the two pixel electrodes are kept unchanged, so that the voltage difference between the two pixel electrodes is stable. Therefore, the occurrence of image flickering can be avoided.
  • the driving method for the pixel unit provided by the embodiment of the present invention, since two pixel electrodes are arranged in the pixel unit and each of the pixel electrodes is respectively controlled by a corresponding TFT, the rotation direction of the liquid crystal molecules is controlled by the voltage difference between the two pixel electrodes, while the voltage on the pixel electrodes of other pixel units in the array substrate is not affected, so that the greenish phenomenon can be avoided. Furthermore, since the two TFTs for controlling the two pixel electrodes respectively may have same electricity leakage capability when the pixel unit is turned off, the voltage difference between the two pixel electrodes is kept unchanged, and thus the occurrence of the image flickering can be avoided.
  • connection modes of the connection between the gate line and the data line and the TFT in the pixel unit are shown by Fig. 6a to Fig. 6c , respectively. Accordingly, the pixel unit in different connection mode is to be driven by different driving method. In the following, the driving methods of the pixel unit shown in Fig. 6a to Fig. 6c will be respectively described.
  • the pixel unit comprises two gate lines G1, G2 and one data line D1.
  • the step of providing a first voltage to a first pixel electrode P specifically comprises: applying a turn-on voltage to the first gate line G1 of the two gate lines which is electrically coupled to a gate electrode 11 of a first TFT T 1, so as to turn on the first TFT T 1; applying the first voltage to the first pixel electrode P by the data line D2 which is electrically coupled to the source electrode 13 of the first TFT T1.
  • the step of providing a second voltage to a second pixel electrode PB specifically comprises: applying a turn-on voltage to the second gate line G2 of the two gate lines which is electrically coupled to the gate electrode 12 of a second TFT T2, so as to turn on the second TFT T2; applying the second voltage to the second pixel electrode PB by the data line D2 which is electrically coupled to the source electrode 14 of the second TFT T2.
  • the pixel unit comprises two gate lines G1, G2 and two data lines D1, D2.
  • the step of providing the first voltage to the first pixel electrode P specifically comprises: applying a turn-on voltage to the first gate line G1 of the two gate lines which is electrically coupled to the gate electrode 11 of the first TFT T1, so as to turn on the first TFT T1; applying the first voltage to the first pixel electrode P by the first data line D1 of the two data lines which is electrically coupled to the source electrode 13 of the first TFT T1.
  • the step of providing the second voltage to the second pixel electrode PB specifically comprises: applying a turn-on voltage to the second gate line G2 of the two gate lines which is electrically coupled to the gate electrode 12 of the second TFT T2, so as to turn on the second TFT T2; applying the second voltage to the second pixel electrode PB by the second data line D2 of the two data lines which is electrically coupled to the source electrode 14 of the second TFT T2.
  • the pixel unit comprises a gate line G1 and two data lines D1, D2.
  • the step of providing the first voltage to the first pixel electrode P and the step of providing the second voltage to the second pixel electrode may be implemented simultaneously, which specifically comprise: applying a turn-on voltage to the gate line G1 which is commonly and electrically coupled to the gate electrode 11 of the first TFT T1 and the gate electrode 12 of the second TFT T2, so as to turn on the first TFT T1 and the second TFT T2 simultaneously; applying the first voltage to the first pixel electrode P by the first data line D1 of the two data lines which is electrically coupled to the source electrode 13 of the first TFT T1; meanwhile, applying the second voltage to the second pixel electrode PB by the second data line D2 of the two data lines which is electrically coupled to the source electrode 14 of the second TFT T2.
  • This method is configured for driving the array substrate as illustrated in Fig. 4 and adopts the line scanning manner, i.e. applying a voltage to the gate line row by row.
  • the data voltage Data_in as illustrated in Fig. 5 is applied to the data line D j of the pixel units in the j th column in the array substrate as illustrated in Fig. 4 .
  • the following voltages are applied on the data line in turn: 0v, -2v, +3v, -2v, 0v, 0v, -2v, 1v.
  • the turn-on voltage is applied on the i-1 th gate line to the i+6 th gate line in turn in the predetermined time intervals t1 ⁇ t8.
  • the turn-on voltage is applied on the i-1 th gate line G i-1 , the first TFT of the pixel unit in the i th row is turned on, the voltage of 0v is applied on the first pixel electrode P being coupled to the first TFT T1 in the pixel unit C in the i th row and the j th column; during the second time interval t2, the gate line G i-1 in the i-1 th row is turned off, i.e.
  • the first TFT T1 of the pixel unit in the i-1 th row is turned off, and under the storage capacitance, the voltage on the first pixel electrode P may be maintained until the display of the frame of image is completed, the turn-on voltage is applied on the i th gate line G i , the second TFT T2 of the pixel unit in the i th row and the first TFT T1 of the pixel unit in the i+1 th row are turned on, the voltage of -2v is applied on the second pixel electrode PB being coupled to the second TFT T2 in the pixel unit C in the i th row and the j th column, meanwhile the voltage of -2v is also applied on the first pixel electrode being coupled to the first TFT T1 in the pixel unit in the i+1 th row and the j th column, so that a voltage difference of (-2-0)v (i.e.-2v) is generated between the first pixel electrode P and the second pixel electrode PB in the pixel unit in the
  • the voltage of the second pixel electrode in the pixel unit C in the i th row and the j th column may also be maintained until the display of the frame of the image is completed by the storage capacitance, and so on.
  • the waveform in solid line indicated by P in Fig. 5 illustrates the voltage being applied on the first pixel electrode P in pixel unit in each row in turn; the waveform in dotted line indicated by PB illustrates the voltage being applied on the second pixel electrode PB in each pixel unit in turn. Therefore, a voltage difference ⁇ V is obtained by subtracting the voltage on the first pixel electrode P from the voltage on the second pixel electrode PB, and such voltage difference is a voltage being configured for controlling the rotation direction of the liquid crystal molecules in the pixel unit.
  • the absolute value of the voltage being applied on a single pixel electrode is significantly reduced while the same control voltage of the liquid crystal molecules may be obtained.
  • the voltage difference between the two pixel electrodes being obtained during the time interval t2 is +5v
  • the voltages being required to be applied on the two pixel electrodes are -2v and +3v respectively.
  • the voltage on the common electrode is generally set to 0v
  • a voltage of +5v is required to be applied on the pixel electrode for obtaining the voltage difference of +5v between the pixel electrode and the common electrode.

Claims (9)

  1. Substrat de réseau pour un affichage à cristaux liquides, comprenant une pluralité d'unités de pixel (C) agencées sous forme de matrice, chaque unité de pixel comprenant : un premier transistor à couches minces (TFT) (T1), un deuxième TFT (T2), une première électrode de pixel (P) et une deuxième électrode de pixel (PB) ;
    sachant qu'une électrode de drain (15) du premier TFT est électriquement couplée à la première électrode de pixel (P) ; une électrode de drain (16) du deuxième TFT est électriquement couplée à la deuxième électrode de pixel (PB) ; et la première électrode de pixel (P) est électriquement isolée de la deuxième électrode de pixel (PB), de sorte que lorsqu'une différence de potentiel électrique existe entre la première électrode de pixel (P) et la deuxième électrode de pixel (PB), un champ électrique soit généré entre la première électrode de pixel (P) et la deuxième électrode de pixel (PB),
    lequel est caractérisé en ce que chaque unité de pixel (C) comprend en outre deux lignes de porte (G1, G2) et une ligne de données (D2) ; et
    une électrode de porte (11) du premier TFT est électriquement couplée à une première ligne de porte (G1) des deux lignes de porte ; une électrode de porte (12) du deuxième TFT est électriquement couplée à une deuxième ligne de porte (G2) des deux lignes de porte ; et des électrodes de source (13, 14) du premier et du deuxième TFT sont électriquement couplées à la ligne de données (D2).
  2. Le substrat de réseau selon la revendication 1, sachant que la deuxième électrode de pixel est une électrode revêtue d'une couche entière ; la première électrode de pixel est une électrode en forme de bande ; et la première électrode de pixel est agencée sur la deuxième électrode de pixel, une couche isolante étant intercalée entre elles.
  3. Le substrat de réseau selon la revendication 2, sachant que l'électrode de drain du premier TFT est électriquement couplée à la première électrode de pixel via un trou d'interconnexion ; et l'électrode de drain du deuxième TFT est électriquement couplée à la deuxième électrode de pixel.
  4. Le substrat de réseau selon la revendication 1, sachant que la première électrode de pixel et la deuxième électrode de pixel sont formées sur une même couche, et à la fois la première électrode de pixel et la deuxième électrode de pixel sont des électrodes en forme de bande.
  5. Le substrat de réseau selon l'une quelconque des revendications 1 à 4, sachant que le premier et le deuxième TFT ont un même condensateur parasite.
  6. Le substrat de réseau selon la revendication 1, sachant que la première électrode de pixel, la deuxième électrode de pixel et les lignes de données sont formées sur une même couche.
  7. Le substrat de réseau selon l'une quelconque des revendications 1 à 6, sachant que deux unités de pixel qui sont dans une même colonne et sont dans des rangées voisines partagent une ligne de porte, et sachant que les deux unités de pixel sont agencées de façon adjacente l'une à l'autre.
  8. Dispositif d'affichage à cristaux liquides (LCD), lequel est caractérisé en ce qu'il comprend le substrat de réseau selon l'une quelconque des revendications 1 à 7.
  9. Procédé destiné à commander un substrat de réseau pour un affichage à cristaux liquides, sachant que le substrat de réseau comprend une pluralité d'unités de pixel (C) agencées sous forme de matrice, chaque unité de pixel comprend un premier transistor TFT (T1), un deuxième TFT (T2), une première électrode de pixel (P) et une deuxième électrode de pixel (PB) ; une électrode de drain (15) du premier TFT est électriquement couplée à la première électrode de pixel (P) ; une électrode de drain (16) du deuxième TFT (PB) est électriquement couplée à la deuxième électrode de pixel ; et la première électrode de pixel (P) est électriquement isolée de la deuxième électrode de pixel (PB), le procédé comprenant :
    la fourniture d'une première tension à la première électrode de pixel (P) ;
    la fourniture d'une deuxième tension à la deuxième électrode de pixel (PB) ; et
    la génération d'un champ électrique entre la première électrode de pixel (P) et la deuxième électrode de pixel (PB), lorsqu'une différence de tension existe entre la première tension et la deuxième tension,
    lequel est caractérisé en ce que chaque unité de pixel (C) comprend en outre deux lignes de porte (G1, G2) et une ligne de données (D2),
    l'étape de fourniture de la première tension à la première électrode de pixel (P) de l'unité de pixel comprend :
    l'application d'une tension de mise en marche à la première ligne de porte (G1) des deux lignes de porte qui est électriquement couplée à une électrode de porte (11) du premier TFT, de manière à mettre en marche le premier TFT ; et
    l'application de la première tension à la première électrode de pixel (P) par la ligne de données (D2) qui est électriquement couplée à une électrode de source (13) du premier TFT ;
    l'étape de fourniture de la deuxième tension à la deuxième électrode de pixel (PB) de l'unité de pixel comprend :
    l'application de la tension de mise en marche à une deuxième ligne de porte (G2) des deux lignes de porte qui est électriquement couplée à une électrode de porte (12) du deuxième TFT, de manière à mettre en marche le deuxième TFT ; et
    l'application de la deuxième tension à la deuxième électrode de pixel (PB) par la ligne de données (D2) qui est électriquement couplée à l'électrode de source (14) du deuxième TFT.
EP13189737.3A 2012-10-22 2013-10-22 Substrat de réseau, dispositif d'affichage à cristaux liquides et procédé de commande Active EP2722710B1 (fr)

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