EP2394275B1 - Composant électrique multicouche - Google Patents

Composant électrique multicouche Download PDF

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Publication number
EP2394275B1
EP2394275B1 EP10701703.0A EP10701703A EP2394275B1 EP 2394275 B1 EP2394275 B1 EP 2394275B1 EP 10701703 A EP10701703 A EP 10701703A EP 2394275 B1 EP2394275 B1 EP 2394275B1
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EP
European Patent Office
Prior art keywords
electrical component
component according
layer
dielectric layer
multilayer electrical
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Active
Application number
EP10701703.0A
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German (de)
English (en)
Other versions
EP2394275A1 (fr
Inventor
Thomas Feichtinger
Georg Krenn
Thomas Pürstinger
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
TDK Electronics AG
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TDK Electronics AG
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Publication date
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Publication of EP2394275A1 publication Critical patent/EP2394275A1/fr
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Publication of EP2394275B1 publication Critical patent/EP2394275B1/fr
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Classifications

    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/102—Varistor boundary, e.g. surface layers
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/10—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material voltage responsive, i.e. varistors
    • H01C7/12—Overvoltage protection resistors
    • H—ELECTRICITY
    • H01—ELECTRIC ELEMENTS
    • H01C—RESISTORS
    • H01C7/00—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material
    • H01C7/18—Non-adjustable resistors formed as one or more layers or coatings; Non-adjustable resistors made from powdered conducting material or powdered semi-conducting material with or without insulating material comprising a plurality of layers stacked between terminals

Definitions

  • DE 10 2004 058 410 A1 is an electrical multilayer component with ESD protection element known.
  • DE 10 2004 010001 A1 an electrical component which has a stack of ceramic layers which form a base body and electrode layers arranged therebetween, which form a capacitor. A phase shifter is applied to a ceramic layer.
  • the electrode layers are electrically conductively connected by means of through-contacts running in the interior of the main body with contact surfaces.
  • the invention is defined by the features of claim 1.
  • the object of the present invention is to specify a multilayer electrical component comprising an ESD protection device with a low breakdown voltage and a low ESD clamping voltage.
  • an electrical multilayer component having a base body with at least two outer electrodes.
  • the electrical multilayer component has at least one first and at least one second inner electrode, which are electrically conductively connected to one outer electrode each are.
  • the inner electrode is connected directly or via plated-through holes in the multilayer component with the outer electrode.
  • the electrical multilayer component has at least one ceramic varistor layer.
  • the ceramic varistor layer comprises at least the first inner electrode.
  • the first inner electrode is preferably largely surrounded by the ceramic varistor layer, wherein the first inner electrode is freely contactable at least in the region of the contact to the outer electrode.
  • the first inner electrode is applied directly to the varistor layer.
  • the multilayer electrical component comprises at least one dielectric layer.
  • the dielectric layer is arranged at least between a varistor layer and at least one further layer.
  • the further layer comprises the second inner electrode.
  • the second inner electrode is largely enclosed by the further layer, wherein the second inner electrode is freely contactable at least in the region of the contact with its outer electrode.
  • the second inner electrode is preferably applied directly to the further layer.
  • the dielectric layer has at least one opening.
  • the opening may be formed as a breakthrough, as a recess or as a cavity.
  • the opening in the dielectric layer is filled with a semiconducting material or a metal. Preferably, the opening is completely filled. In a further embodiment, however, single or multiple closed or open cavities are present in the filling of the opening.
  • the semiconductive material with which one or more openings in the dielectric layer are filled comprises a varistor ceramic.
  • the varistor ceramic, with which the opening in the dielectric layer is filled, is preferably identical to the varistor ceramic of the further varistor layer.
  • the varistor ceramic in the opening of the dielectric layer is different from the ceramic of the varistor layer.
  • the semiconducting material comprises a resistance material.
  • the metal with which one or more openings of a dielectric layer are filled comprises a metal, which preferably comprises silver, palladium, platinum, silver palladium or other suitable metals.
  • openings in the dielectric layer may be filled with different materials.
  • all openings of a dielectric layer are filled with the same material.
  • the main body of the electrical multilayer component comprises cover packages, which terminate the basic body of the multilayer component in the thickness direction upwards and downwards.
  • the cover packages each comprise at least one dielectric layer.
  • the cover packages of the multilayer electrical component and the dielectric layers having at least one opening may comprise the same material. In a further embodiment, it is also possible for the cover packages and the dielectric layer to comprise different materials.
  • the dielectric layer zirconia (ZrO 2 ) or a zirconia-glass composite
  • the dielectric layers may also comprise other suitable materials.
  • the electrical multilayer component has one or more plated-through holes, so-called vias, with which individual or all internal electrodes of the electrical multilayer component are connected to the external contacts.
  • the external contacts of the electrical multilayer component are formed as an array (row or matrix arrangement).
  • LGA Land Grid Array
  • BGA Ball Grid Array
  • the internal electrodes of the electrical multilayer component are preferably connected to the external contacts via plated-through holes.
  • the dielectric layer which comprises at least one opening, is designed such that it forms an ESD discharge gap together with at least two adjacent varistor layers and two overlapping internal electrodes.
  • the opening in the dielectric layer is filled with a semiconducting material or a metal, in particular by a method of printing on the dielectric layer, in such a way that a so-called catch pad known per se is formed.
  • a via can be arranged thereon, whereby a free-standing electrode structure is formed over the dielectric layer.
  • the electrical multilayer component has the function of a varistor with integrated ESD protection component.
  • the varistor preferably has a capacity of less than 1 pF.
  • the ESD protection component of the multilayer electrical component is preferably designed such that it has an ESD breakdown voltage of less than 20 V at 1 mA current.
  • the ESD protection component of the electrical multilayer component preferably has an ESD clamping voltage of less than 500 V.
  • An electrical multilayer component as described above has a reduction in the total capacitance of the component, especially as a result of the arrangement of the small capacitance of the dielectric layer connected in series with the varistor capacitance.
  • the clamping voltage of the electrical multilayer component is only slightly increased by the dielectric layer compared to conventional multilayer components.
  • the specified clamping voltage of the ESD protection component is essentially dependent on the distance between the inner electrode layers.
  • the total capacitance of the electrical multilayer component is significantly reduced, as a result of which the current-carrying capacity and pulse stability of the component are further increased.
  • FIG. 1 a first embodiment of a multilayer electrical component is shown, which comprises a base body 1. On the side surfaces of the base body 1 are Outer electrodes 2, 2 'are arranged, which are conductively connected to the inside of the main body 1 lying inside electrodes 3, 4.
  • the main body 1 has a varistor layer 5, which comprises a first inner electrode 3.
  • the first inner electrode 3 is largely enclosed by the varistor layer 5.
  • the electrical multilayer component has a further layer 7, which in the illustrated embodiment is designed as a further varistor layer.
  • the further layer 7 comprises a second inner electrode 4, which is largely enclosed by the further layer 7.
  • a dielectric layer 6 is arranged, which has an opening 8.
  • the opening 8 is filled with a semiconductive material or a metal.
  • the main body 1 of the electrical multilayer component is terminated in the thickness direction by cover packages 9, 9 ', the cover packages 9, 9' preferably each comprising at least one dielectric layer.
  • FIG. 2 shows a further embodiment of the electrical multilayer component.
  • the structure of the electric multilayer component is almost identical to the structure in FIG FIG. 1 wherein the first inner electrode 3 is applied on a surface of the varistor layer 5 and the second inner electrode 4 is applied on a surface of the further layer 7.
  • the first inner electrode is arranged between the varistor layer 5 and the cover package 9.
  • the second inner electrode 4 is arranged between the further layer 7 and the further second cover package 9 '.
  • FIG. 3 shows a further embodiment of the electrical multilayer component.
  • the electrical multilayer component has a main body 1 in which a varistor layer 5 is arranged, on which a first inner electrode 3 is arranged. In the thickness direction, the first inner electrode 3 and the varistor layer 5 are closed by a first cover package 9 upwards.
  • a dielectric layer 6 is arranged below the varistor layer 5, which has openings 8. The openings 8 are filled with a semiconducting material or metal.
  • second internal electrodes 4 are arranged on the underside of the dielectric layer 6.
  • the first inner electrode 3 and the second inner electrodes 4 are connected via vias 10 with external contacts 2.
  • the vias 10 can, for example, as in the FIG.
  • the main body 1 of the electrical multilayer component is closed in the thickness direction down by a second cover package 9 '.
  • FIG. 4 a further embodiment of the electrical multilayer component is shown, which corresponds to the embodiment in FIG. 3 is similar, wherein the dielectric layer 6 has the two openings 8.
  • the dielectric layer 6 is arranged in the thickness direction between two layers 5, 7.
  • the two layers 5, 7 are designed as varistor ceramic.
  • the external contacts 2, 2 'of the electrical multilayer component are designed as land grid arrays in the illustrated embodiment.
  • the vias can, for example, as in the FIG. 4 be shown cylindrical or frusto-conical, the vias can, for example, in the direction of the external contacts 2, 2 'or taper towards the internal electrodes 3, 4 out.
  • FIG. 5 shows a further embodiment of the multilayer electrical component, the embodiment of FIG. 1 similar.
  • the dielectric layer 6 in the FIG. 5 has two openings 8, which are filled with a semiconducting material or with a metal.
  • FIG. 6 shows a further embodiment of the electrical multilayer component, wherein the electrical multilayer component comprises three parallel ESD protection elements.
  • the ESD protection elements are each in the FIG. 2 already described in detail.
  • Each of the ESD protection elements comprises a first varistor layer 5 and a further layer 7.
  • the further layer 7 is designed as a further varistor layer in the illustrated embodiment.
  • a dielectric layer 6 is arranged, which has an opening 8.
  • the opening 8 is filled with a semiconductive material or with metal.
  • the ESD protection elements each have a first inner electrode 3 and a second inner electrode 4, wherein the inner electrodes 3, 4 are applied to the varistor layer 5 or to the further layer 7.
  • FIG. 7 shows a further embodiment of the electrical multilayer component.
  • the electrical multilayer component has a base body 1 with cover packages 9, 9 ', the cover packages 9, 9' preferably comprising at least one dielectric layer. Between the cover packages 9, 9 ', a varistor layer 5 and a further layer 7 are arranged, wherein the further layer 7 is designed as a varistor layer. Between the varistor layer 5 and the further layer 7, three dielectric intermediate layers 6 are arranged, which are separated from one another by intermediate layers of a varistor ceramic are spaced in the thickness direction.
  • the dielectric layers 6 each have an opening 8.
  • the openings 8 of the dielectric layers 6 are each filled with a semiconductive material or the opening 8 'with a metal.
  • the electrical multilayer component has internal electrodes 3, 4 which are connected to external contacts 2, 2 '.
  • the first inner electrode 3 is arranged between the varistor layer 5 and the cover package 9.
  • the second inner electrode 4 is arranged between the further layer 7 and the second cover package 9 '.
  • FIG. 8 shows an embodiment in which similar to the embodiments of the FIGS. 3 and 4 a base body 1, a varistor layer 5, a first inner electrode 3, a first cover package 9, a dielectric layer 6 with openings 8, a second cover package 9 ', vias 10 and external contacts 2, 2' are present.
  • the openings 8 are filled with a semiconducting material or metal, so that catch pads 11 are formed, which spread on a surface of the dielectric layer 6 laterally to the openings 8.
  • the catch pads 11 are in the embodiment of the FIG. 8 on the side facing away from the varistor layer 5 side of the dielectric layer 6.
  • the catch pads 11 may be prepared, for example, that the openings are filled by a method of printing with the semiconducting material or metal, so that a proportion of the fillings material used forms the top-side catch pads 11.
  • the catch pads 11 can be like in the FIG. 8 shown provided with the associated vias 10 and so are electrically connected to the external contacts 2 '.
  • the catch pads 11 may act as second internal electrodes. It may additionally second Internal electrodes are provided in electrically conductive connection with the catch pads 11.
  • typical dimensions are a thickness of the dielectric layer 6 of 10 ⁇ m to 30 ⁇ m, a diameter of the openings 8 of 20 ⁇ m to 30 ⁇ m, a diameter of the catch pads 11 of about 100 ⁇ m, a thickness of the catch pads of FIG ⁇ m to 5 ⁇ m and a height of a vias 10 plus catch pad 11 of about 50 ⁇ m.
  • the vias 10 may be cylindrical or conical.
  • FIG. 9 shows a further embodiment, in which similar to the embodiment according to FIG. 8 a base body 1, a varistor layer 5, a first inner electrode 3, a first cover package 9, a dielectric layer 6 with openings 8, a second cover package 9 ', vias 10 and external contacts 2, 2' are present.
  • the openings 8 are filled with a semiconducting material or metal, so that catch pads 11 are formed, which spread on a surface of the dielectric layer 6 laterally to the openings 8.
  • the catch pads 11 are in the embodiment of the FIG. 9
  • Second inner electrodes 4 are arranged on the side facing away from the varistor layer 5 side of the dielectric layer 6 and electrically connected via vias 10 with external contacts 2 '.
  • the dimensions, in particular the openings 8 and the catch pads 11, the above to the embodiment of the FIG. 8 corresponding dimensions.
  • the electrical multilayer component comprises a plurality of ESD protection devices connected in series or in parallel, which are protected by at least a dielectric layer having one or more openings and at least one adjacent varistor layer are formed.

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  • Engineering & Computer Science (AREA)
  • Microelectronics & Electronic Packaging (AREA)
  • Physics & Mathematics (AREA)
  • Electromagnetism (AREA)
  • Thermistors And Varistors (AREA)
  • General Electrical Machinery Utilizing Piezoelectricity, Electrostriction Or Magnetostriction (AREA)

Claims (15)

  1. Composant multicouche électrique, comprenant
    - un corps de base (1) muni d'électrodes externes (2, 2'),
    - des électrodes internes (3, 4) qui sont reliées de manière électriquement conductrice respectivement à une électrode externe (2, 2'),
    - une couche de varistance (5) en céramique qui est pourvue de l'une des électrodes internes (3), et
    - une couche diélectrique (6) adjacente à la couche de varistance (5),
    - les électrodes internes (3, 4) étant disposées sur des côtés mutuellement opposés de la couche diélectrique (6) et
    - la couche diélectrique (6) possédant au moins une ouverture (8) entre les électrodes internes (3, 4), laquelle est remplie d'un matériau semiconducteur ou d'un métal, de sorte que le matériau semiconducteur présent dans l'ouverture (8) ou le métal présent dans l'ouverture (8) jouxte à plat la couche de varistance (5).
  2. Composant multicouche électrique selon la revendication 1, avec lequel l'ouverture (8) est remplie d'un matériau semiconducteur qui comporte une céramique de varistance ou un matériau résistif.
  3. Composant multicouche électrique selon la revendication 1, avec lequel l'ouverture (8) est remplie de métal qui comporte de l'Ag, du Pd, du Pt ou de l'AgPd.
  4. Composant multicouche électrique selon l'une des revendications 1 à 3, avec lequel, sur le côté de la couche diélectrique (6) qui est à l'opposé de la couche de varistance (5) est disposée une couche supplémentaire (7) qui est réalisée sous la forme d'une couche de varistance en céramique et est pourvue de l'une des électrodes internes (4).
  5. Composant multicouche électrique selon l'une des revendications 1 à 4, avec lequel la couche diélectrique (6) comporte du ZrO2, un composite de ZrO2 et de verre, de l'AlOx, un verre-AlOx, du MgO ou un verre-MgO.
  6. Composant multicouche électrique selon l'une des revendications 1 à 5, avec lequel le corps de base (1) possède des paquets de recouvrement (9, 9') qui comportent respectivement au moins une couche diélectrique supplémentaire.
  7. Composant multicouche électrique selon l'une des revendications 1 à 6, avec lequel les électrodes internes (3, 4) sont reliées aux contacts externes (2, 2') par le biais de trous d'interconnexion (10).
  8. Composant multicouche électrique selon l'une des revendications 1 à 7, avec lequel les contacts externes (2, 2') sont réalisés sous la forme d'un boîtier à matrice de plots (LGA) ou d'un boîtier à matrice de billes (BGA).
  9. Composant multicouche électrique selon l'une des revendications 1 à 8, avec lequel la couche diélectrique (6) est configurée de telle sorte que conjointement avec au moins deux couches de varistance (5) voisines qui sont présentes en tout et les électrodes internes réalisées sous la forme de deux électrodes internes (2, 3) qui se chevauchent, elle forme un trajet de décharge d'ESD.
  10. Composant multicouche électrique selon l'une des revendications 1 à 9, qui possède la fonction d'une varistance avec composant de protection ESD intégré.
  11. Composant multicouche électrique selon l'une des revendications 1 à 10, qui présente une capacité inférieure à 1 pF.
  12. Composant multicouche électrique selon l'une des revendications 1 à 11, qui, à un courant de 1 mA, présente une tension de claquage ESD inférieure à 20 V.
  13. Composant multicouche électrique selon l'une des revendications 1 à 12, qui, en présence d'une impulsion ESD d'une tension de 8 kV, présente une tension aux bornes ESD inférieure à 500 V.
  14. Composant multicouche électrique selon l'une des revendications 1 à 13, avec lequel l'ouverture (8) dans la couche diélectrique (6) est remplie avec un matériau semiconducteur ou un métal de telle sorte qu'une pastille (11) est formée, laquelle s'élargit latéralement par rapport à l'ouverture (8) sur une surface de la couche diélectrique (6).
  15. Composant multicouche électrique selon la revendication 14, avec lequel la pastille (11) est pourvue d'un trou d'interconnexion (10).
EP10701703.0A 2009-02-03 2010-02-02 Composant électrique multicouche Active EP2394275B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
DE102009007316A DE102009007316A1 (de) 2009-02-03 2009-02-03 Elektrisches Vielschichtbauelement
PCT/EP2010/051247 WO2010089294A1 (fr) 2009-02-03 2010-02-02 Composant électrique multicouche

Publications (2)

Publication Number Publication Date
EP2394275A1 EP2394275A1 (fr) 2011-12-14
EP2394275B1 true EP2394275B1 (fr) 2019-10-16

Family

ID=42035891

Family Applications (1)

Application Number Title Priority Date Filing Date
EP10701703.0A Active EP2394275B1 (fr) 2009-02-03 2010-02-02 Composant électrique multicouche

Country Status (7)

Country Link
US (1) US8410891B2 (fr)
EP (1) EP2394275B1 (fr)
JP (1) JP5758305B2 (fr)
KR (1) KR101665742B1 (fr)
CN (1) CN102308341B (fr)
DE (1) DE102009007316A1 (fr)
WO (1) WO2010089294A1 (fr)

Families Citing this family (11)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
DE102009010212B4 (de) * 2009-02-23 2017-12-07 Epcos Ag Elektrisches Vielschichtbauelement
EP2381451B1 (fr) 2010-04-22 2018-08-01 Epcos AG Procédé de production d'un composant électrique multicouches et composant électrique multicouches
DE102010036270B4 (de) * 2010-09-03 2018-10-11 Epcos Ag Keramisches Bauelement und Verfahren zur Herstellung eines keramischen Bauelements
TW201234393A (en) * 2011-02-09 2012-08-16 Yageo Corp Multi-layer varistor having core electrode unit
DE102012101606A1 (de) * 2011-10-28 2013-05-02 Epcos Ag ESD-Schutzbauelement und Bauelement mit einem ESD-Schutzbauelement und einer LED
KR101983135B1 (ko) 2012-12-27 2019-05-28 삼성전기주식회사 인덕터 및 그의 갭층 제조를 위한 조성물
KR101808794B1 (ko) * 2015-05-07 2018-01-18 주식회사 모다이노칩 적층체 소자
DE102017108384A1 (de) * 2017-04-20 2018-10-25 Epcos Ag Vielschichtbauelement und Verfahren zur Herstellung eines Vielschichtbauelements
JP7235492B2 (ja) * 2018-12-12 2023-03-08 Tdk株式会社 チップバリスタ
JP7322793B2 (ja) * 2020-04-16 2023-08-08 Tdk株式会社 チップバリスタの製造方法及びチップバリスタ
US20230215727A1 (en) * 2022-01-05 2023-07-06 Polar Semiconductor, Llc Forming passivation stack having etch stop layer

Family Cites Families (14)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH0722752A (ja) * 1993-06-30 1995-01-24 Matsushita Electric Ind Co Ltd 多層セラミック基板およびその製造方法
JPH11265808A (ja) * 1998-03-16 1999-09-28 Tokin Corp サージ吸収素子及びその製造方法
JP3489728B2 (ja) * 1999-10-18 2004-01-26 株式会社村田製作所 積層コンデンサ、配線基板および高周波回路
DE10064447C2 (de) * 2000-12-22 2003-01-02 Epcos Ag Elektrisches Vielschichtbauelement und Entstörschaltung mit dem Bauelement
JP2002368420A (ja) * 2001-06-05 2002-12-20 Murata Mfg Co Ltd ガラスセラミック多層基板の製造方法およびガラスセラミック多層基板
FR2835981B1 (fr) * 2002-02-13 2005-04-29 Commissariat Energie Atomique Microresonateur mems a ondes acoustiques de volume accordable
JP4292788B2 (ja) * 2002-11-18 2009-07-08 三菱マテリアル株式会社 チップ型サージアブソーバ及びその製造方法
DE102004010001A1 (de) * 2004-03-01 2005-09-22 Epcos Ag Elektrisches Bauelement und schaltungsanordnung mit dem Bauelement
DE102004058410B4 (de) 2004-12-03 2021-02-18 Tdk Electronics Ag Vielschichtbauelement mit ESD-Schutzelementen
DE102005016590A1 (de) * 2005-04-11 2006-10-26 Epcos Ag Elektrisches Mehrschicht-Bauelement und Verfahren zur Herstellung eines Mehrschicht-Bauelements
DE102005050638B4 (de) 2005-10-20 2020-07-16 Tdk Electronics Ag Elektrisches Bauelement
DE102006000935B4 (de) * 2006-01-05 2016-03-10 Epcos Ag Monolithisches keramisches Bauelement und Verfahren zur Herstellung
US7541910B2 (en) * 2006-05-25 2009-06-02 Sfi Electronics Technology Inc. Multilayer zinc oxide varistor
DE102007012049B4 (de) * 2007-03-13 2017-10-12 Epcos Ag Elektrisches Bauelement

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
None *

Also Published As

Publication number Publication date
JP2012517097A (ja) 2012-07-26
EP2394275A1 (fr) 2011-12-14
CN102308341A (zh) 2012-01-04
WO2010089294A1 (fr) 2010-08-12
JP5758305B2 (ja) 2015-08-05
KR20110116041A (ko) 2011-10-24
CN102308341B (zh) 2013-06-05
US8410891B2 (en) 2013-04-02
DE102009007316A1 (de) 2010-08-05
KR101665742B1 (ko) 2016-10-12
US20120044039A1 (en) 2012-02-23

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