EP2003569A2 - Controleur de memoire flash - Google Patents

Controleur de memoire flash Download PDF

Info

Publication number
EP2003569A2
EP2003569A2 EP06798153A EP06798153A EP2003569A2 EP 2003569 A2 EP2003569 A2 EP 2003569A2 EP 06798153 A EP06798153 A EP 06798153A EP 06798153 A EP06798153 A EP 06798153A EP 2003569 A2 EP2003569 A2 EP 2003569A2
Authority
EP
European Patent Office
Prior art keywords
data
page
segment
last valid
pages
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
EP06798153A
Other languages
German (de)
English (en)
Other versions
EP2003569A4 (fr
EP2003569B1 (fr
EP2003569A9 (fr
Inventor
Seiji c/o Matsushita El. Ind. Co. Ltd. NAKAMURA
Hirokazu c/o Matsushita El. Ind. Co. Ltd. SOU
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panasonic Corp
Original Assignee
Panasonic Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panasonic Corp filed Critical Panasonic Corp
Publication of EP2003569A2 publication Critical patent/EP2003569A2/fr
Publication of EP2003569A9 publication Critical patent/EP2003569A9/fr
Publication of EP2003569A4 publication Critical patent/EP2003569A4/fr
Application granted granted Critical
Publication of EP2003569B1 publication Critical patent/EP2003569B1/fr
Not-in-force legal-status Critical Current
Anticipated expiration legal-status Critical

Links

Images

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/14—Error detection or correction of the data by redundancy in operation
    • G06F11/1402—Saving, restoring, recovering or retrying
    • G06F11/1415—Saving, restoring, recovering or retrying at system level
    • G06F11/1441—Resetting or repowering
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F11/00—Error detection; Error correction; Monitoring
    • G06F11/07—Responding to the occurrence of a fault, e.g. fault tolerance
    • G06F11/08—Error detection or correction by redundancy in data representation, e.g. by using checking codes
    • G06F11/10—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's
    • G06F11/1008—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices
    • G06F11/1068—Adding special bits or symbols to the coded information, e.g. parity check, casting out 9's or 11's in individual solid state devices in sector programmable memories, e.g. flash disk
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F12/00—Accessing, addressing or allocating within memory systems or architectures
    • G06F12/02—Addressing or allocation; Relocation
    • G06F12/0223—User address space allocation, e.g. contiguous or non contiguous base addressing
    • G06F12/023—Free address space management
    • G06F12/0238—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory
    • G06F12/0246—Memory management in non-volatile memory, e.g. resistive RAM or ferroelectric memory in block erasable memory, e.g. flash memory
    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F2212/00—Indexing scheme relating to accessing, addressing or allocation within memory systems or architectures
    • G06F2212/72—Details relating to flash memory management
    • G06F2212/7209—Validity control, e.g. using flags, time stamps or sequence numbers
    • G—PHYSICS
    • G11—INFORMATION STORAGE
    • G11C—STATIC STORES
    • G11C29/00—Checking stores for correct operation ; Subsequent repair; Testing stores during standby or offline operation
    • G11C29/04—Detection or location of defective memory elements, e.g. cell constructio details, timing of test signals
    • G11C2029/0411—Online error correction

Definitions

  • the present invention relates to an art of controlling access to nonvolatile semiconductor memories.
  • it relates to a memory controller for controlling access to flash memories requiring sequential write.
  • Flash memories are one of semiconductor memories utilizing floating gate transistors to achieve nonvolatility of data.
  • a conventional flash memory data erasure is performed on a physical block basis, the physical block including a plurality of pages, and reading and writing of data are performed page by page. Even if a random write request is received, data write operation is controlled such that data is written in all erased pages of the physical block sequentially from the first page.
  • sequential write access is controlled in accordance with mapping from logical (virtual) pages to physical pages.
  • Each of the pages includes a data area for storing data and a redundant area for storing data management information.
  • the redundant area of each page stores a logical page number (address) associated with data written in the data area of the same page (see Patent Publication 1) as data management information.
  • an object of the present invention is to identify a last valid page and make a judgment as to whether or not an error page resulting from the power-down exists in a quick and accurate manner.
  • binary search is performed on the redundant areas of the pages to temporarily identify a last valid page. Then, the contents of every area (data areas and redundant areas) of the temporarily identified last valid page and a page adjacent thereto are checked to finally identify the last valid page and make a judgment as to whether or not an error page resulting from the power-down exists.
  • the present invention relates to a memory controller for controlling access to a flash memory having a physical block including a plurality of pages, each of the pages having a data area for storing data and a redundant area for storing data management information.
  • the memory controller includes: a page write unit for writing data in the data areas and writing information for correcting an error of the data and status information indicating that the data has been written as the data management information in the redundant areas sequentially from the first page of all erased pages of the physical block; a binary search unit for reading the status information in the redundant areas of the pages through a binary search to temporarily identify a last valid page; and a last valid data identification unit for reading the data from the data areas and the data management information from the redundant areas of the last valid page temporarily identified by the binary search unit and a page adjacent to the temporarily identified last valid page to finally identify the last valid page and make a judgment as to whether an error page resulting from power-down during the operation of the page write unit exists or not based on the results of checking each page as to whether or not an uncorrect
  • a memory controller for the flash memory may include: a page write unit for writing data in the data areas and writing information for correcting an error of the data and status information indicating that the data has been written as the data management information in the redundant areas sequentially on a segment-by-segment basis from the first segment of all erased segments of the physical unit, each of the segments including a predetermined number of pages of the physical block; a binary search unit for reading the status information in the redundant areas of the first pages of the segments through a binary search to temporarily identify a last valid segment; and a last valid data identification unit for reading the data from the data areas and the data management information from the redundant areas of every page belonging to the last valid segment temporarily identified by the binary search unit and every page belonging to a segment adjacent to the temporarily identified last valid page to finally identify the last valid segment and make a judgment as to whether an error segment resulting from power-down during the
  • the identification of a true last valid page and the judgment as to whether or not an error page resulting from the power-down exists are carried out in a quick and accurate manner.
  • the identification of a true last valid segment and the judgment as to whether or not an error segment resulting from the power-down exists are achieved in a quick and accurate manner.
  • Figure 1 illustrates an example of the configuration of a system including a memory card provided with a memory controller and a flash memory according to the present invention.
  • the system of Figure 1 is a nonvolatile memory system including a memory card 101 which is one of nonvolatile memory devices and a host 102 which requests access to the memory card 101.
  • the host 102 may be a cellular phone, a digital still camera, a personal computer or a portable digital music player.
  • the nonvolatile memory device is not limited to those in the form of a card such as the memory card 101 as long as it is used as a recording medium for the host 102.
  • the host 102 is a cellular phone provided with a slot into which the memory card 101 is inserted.
  • the memory card 101 is inserted into the slot of the host 102 to communicate with the host 102.
  • the communication between the memory card 101 and the host 102 is that of a master-slave type with the host 102 serving as the master and the memory card 101 as the slave.
  • the memory card 101 includes a memory controller 103 and a flash memory 104, access to which is controlled by the memory controller 103.
  • the flash memory 104 may be a NAND flash memory requiring sequential write as described above. It may be a binary flash memory in which a single memory cell has one of two values 0 and 1, or a multivalued flash memory in which a single memory cell has one of four values 00, 01, 10 and 11.
  • the memory controller 103 and the flash memory 104 may be configured as individual LSI chips, respectively, or may be integrated into a single LSI chip.
  • the memory controller 103 includes an input/output unit 105, a RAM (random access memory) control unit 106, a transfer RAM 107, a table RAM 108, a CPU (central processing unit) 109, a flash control unit 110 and an ECC (error correcting code) circuit 111.
  • the input/output unit 105 receives command signals and data signals sent from the host 102 and transmits response signals and data signals to the host 102. Upon receiving a data signal from the host 102, the input/output unit 105 transfers the data signal to the transfer RAM 107 to temporarily store the signal therein and outputs an interrupt signal to the CPU 109. To send the data to the host 102, the data stored in the transfer RAM 107 is output to the host 102.
  • the RAM control unit 106 performs switching between access to the transfer RAM 107 and access to the table RAM 108 based on the setting of the CPU 109. Based on the setting of the RAM control unit 106, the CPU 109 and the flash control unit 110 are allowed to access both of the transfer RAM 107 and the table RAM 108.
  • the input/output unit 105 is able to access the transfer RAM 107.
  • the transfer RAM 107 temporarily stores data transferred from the host 102 and data that the flash control unit 110 read out of the flash memory 104.
  • the table RAM 108 stores write information of the flash memory 104.
  • the write information is information about the status of usage of the physical block (whether it has been written or virgin), an address conversion table indicating the correspondence between a logical address and a physical address and an address of a last valid page in the physical block during writing, etc.
  • the information stored in the table RAM 108 is created when the flash control unit 110 accesses the flash memory 104 during the initialization period before reading/writing data from/in the memory card 101 after the memory card 101 is turned on and updated when data from the host 102 is received after the initialization or an erase command is received.
  • the information as to whether or not the physical block is virgin is easily created by reading the first page of the physical block to check whether the data has been written or not.
  • the CPU 109 reads/writes data from/in the transfer RAM 107 and the table RAM 108 via the RAM control unit 106. If the command signal and the data signal are not sent from the host 102 for a certain period, blocks other than an interrupt control unit in the CPU 109 are suspended until an interrupt signal is sent from the input/output unit 105, thereby assisting power saving function. In order that the CPU 109 accesses the flash memory 104, a certain operation command is sent to the flash control unit 110 to achieve the access.
  • the operation command may be a command to erase data from the physical block, a command to write data in pages of the physical block, a command to read data out of the redundant areas through a binary search and a command to read data out of every area of the pages to identify a last valid page and make a judgment as to whether or not power-down has occurred, etc.
  • the flash control unit 110 includes a block erasure unit 112, a page write unit 113, a binary search unit 114 and a last valid data identification unit 115.
  • the units 112 to 115 operate in response to a command from the CPU 109 to access the flash memory 104 for the purpose of reading, writing and erasing.
  • the block erasure unit 112 erases data from a specified physical block of the flash memory 104.
  • the page write unit 113 reads data from the transfer RAM 107, adds a syndrome for error correction thereto and write the data in a predetermined page of the physical block.
  • the syndrome for error correction is written in the redundant area of the predetermined page and a mark "Low" indicating that the data has been written is placed in a bit corresponding to the write status information in the redundant area.
  • the binary search unit 114 reads data out of the redundant areas of the target physical block through a binary search to temporarily identify a last valid page (details are described later).
  • the binary search unit 114 may read only the write status information in the redundant areas.
  • the last valid data identification unit 115 reads the contents of every area of a predetermined page in the physical block and stores the data in the transfer RAM 107 via the ECC circuit 111. Then, based on whether or not an uncorrectable error has occurred, the last valid page is finally identified and a judgment is made as to whether or not the power-down has occurred (details are described later).
  • the ECC circuit 111 generates a syndrome for error correction with respect to data written in the flash memory 104 and performs detection and correction of error with respect to data read out of the flash memory 104.
  • an uncorrectable error signal is issued by the ECC circuit 111. If the ECC circuit 111 detects an uncorrectable error in the data read out of a certain page, it means that the page is an error page where the power-down has occurred.
  • Figure 2 shows an example of the internal configuration of the flash memory 104 shown in Figure 1 . While the flash memory 104 of Figure 1 includes a plurality of physical blocks, Figure 2 shows only a single physical block 201 for explanation purpose.
  • the physical block 201 shown in Figure 2 is consisted of 32 physical pages including page 0 to page 31.
  • each of the pages includes a data area (DA) 202 of 512 bytes and a redundant area (RA) 203 of 16 bytes.
  • the data area 202 is mainly used to store data transferred from the host 102.
  • the redundant area 203 is used to store data management information such an ECC syndrome, page offset and status information indicating that the data has been written.
  • Figure 3 shows the operation of the binary search unit 114 shown in Figure 1 with the configuration of Figure 2 adopted thereto.
  • the physical block 201 to be searched for the last valid page it is supposed that data is always written at least in page 0.
  • variable n representing the number of readings is set to 1 in step 301.
  • variable M representing an address of a page to be read is set to a value "the total number of pages of the physical block 201 / 2".
  • the redundant area 203 of page M is read in step 303. Based on the write status information in the data management information read out of the redundant area 203 of page M, a judgment is made as to whether or not data has been written. If the bit of the write status information is "Low”, it means that the data has been written. If it is "High”, it means that the data has not been written.
  • step 304 variable n is incremented by 1. Then, in step 305, a judgment is made as to whether or not "the total number of pages of the physical block 201 ⁇ 2 n " is met.
  • the step 305 is a termination condition for a loop operation from step 303 to step 307 or 308 to be described later.
  • step 306 If "Yes” is selected in step 305, the flow proceeds to step 306. If it is found in step 306 that the status information read in step 303 indicates that the data has been written, the flow proceeds to step 307. In step 307, variable M is increased by "the total number of pages of the physical block 201 / 2 n ". Alternatively, if it is found in step 306 that the status information read in step 303 indicates that the data has not been written, the flow proceeds to step 308. In step 308, variable M is decreased by "the total number of pages of the physical block 201 / 2 n ". After step 307 or 308, the flow returns to step 303 to repeat the processing.
  • step 309 If "No" is selected in step 305, the flow proceeds to step 309. If it is found in step 309 that the status information read in step 303 indicates that the data has been written, the flow proceeds to step 310. In step 310, page M is temporarily identified as a last valid page. Alternatively, if it is found in step 309 that the status information read in step 303 indicates that the data has not been written, the flow proceeds to step 311. In step 311, page (M-1) is temporarily identified as a last valid page.
  • Figure 4 shows the operation of the last valid data identification unit 115 of Figure 1 with the configuration of Figure 2 adopted thereto. In this case, it is assumed that the temporary identification of the last valid page by the binary search unit 114 has already been done.
  • step 401 the last valid page temporarily identified by the binary search unit 114 is regarded as page N.
  • step 402 the contents of every area (the data area 202 and the redundant area 203 ) of page N are read and temporarily stored in the transfer RAM 107 via the ECC circuit 111.
  • step 403 a judgment is made as to whether or not an uncorrectable error has occurred in page N. If it is judged that the uncorrectable error has not occurred in page N, the flow proceeds to step 404.
  • step 404 data is read out of every area of page (N+1) to make a judgment as to whether or not page (N+1) is an error page.
  • step 405 a judgment is made as to whether or not data has been erased from (has not been written in) the data area 202 of page (N+1). If the data has been erased from page (N+1), the flow proceeds to step 406. This is the case where the physical block 201 does not include any error page resulting from the power-down. In step 406, page N is finally identified as the last valid page and it is judged that the power-down has not occurred in the physical block 201.
  • step 405 If it is judged in step 405 that data has been written in the data area 202 of page (N+1), the flow proceeds to step 407.
  • page (N+1) since the data area 202 has been written while the redundant area 203 has been erased, this is judged as an abnormal state resulting from the power-down.
  • step 407 page N is finally identified as the last valid page and it is judged that the power-down has occurred while the data is written in page (N+1).
  • step 403 If it is judged in step 403 that the uncorrectable error has occurred in page N, the flow proceeds to step 408.
  • page N since the data area 202 has been written while the redundant area 203 has been erased, this is judged as an abnormal state resulting from the power-down. However, it is also necessary to make a judgment as to whether or not the uncorrectable error has occurred in page (N-1).
  • step 408 data is read out of every area of page (N-1).
  • step 409 If it is judged in step 409 that the uncorrectable error has not occurred in page (N-1), the flow proceeds to step 410.
  • step 410 page (N-1) is identified as a true last valid page and it is judged that the power-down has occurred while the data is written in page N.
  • step 409 If it is judged in step 409 that the uncorrectable error has occurred in page (N-1), the flow proceeds to step 411. This is the case where the uncorrectable error has occurred in both of pages N and (N-1). Since this is an abnormal state and will not be caused by a single power-down, it is judged that no valid page exists in the physical block 201 and the processing is terminated.
  • page 20 is temporarily identified as the last valid page. Then, data is read out of every area (the data areas 202 and the redundant areas 203 ) of (i) page 20 and (ii) page 21 in this order. Thus, page 20 is finally identified as the last valid page and it is judged that the power-down has not occurred in the physical block 201.
  • the CPU 109 After the identification of the last valid page, the CPU 109 updates the information of the table RAM 108. However, if the writing is performed in pages downstream of the page where the power-down has occurred, data corruption may possibly occur and data writing cannot be controlled properly. Therefore, if the uncorrectable error resulting from the power-down is detected, valid data is copied into another erased physical block before updating the information of the table RAM 108.
  • FIG. 5 shows the operation of the binary search unit 114 according to a modification of Figure 3 .
  • information is read out of the redundant area 203 of a first page (page 0) of the physical block 201 in step 501.
  • a judgment is made in step 502 as to whether or not data has been erased from (has not been written in) page 0. If it is found in step 502 that the data has been erased, the flow proceeds to step 503, where page 0 is temporarily identified as the last valid page and the operation is terminated. After page 0 is temporarily identified as the last valid page in such a quick manner, the last valid data identification unit 115 operates as indicated in the flowchart of Figure 4 .
  • the binary search unit 114 proceeds to the flow starting from step 301 shown in Figure 3 .
  • Figure 6 shows another internal configuration of the flash memory 104 shown in Figure 1 .
  • four physical blocks A, B, C and D constitute a single physical unit 601.
  • Each of the physical blocks A, B, C and D contains segments made of 8 pages and data writing is performed segment by segment.
  • the four physical blocks A, B, C and D include 128 pages, respectively. That is, the physical unit 601 of Figure 6 includes 16 segments from segment 0 to segment 15.
  • Each of the pages includes a data area (DA) and a redundant area (RA) just like the example shown in Figure 2 .
  • DA data area
  • RA redundant area
  • the page write unit 113 of Figure 1 operates in the following manner. Data writing into the physical unit 601 is always performed segment by segment irrespective of the byte count transferred from the host 102. Each of the segments is made of 8 pages. Write status information of each segment is stored at least in the redundant area of the first page in the segment.
  • the data when data is transferred from the host 102, the data is first written in page 0 of the physical block A. Then, the data is sequentially written in pages 0 of the physical blocks B, C and D in this order. After the data is written in the pages 0 of the physical blocks A to D, the data is sequentially written in pages 1 of the physical blocks A, B, C and D in this order. If the data transfer from the host 102 is stopped after the data is written in page 1 of the physical block B, data having "1" in every bit is written or original data is copied into the rest of the pages.
  • the last valid segment is a segment which is written most recently among the segments in the physical unit 601 and does not contain any uncorrectable error.
  • Figure 7 shows the operation of the binary search unit 114 of Figure 1 with the configuration of Figure 6 adopted thereto.
  • the physical unit 601 to be searched for the last valid segment it is supposed that the data is always written in at least segment 0.
  • variable n representing the number of readings is set to 1 in step 701.
  • variable L representing an address of a segment to be read is set to a value "the total number of segments of the physical unit 601 / 2".
  • the redundant area of the first page of segment L is read in step 703. Based on the write status information in the data management information read out of the redundant area of the first page of segment L, a judgment is made as to whether or not data has been written. If the bit of the write status information is "Low”, it means that the data has been written. If it is "High”, it means that the data has not been written.
  • step 704 variable n is incremented by 1. Then, in step 705, a judgment is made as to whether or not "the total number of segments of the physical unit 601 ⁇ 2 n " is met.
  • the step 705 is a termination condition for a loop operation from step 703 to step 707 or 708 to be described later.
  • step 705 If “Yes” is selected in step 705, the flow proceeds to step 706. If it is found in step 706 that the status information read in step 703 indicates that the data has been written, the flow proceeds to step 707. In step 707, variable L is increased by "the total number of segments of the physical unit 601 / 2 n ". Alternatively, if it is found in step 706 that the status information read in step 703 indicates that the data has not been written, the flow proceeds to step 708. In step 708, variable L is decreased by "the total number of segments of the physical unit 601 / 2 n ". After step 707 or 708, the flow returns to step 703 to repeat the processing.
  • step 705 If "No” is selected in step 705, the flow proceeds to step 709. If it is found in step 709 that the status information read in step 703 indicates that the data has been written, the flow proceeds to step 710. In step 710, segment L is temporarily identified as a last valid segment. Alternatively, if it is found in step 709 that the status information read in step 703 indicates that the data has not been written, the flow proceeds to step 711. In step 711, segment (L-1) is temporarily identified as a last valid segment.
  • segment 9 is temporarily identified as the last valid segment.
  • Figure 8 shows the operation of the last valid data identification unit 115 of Figure 1 with the configuration of Figure 6 adopted thereto. In this case, it is assumed that the temporary identification of the last valid segment by the binary search unit 114 has already been done.
  • step 801 the last valid segment temporarily identified by the binary search unit 114 is regarded as segment N.
  • step 802 the contents of every area (the data areas and the redundant areas) of every page in segment N are sequentially read and temporarily stored in the transfer RAM 107 via the ECC circuit 111.
  • step 803 a judgment is made as to whether or not an uncorrectable error has occurred in segment N. If it is judged that the uncorrectable error has not occurred in any page of segment N, the flow proceeds to step 804.
  • step 804 data is read out of every area of every page in segment (N+1) to make a judgment as to whether or not segment (N+1) is an error segment.
  • step 805 a judgment is made as to whether or not data has been erased from (has not been written in) the data areas of every page in segment (N+1). If it is found that the data has been erased from segment (N+1), the flow proceeds to step 806. This is the case where the physical unit 601 does not include any error segment resulting from the power-down. In step 806, segment N is finally identified as the last valid segment and it is judged that the power-down has not occurred in the physical unit 601.
  • step 805 If it is judged in step 805 that data has been written in the data areas of segment (N+1), the flow proceeds to step 807.
  • segment (N+1) since the data areas have been written while the redundant areas have been erased, this is judged as an abnormal state resulting from the power-down.
  • step 807 segment N is finally identified as the last valid segment and it is judged that the power-down has occurred while the data is written in segment (N+1).
  • step 803 If it is judged in step 803 that the uncorrectable error has occurred in segment N, the flow proceeds to step 808.
  • segment N since the data areas have been written while the redundant areas have been erased, this is judged as an abnormal state resulting from the power-down. However, it is also necessary to make a judgment as to whether or not the uncorrectable error has occurred in segment (N-1).
  • step 808 data is read out of every area of every page in segment (N-1).
  • step 809 if it is judged in step 809 that the uncorrectable error has not occurred in segment (N-1), the flow proceeds to step 810.
  • step 810 segment (N-1) is identified as a true last valid segment and it is judged that the power-down has occurred while the data is written in segment N.
  • step 809 If it is judged in step 809 that the uncorrectable error has occurred in segment (N-1), the flow proceeds to step 811. This is the case where the uncorrectable error has occurred in both of segments N and (N-1). Since this is an abnormal state and will not be caused by a single power-down, it is judged that no valid segment exists in the physical unit 601 and the processing is terminated.
  • segment 9 is temporarily identified as the last valid segment. Then, data is read out of every area (the data areas and the redundant areas) of every page in (i) segment 9 and (ii) segment 10 in this order. Thus, segment 9 is finally identified as the last valid segment and it is judged that the power-down has not occurred in the physical unit 601.
  • the CPU 109 After the identification of the last valid segment, the CPU 109 updates the information of the table RAM 108. However, if the writing is performed in segments downstream of the segment where the power-down has occurred, data corruption may possibly occur and data writing cannot be controlled properly. Therefore, if the uncorrectable error resulting from the power-down is detected, valid data is copied into another erased physical unit before updating the information of the table RAM 108.
  • the memory controller of the present invention makes it possible to identify a last valid page or segment and make a judgment as to whether or not an error page or segment resulting from power-down exists in a quick and accurate manner.
  • the invention is useful as a technique for controlling access to flash memories requiring sequential write.

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Quality & Reliability (AREA)
  • Techniques For Improving Reliability Of Storages (AREA)
  • Read Only Memory (AREA)
EP06798153A 2006-03-13 2006-09-20 Controleur de memoire flash Not-in-force EP2003569B1 (fr)

Applications Claiming Priority (2)

Application Number Priority Date Filing Date Title
JP2006067385 2006-03-13
PCT/JP2006/318597 WO2007119267A1 (fr) 2006-03-13 2006-09-20 Controleur de memoire flash

Publications (4)

Publication Number Publication Date
EP2003569A2 true EP2003569A2 (fr) 2008-12-17
EP2003569A9 EP2003569A9 (fr) 2009-04-15
EP2003569A4 EP2003569A4 (fr) 2009-04-22
EP2003569B1 EP2003569B1 (fr) 2010-06-02

Family

ID=38609089

Family Applications (1)

Application Number Title Priority Date Filing Date
EP06798153A Not-in-force EP2003569B1 (fr) 2006-03-13 2006-09-20 Controleur de memoire flash

Country Status (7)

Country Link
US (1) US8006030B2 (fr)
EP (1) EP2003569B1 (fr)
JP (1) JP4524309B2 (fr)
CN (1) CN101288056A (fr)
DE (1) DE602006014734D1 (fr)
TW (1) TW200736909A (fr)
WO (1) WO2007119267A1 (fr)

Families Citing this family (54)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP5142685B2 (ja) * 2007-11-29 2013-02-13 株式会社東芝 メモリシステム
US8413016B2 (en) * 2009-04-28 2013-04-02 Panasonic Corporation Nonvolatile memory device and controller for judging a normal or anomalous condition of an error-corrected bit pattern
CN101587744B (zh) * 2009-06-19 2011-11-23 上海微小卫星工程中心 一种大规模flash存储阵列的多层次数据冗余方法
JP4818404B2 (ja) * 2009-06-26 2011-11-16 株式会社東芝 素材サーバおよび素材蓄積方法
TWI425513B (zh) * 2009-08-13 2014-02-01 Silicon Motion Inc 識別快閃記憶體中區塊之資料頁的方法以及相關之記憶裝置
CN102103558B (zh) * 2009-12-18 2013-09-18 上海华虹集成电路有限责任公司 一种带有写重传功能的多通道NANDflash控制器
TWI447739B (zh) * 2010-03-22 2014-08-01 Phison Electronics Corp 錯誤校正方法、記憶體控制器與儲存系統
TWI451435B (zh) * 2010-10-08 2014-09-01 Phison Electronics Corp 非揮發性記憶體儲存裝置、記憶體控制器與資料儲存方法
US8683113B2 (en) * 2011-02-04 2014-03-25 Western Digital Technologies, Inc. Concurrently searching multiple devices of a non-volatile semiconductor memory
JP5643708B2 (ja) * 2011-03-30 2014-12-17 株式会社ケーヒン 電子制御装置
US9098399B2 (en) 2011-08-31 2015-08-04 SMART Storage Systems, Inc. Electronic system with storage management mechanism and method of operation thereof
US9063844B2 (en) 2011-09-02 2015-06-23 SMART Storage Systems, Inc. Non-volatile memory management system with time measure mechanism and method of operation thereof
CN102411548B (zh) * 2011-10-27 2014-09-10 忆正存储技术（武汉）有限公司 闪存控制器以及闪存间数据传输方法
CN102609334B (zh) * 2012-01-09 2016-05-04 晨星软件研发(深圳)有限公司 非易失闪存擦除异常存储块修复方法和装置
US9239781B2 (en) 2012-02-07 2016-01-19 SMART Storage Systems, Inc. Storage control system with erase block mechanism and method of operation thereof
WO2013171806A1 (fr) * 2012-05-18 2013-11-21 Hitachi, Ltd. Dispositif de stockage semi-conducteur et procédé de commande d'une mémoire non volatile
US9671962B2 (en) 2012-11-30 2017-06-06 Sandisk Technologies Llc Storage control system with data management mechanism of parity and method of operation thereof
CN103020323B (zh) * 2013-01-15 2016-01-20 山东大学 一种基于未知长度二分查找的闪存数据检索存储的方法
US9123445B2 (en) 2013-01-22 2015-09-01 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US9329928B2 (en) 2013-02-20 2016-05-03 Sandisk Enterprise IP LLC. Bandwidth optimization in a non-volatile memory system
US9214965B2 (en) 2013-02-20 2015-12-15 Sandisk Enterprise Ip Llc Method and system for improving data integrity in non-volatile storage
US9183137B2 (en) 2013-02-27 2015-11-10 SMART Storage Systems, Inc. Storage control system with data management mechanism and method of operation thereof
US9183081B2 (en) * 2013-03-12 2015-11-10 Sandisk Technologies Inc. Systems and methods for performing defect detection and data recovery in a memory system
JP5695112B2 (ja) * 2013-03-18 2015-04-01 富士通テン株式会社 データ記憶装置、データの記憶方法および車載用制御装置
US9170941B2 (en) 2013-04-05 2015-10-27 Sandisk Enterprises IP LLC Data hardening in a storage system
US10049037B2 (en) 2013-04-05 2018-08-14 Sandisk Enterprise Ip Llc Data management in a storage system
US9543025B2 (en) * 2013-04-11 2017-01-10 Sandisk Technologies Llc Storage control system with power-off time estimation mechanism and method of operation thereof
US10546648B2 (en) 2013-04-12 2020-01-28 Sandisk Technologies Llc Storage control system with data management mechanism and method of operation thereof
US9244519B1 (en) 2013-06-25 2016-01-26 Smart Storage Systems. Inc. Storage system with data transfer rate adjustment for power throttling
US9367353B1 (en) 2013-06-25 2016-06-14 Sandisk Technologies Inc. Storage control system with power throttling mechanism and method of operation thereof
US9146850B2 (en) 2013-08-01 2015-09-29 SMART Storage Systems, Inc. Data storage system with dynamic read threshold mechanism and method of operation thereof
US9431113B2 (en) 2013-08-07 2016-08-30 Sandisk Technologies Llc Data storage system with dynamic erase block grouping mechanism and method of operation thereof
US9448946B2 (en) 2013-08-07 2016-09-20 Sandisk Technologies Llc Data storage system with stale data mechanism and method of operation thereof
US9361222B2 (en) 2013-08-07 2016-06-07 SMART Storage Systems, Inc. Electronic system with storage drive life estimation mechanism and method of operation thereof
US9152555B2 (en) 2013-11-15 2015-10-06 Sandisk Enterprise IP LLC. Data management with modular erase in a data storage system
CN103778964B (zh) * 2013-12-30 2016-08-17 上海晨思电子科技有限公司 一种NAND Flash烧写数据的处理、使用方法及装置、系统
CN105808153B (zh) * 2014-12-31 2018-11-13 深圳市硅格半导体有限公司 存储系统及其读写操作方法
KR102547642B1 (ko) * 2016-05-18 2023-06-28 에스케이하이닉스 주식회사 메모리 시스템 및 메모리 시스템의 동작방법
CN107544925B (zh) * 2016-06-24 2020-05-08 爱思开海力士有限公司 存储器系统及加速引导时间的方法
JP7109949B2 (ja) * 2018-03-23 2022-08-01 キオクシア株式会社 メモリシステム及びメモリシステムの制御方法
JP7030636B2 (ja) * 2018-07-12 2022-03-07 キオクシア株式会社 メモリシステムおよびその制御方法
JP2020021385A (ja) * 2018-08-03 2020-02-06 キオクシア株式会社 メモリシステム
TWI696951B (zh) * 2018-08-31 2020-06-21 威剛科技股份有限公司 儲存裝置異常斷電的處理系統和方法
JP2020047834A (ja) 2018-09-20 2020-03-26 キオクシア株式会社 記憶装置
JP7017495B2 (ja) * 2018-10-15 2022-02-08 ハギワラソリューションズ株式会社 フラッシュメモリの管理方法
JP6708762B1 (ja) * 2019-01-29 2020-06-10 ウィンボンド エレクトロニクス コーポレーション 半導体記憶装置
CN111949426B (zh) * 2019-05-16 2024-09-17 兆易创新科技集团股份有限公司 一种固件程序错误的检测方法、装置及存储设备
TWI745695B (zh) * 2019-05-22 2021-11-11 慧榮科技股份有限公司 用來進行無預警斷電復原管理之方法、記憶裝置及其控制器以及電子裝置
CN112099985B (zh) 2019-06-17 2023-09-12 慧荣科技股份有限公司 数据储存装置以及非挥发式存储器控制方法
CN112100087B (zh) 2019-06-17 2024-04-02 慧荣科技股份有限公司 数据储存装置以及非挥发式存储器控制方法
CN112130750B (zh) * 2019-06-25 2023-11-07 慧荣科技股份有限公司 数据储存装置以及非挥发式存储器控制方法
CN110764693B (zh) * 2019-09-12 2023-03-28 深圳市德明利技术股份有限公司 一种提高Nand flash数据稳定性的方法以及装置
JP7500365B2 (ja) * 2020-09-14 2024-06-17 キオクシア株式会社 メモリシステム
CN114116309B (zh) * 2021-11-19 2023-04-14 合肥康芯威存储技术有限公司 一种存储器的数据存取方法及系统

Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2256735A (en) * 1991-06-12 1992-12-16 Intel Corp Non-volatile disk cache.
US20030189860A1 (en) * 2001-06-28 2003-10-09 Akio Takeuchi Non-volatile memory control method
DE10322723B3 (de) * 2003-05-20 2004-10-14 Infineon Technologies Ag Vorrichtung und Verfahren zum Behandeln eines Zustands eines Speichers

Family Cites Families (8)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP2002073425A (ja) * 2000-08-31 2002-03-12 Hitachi Ltd 媒体再生装置
US7240178B2 (en) * 2001-07-25 2007-07-03 Sony Corporation Non-volatile memory and non-volatile memory data rewriting method
US6678785B2 (en) 2001-09-28 2004-01-13 M-Systems Flash Disk Pioneers Ltd. Flash management system using only sequential write
WO2004021191A1 (fr) 2002-08-29 2004-03-11 Matsushita Electric Industrial Co., Ltd. Memoire a semi-conducteurs et procede d'enregistrement de donnees dans une memoire flash
US7003532B2 (en) * 2002-11-27 2006-02-21 Microsoft Corporation System and method for scaleable multiplexed transactional log recovery
US6988175B2 (en) * 2003-06-30 2006-01-17 M-Systems Flash Disk Pioneers Ltd. Flash memory management method that is resistant to data corruption by power loss
JP2006285600A (ja) * 2005-03-31 2006-10-19 Tokyo Electron Device Ltd 記憶装置、メモリ管理装置、メモリ管理方法及びプログラム
US7747903B2 (en) * 2007-07-09 2010-06-29 Micron Technology, Inc. Error correction for memory

Patent Citations (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
GB2256735A (en) * 1991-06-12 1992-12-16 Intel Corp Non-volatile disk cache.
US20030189860A1 (en) * 2001-06-28 2003-10-09 Akio Takeuchi Non-volatile memory control method
DE10322723B3 (de) * 2003-05-20 2004-10-14 Infineon Technologies Ag Vorrichtung und Verfahren zum Behandeln eines Zustands eines Speichers

Non-Patent Citations (1)

* Cited by examiner, † Cited by third party
Title
See also references of WO2007119267A1 *

Also Published As

Publication number Publication date
DE602006014734D1 (de) 2010-07-15
US8006030B2 (en) 2011-08-23
WO2007119267A1 (fr) 2007-10-25
EP2003569A4 (fr) 2009-04-22
TW200736909A (en) 2007-10-01
JP4524309B2 (ja) 2010-08-18
JPWO2007119267A1 (ja) 2009-08-27
US20090228634A1 (en) 2009-09-10
CN101288056A (zh) 2008-10-15
EP2003569B1 (fr) 2010-06-02
EP2003569A9 (fr) 2009-04-15

Similar Documents

Publication Publication Date Title
US8006030B2 (en) Memory controller for identifying the last valid page/segment in a physical block of a flash memory
CN109634517B (zh) 进行存取管理的方法、记忆装置、电子装置和其控制器
CN111078149B (zh) 存储器管理方法、存储器存储装置及存储器控制电路单元
US8185685B2 (en) NAND flash module replacement for DRAM module
CN110908925B (zh) 高效能垃圾收集方法以及数据存储装置及其控制器
CN106598479B (zh) 闪速存储器的故障安全擦除的方法和装置
US7350044B2 (en) Data move method and apparatus
US7937523B2 (en) Memory system with nonvolatile semiconductor memory
US7773420B2 (en) Memory card system including NAND flash memory and SRAM/NOR flash memory, and data storage method thereof
US20070214309A1 (en) Nonvolatile storage device and data writing method thereof
US20080250188A1 (en) Memory Controller, Nonvolatile Storage, Nonvolatile Storage System, and Memory Control Method
EP2115594A1 (fr) Systeme de memoire
KR20070076849A (ko) 메모리 카드의 카피백 동작을 수행하는 장치 및 방법
CN104731674B (zh) 使用mlc nvm存储电子系统固件的方法与设备
CN113885808B (zh) 映射信息记录方法以及存储器控制电路单元与存储装置
US9384125B2 (en) Method for accessing flash memory having pages used for data backup and associated memory device
US11055000B2 (en) Apparatuses and methods for counter update operations
US20120166706A1 (en) Data management method, memory controller and embedded memory storage apparatus using the same
JP2006338083A (ja) メモリコントローラ
US20130205066A1 (en) Enhanced write abort management in flash memory
CN102591738A (zh) 数据管理方法、存储器控制器与嵌入式存储器储存装置
US8312205B2 (en) Method for identifying a page of a block of flash memory, and associated memory device
CN107436729B (zh) 储存系统的控制装置及其储存空间回收方法
JP2005292925A (ja) メモリコントローラ、フラッシュメモリシステム、並びに、フラッシュメモリの制御方法
JP2008176606A (ja) メモリコントローラ及びメモリコントローラを備えるフラッシュメモリシステム、並びにフラッシュメモリの制御方法

Legal Events

Date Code Title Description
PUAI Public reference made under article 153(3) epc to a published international application that has entered the european phase

Free format text: ORIGINAL CODE: 0009012

17P Request for examination filed

Effective date: 20070503

AK Designated contracting states

Kind code of ref document: A2

Designated state(s): DE FR GB

PUAB Information related to the publication of an a document modified or deleted

Free format text: ORIGINAL CODE: 0009199EPPU

DAX Request for extension of the european patent (deleted)
RBV Designated contracting states (corrected)

Designated state(s): DE FR GB

A4 Supplementary search report drawn up and despatched

Effective date: 20090320

17Q First examination report despatched

Effective date: 20090617

GRAP Despatch of communication of intention to grant a patent

Free format text: ORIGINAL CODE: EPIDOSNIGR1

GRAS Grant fee paid

Free format text: ORIGINAL CODE: EPIDOSNIGR3

GRAA (expected) grant

Free format text: ORIGINAL CODE: 0009210

AK Designated contracting states

Kind code of ref document: B1

Designated state(s): DE FR GB

REG Reference to a national code

Ref country code: GB

Ref legal event code: FG4D

REF Corresponds to:

Ref document number: 602006014734

Country of ref document: DE

Date of ref document: 20100715

Kind code of ref document: P

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: DE

Payment date: 20101029

Year of fee payment: 5

PLBE No opposition filed within time limit

Free format text: ORIGINAL CODE: 0009261

STAA Information on the status of an ep patent application or granted ep patent

Free format text: STATUS: NO OPPOSITION FILED WITHIN TIME LIMIT

26N No opposition filed

Effective date: 20110303

REG Reference to a national code

Ref country code: DE

Ref legal event code: R097

Ref document number: 602006014734

Country of ref document: DE

Effective date: 20110302

PGFP Annual fee paid to national office [announced via postgrant information from national office to epo]

Ref country code: FR

Payment date: 20110922

Year of fee payment: 6

Ref country code: GB

Payment date: 20110914

Year of fee payment: 6

GBPC Gb: european patent ceased through non-payment of renewal fee

Effective date: 20120920

REG Reference to a national code

Ref country code: FR

Ref legal event code: ST

Effective date: 20130531

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: GB

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20120920

Ref country code: DE

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20130403

PG25 Lapsed in a contracting state [announced via postgrant information from national office to epo]

Ref country code: FR

Free format text: LAPSE BECAUSE OF NON-PAYMENT OF DUE FEES

Effective date: 20121001

REG Reference to a national code

Ref country code: DE

Ref legal event code: R119

Ref document number: 602006014734

Country of ref document: DE

Effective date: 20130403